Changeset 0abc2ae in mainline for kernel/arch/arm32/include/arch/barrier.h

Timestamp:

2018-08-13T00:11:39Z (6 years ago)

Author:

Jiří Zárevúcky <jiri.zarevucky@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

f34d2be

Parents:

05882233

Message:

Remove single-argument version of smc_coherence.

File:

• kernel/arch/arm32/include/arch/barrier.h (modified) (1 diff)

kernel/arch/arm32/include/arch/barrier.h

@@ -117 +117 @@
  */
 
-#if defined PROCESSOR_ARCH_armv7_a | defined PROCESSOR_ARCH_armv6 | defined KERNEL
-//TODO might be PL1 only on armv5-
-#define smc_coherence(a) \
-do { \
-        dcache_clean_mva_pou(ALIGN_DOWN((uintptr_t) a, CP15_C7_MVA_ALIGN)); \
-        write_barrier();               /* Wait for completion */\
-        icache_invalidate();\
-        inst_barrier();                /* Wait for Inst refetch */\
-} while (0)
+#ifdef KERNEL
+
 /*
  * @note: Cache type register is not available in uspace. We would need
  * to export the cache line value, or use syscall for uspace smc_coherence
  */
-#define smc_coherence_block(a, l) \
+#define smc_coherence(a, l) \
 do { \
         for (uintptr_t addr = (uintptr_t) a; addr < (uintptr_t) a + l; \
             addr += CP15_C7_MVA_ALIGN) \
-                smc_coherence(addr); \
+                dcache_clean_mva_pou(ALIGN_DOWN((uintptr_t) a, CP15_C7_MVA_ALIGN)); \
+        write_barrier();               /* Wait for completion */\
+        icache_invalidate();\
+        write_barrier();\
+        inst_barrier();                /* Wait for Inst refetch */\
 } while (0)
-#else
-#define smc_coherence(a)
-#define smc_coherence_block(a, l)
+
 #endif