Changeset 0abc2ae in mainline


Ignore:
Timestamp:
2018-08-13T00:11:39Z (6 years ago)
Author:
Jiří Zárevúcky <jiri.zarevucky@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
f34d2be
Parents:
05882233
Message:

Remove single-argument version of smc_coherence.

Location:
kernel
Files:
13 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/abs32le/include/arch/barrier.h

    r05882233 r0abc2ae  
    4949#ifdef KERNEL
    5050
    51 #define smc_coherence(addr)
    52 #define smc_coherence_block(addr, size)
     51#define smc_coherence(addr, size)
    5352
    5453#endif  /* KERNEL*/

  • kernel/arch/arm32/include/arch/barrier.h

    r05882233 r0abc2ae  
    117117 */
    118118
    119 #if defined PROCESSOR_ARCH_armv7_a | defined PROCESSOR_ARCH_armv6 | defined KERNEL
    120 //TODO might be PL1 only on armv5-
    121 #define smc_coherence(a) \
    122 do { \
    123         dcache_clean_mva_pou(ALIGN_DOWN((uintptr_t) a, CP15_C7_MVA_ALIGN)); \
    124         write_barrier();               /* Wait for completion */\
    125         icache_invalidate();\
    126         inst_barrier();                /* Wait for Inst refetch */\
    127 } while (0)
     119#ifdef KERNEL
     120
    128121/*
    129122 * @note: Cache type register is not available in uspace. We would need
    130123 * to export the cache line value, or use syscall for uspace smc_coherence
    131124 */
    132 #define smc_coherence_block(a, l) \
     125#define smc_coherence(a, l) \
    133126do { \
    134127        for (uintptr_t addr = (uintptr_t) a; addr < (uintptr_t) a + l; \
    135128            addr += CP15_C7_MVA_ALIGN) \
    136                 smc_coherence(addr); \
     129                dcache_clean_mva_pou(ALIGN_DOWN((uintptr_t) a, CP15_C7_MVA_ALIGN)); \
     130        write_barrier();               /* Wait for completion */\
     131        icache_invalidate();\
     132        write_barrier();\
     133        inst_barrier();                /* Wait for Inst refetch */\
    137134} while (0)
    138 #else
    139 #define smc_coherence(a)
    140 #define smc_coherence_block(a, l)
     135
    141136#endif
    142137

  • kernel/arch/arm32/src/exception.c

    r05882233 r0abc2ae  
    7575        /* Make it LDR instruction and store at exception vector */
    7676        *vector = handler_address_ptr | LDR_OPCODE;
    77         smc_coherence(vector);
     77        smc_coherence(vector, 4);
    7878
    7979        /* Store handler's address */

  • kernel/arch/ia32/include/arch/barrier.h

    r05882233 r0abc2ae  
    106106 * sufficient for them to drain to the D-cache).
    107107 */
    108 #define smc_coherence(a)           write_barrier()
    109 #define smc_coherence_block(a, l)  write_barrier()
     108#define smc_coherence(a, l)  write_barrier()
    110109
    111110#endif  /* KERNEL */

  • kernel/arch/ia64/include/arch/barrier.h

    r05882233 r0abc2ae  
    5858#ifdef KERNEL
    5959
    60 #define smc_coherence(a)        \
    61 {                               \
    62         fc_i((a));              \
    63         sync_i();               \
    64         srlz_i();               \
    65 }
    66 
    6760#define FC_INVAL_MIN            32
    68 #define smc_coherence_block(a, l)               \
     61#define smc_coherence(a, l)             \
    6962{                                               \
    7063        unsigned long i;                        \

  • kernel/arch/mips32/include/arch/barrier.h

    r05882233 r0abc2ae  
    4848#ifdef KERNEL
    4949
    50 #define smc_coherence(a)
    51 #define smc_coherence_block(a, l)
     50#define smc_coherence(a, l)
    5251
    5352#endif  /* KERNEL */

  • kernel/arch/mips32/src/debugger.c

    r05882233 r0abc2ae  
    213213        /* Set breakpoint */
    214214        *((sysarg_t *) cur->address) = 0x0d;
    215         smc_coherence(cur->address);
     215        smc_coherence(cur->address, 4);
    216216
    217217        irq_spinlock_unlock(&bkpoint_lock, true);
    … …  
    246246
    247247        ((uint32_t *) cur->address)[0] = cur->instruction;
    248         smc_coherence(((uint32_t *) cur->address)[0]);
     248        smc_coherence(((uint32_t *) cur->address)[0], 4);
    249249        ((uint32_t *) cur->address)[1] = cur->nextinstruction;
    250         smc_coherence(((uint32_t *) cur->address)[1]);
     250        smc_coherence(((uint32_t *) cur->address)[1], 4);
    251251
    252252        cur->address = (uintptr_t) NULL;
    … …  
    358358                        /* Set breakpoint on first instruction */
    359359                        ((uint32_t *) cur->address)[0] = 0x0d;
    360                         smc_coherence(((uint32_t *)cur->address)[0]);
     360                        smc_coherence(((uint32_t *)cur->address)[0], 4);
    361361
    362362                        /* Return back the second */
    363363                        ((uint32_t *) cur->address)[1] = cur->nextinstruction;
    364                         smc_coherence(((uint32_t *) cur->address)[1]);
     364                        smc_coherence(((uint32_t *) cur->address)[1], 4);
    365365
    366366                        cur->flags &= ~BKPOINT_REINST;
    … …  
    380380                /* Return first instruction back */
    381381                ((uint32_t *)cur->address)[0] = cur->instruction;
    382                 smc_coherence(cur->address);
     382                smc_coherence(cur->address, 4);
    383383
    384384                if (!(cur->flags & BKPOINT_ONESHOT)) {

  • kernel/arch/mips32/src/mips32.c

    r05882233 r0abc2ae  
    121121        /* Copy the exception vectors to the right places */
    122122        memcpy(TLB_EXC, (char *) tlb_refill_entry, EXCEPTION_JUMP_SIZE);
    123         smc_coherence_block(TLB_EXC, EXCEPTION_JUMP_SIZE);
     123        smc_coherence(TLB_EXC, EXCEPTION_JUMP_SIZE);
    124124        memcpy(NORM_EXC, (char *) exception_entry, EXCEPTION_JUMP_SIZE);
    125         smc_coherence_block(NORM_EXC, EXCEPTION_JUMP_SIZE);
     125        smc_coherence(NORM_EXC, EXCEPTION_JUMP_SIZE);
    126126        memcpy(CACHE_EXC, (char *) cache_error_entry, EXCEPTION_JUMP_SIZE);
    127         smc_coherence_block(CACHE_EXC, EXCEPTION_JUMP_SIZE);
     127        smc_coherence(CACHE_EXC, EXCEPTION_JUMP_SIZE);
    128128
    129129        /*

  • kernel/arch/ppc32/include/arch/barrier.h

    r05882233 r0abc2ae  
    6262 */
    6363
    64 NO_TRACE static inline void smc_coherence(void *addr)
    65 {
    66         asm volatile (
    67             "dcbst 0, %[addr]\n"
    68             "sync\n"
    69             "icbi 0, %[addr]\n"
    70             "sync\n"
    71             "isync\n"
    72             :: [addr] "r" (addr)
    73         );
    74 }
    75 
    76 NO_TRACE static inline void smc_coherence_block(void *addr, unsigned int len)
     64NO_TRACE static inline void smc_coherence(void *addr, unsigned int len)
    7765{
    7866        unsigned int i;

  • kernel/arch/riscv64/include/arch/barrier.h

    r05882233 r0abc2ae  
    4949#ifdef KERNEL
    5050
    51 #define smc_coherence(addr)
    52 #define smc_coherence_block(addr, size)
     51#define smc_coherence(addr, size)
    5352
    5453#endif /* KERNEL */

  • kernel/arch/sparc64/include/arch/barrier.h

    r05882233 r0abc2ae  
    116116#define FLUSH_INVAL_MIN  4
    117117
    118 #define smc_coherence(a) \
    119         do { \
    120                 write_barrier(); \
    121                 flush((a)); \
    122         } while (0)
    123 
    124 #define smc_coherence_block(a, l) \
     118#define smc_coherence(a, l) \
    125119        do { \
    126120                unsigned long i; \
    … …  
    133127#elif defined (US3)
    134128
    135 #define smc_coherence(a) \
    136         do { \
    137                 write_barrier(); \
    138                 flush_pipeline(); \
    139         } while (0)
    140 
    141 #define smc_coherence_block(a, l) \
     129#define smc_coherence(a, l) \
    142130        do { \
    143131                write_barrier(); \

  • kernel/generic/src/mm/backend_elf.c

    r05882233 r0abc2ae  
    334334                            PAGE_SIZE);
    335335                        if (entry->p_flags & PF_X) {
    336                                 smc_coherence_block((void *) kpage, PAGE_SIZE);
     336                                smc_coherence((void *) kpage, PAGE_SIZE);
    337337                        }
    338338                        km_temporary_page_put(kpage);
    … …  
    385385                    PAGE_SIZE - pad_lo - pad_hi);
    386386                if (entry->p_flags & PF_X) {
    387                         smc_coherence_block((void *) (kpage + pad_lo),
     387                        smc_coherence((void *) (kpage + pad_lo),
    388388                            PAGE_SIZE - pad_lo - pad_hi);
    389389                }

  • kernel/generic/src/synch/smc.c

    r05882233 r0abc2ae  
    5454        }
    5555
    56         smc_coherence_block((void *) va, size);
     56        smc_coherence((void *) va, size);
    5757        return 0;
    5858}
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