Changeset 005b765 in mainline for boot/arch/arm32/src/mm.c

Timestamp:

2013-01-24T22:07:06Z (11 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

03362fbd, 3acd1bb, d59c046

Parents:

6218d4b (diff), 24bead17 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge arm improvements.

Speed up boot by enabling caches early (but disable before jumping to kernel).
Add cycle counters on armv7.
Move bbxm dispc driver to uspace.
Add arm PROCESSOR and PROCESSOR_ARCH defines.

File:

• boot/arch/arm32/src/mm.c (modified) (2 diffs)

boot/arch/arm32/src/mm.c

@@ -56 +56 @@
         else
                 return 1;
-#else
+#elif defined MACHINE_beagleboardxm
+        const unsigned long address = section << PTE_SECTION_SHIFT;
+        if (address >= BBXM_RAM_START && address < BBXM_RAM_END)
+                return 1;
+#endif
         return 0;
-#endif
 }
 
@@ -130 +133 @@
                 "mcr p15, 0, r0, c3, c0, 0\n"
                 
-#ifdef PROCESSOR_armv7_a
-                /* Read Auxiliary control register */
-                "mrc p15, 0, r0, c1, c0, 1\n"
-                /* Mask to enable L2 cache */
-                "ldr r1, =0x00000002\n"
-                "orr r0, r0, r1\n"
-                /* Store Auxiliary control register */
-                "mrc p15, 0, r0, c1, c0, 1\n"
-#endif
                 /* Current settings */
                 "mrc p15, 0, r0, c1, c0, 0\n"
                 
-#ifdef PROCESSOR_armv7_a
-                /* Mask to enable paging, caching */
-                "ldr r1, =0x00000005\n"
-#else
-#ifdef MACHINE_gta02
-                /* Mask to enable paging (bit 0),
-                   D-cache (bit 2), I-cache (bit 12) */
-                "ldr r1, =0x00001005\n"
-#else
-                /* Mask to enable paging */
-                "ldr r1, =0x00000001\n"
-#endif
-#endif
+                /* Enable ICache, DCache, BPredictors and MMU,
+                 * we disable caches before jumping to kernel
+                 * so this is safe for all archs.
+                 */
+                "ldr r1, =0x00001805\n"
+                
                 "orr r0, r0, r1\n"