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Changeset 3acd1bb in mainline


Ignore:
Timestamp:
2013-02-17T15:00:03Z (9 years ago)
Author:
Maurizio Lombardi <m.lombardi85@…>
Branches:
lfn, master
Children:
9ad289d
Parents:
124a1ce (diff), 005b765 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

merge mainline changes

Location:
boot/arch/arm32
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • boot/arch/arm32/Makefile.inc

    r124a1ce r3acd1bb  
    5454RD_SRVS_ESSENTIAL += \
    5555        $(USPACE_PATH)/srv/hid/s3c24xx_ts/s3c24xx_ts \
    56         $(USPACE_PATH)/srv/hw/char/s3c24xx_uart/s3c24xx_uart
     56        $(USPACE_PATH)/srv/hw/char/s3c24xx_uart/s3c24ser
    5757endif
    5858
  • boot/arch/arm32/src/asm.S

    r124a1ce r3acd1bb  
    9797        nop
    9898#endif
    99        
    100 #TODO:This should not be necessary
    101 
    102 #if defined(MACHINE_gta02)
    103 
    104 #define CP15_C7_SEG_SHIFT       5
    105 #define CP15_C7_SEG_SIZE        3
    106 #define CP15_C7_IDX_SHIFT       26
    107 
    108         # Now clean D-cache to guarantee coherency between I-cache and D-cache.
    109 
    110         # D-cache clean and invalidate procedure.
    111         # See ARM920T TRM pages 2-17, 4-17.
    112 
    113         # Initialize segment
    114         mov     r4, #0
    115         # Initialize index
    116 1:      mov     r5, #0
    117 2:      orr     r6, r4, r5
    118         # Clean and invalidate a single line
    119         mcr     p15, 0, r6, c7, c10, 2
    120         # Increment index
    121         add     r5, r5, #(1 << CP15_C7_IDX_SHIFT)
    122         cmp     r5, #0
    123         bne     2b
    124         # Increment segment
    125         add     r4, #(1 << CP15_C7_SEG_SHIFT)
    126         tst     r4, #(1 << (CP15_C7_SEG_SHIFT + CP15_C7_SEG_SIZE))
    127         beq     1b
    128 #endif
    129 
    13099        mov pc, r0
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