Changeset dd0c8a0 in mainline for kernel/arch

Timestamp:

2013-09-29T06:56:33Z (12 years ago)

Author:

Beniamino Galvani <b.galvani@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

a9bd960d

Parents:

3deb0155 (diff), 13be2583 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge mainline changes.

Location:

kernel/arch

Files:

• abs32le/Makefile.inc (modified) (1 diff)
• abs32le/include/arch/mm/frame.h (modified) (1 diff)
• abs32le/include/arch/mm/page.h (modified) (1 diff)
• amd64/Makefile.inc (modified) (2 diffs)
• amd64/include/arch/mm/frame.h (modified) (1 diff)
• amd64/include/arch/mm/page.h (modified) (1 diff)
• amd64/include/arch/pm.h (modified) (1 diff)
• amd64/src/ddi/ddi.c (modified) (7 diffs)
• amd64/src/pm.c (modified) (1 diff)
• amd64/src/proc/task.c (modified) (3 diffs)
• arm32/include/arch/asm.h (modified) (3 diffs)
• arm32/include/arch/cp15.h (modified) (5 diffs)
• arm32/include/arch/mm/frame.h (modified) (1 diff)
• arm32/include/arch/mm/page.h (modified) (5 diffs)
• arm32/include/arch/mm/page_armv4.h (modified) (3 diffs)
• arm32/include/arch/mm/page_armv6.h (modified) (7 diffs)
• arm32/src/cpu/cpu.c (modified) (8 diffs)
• arm32/src/mach/beagleboardxm/beagleboardxm.c (modified) (7 diffs)
• arm32/src/mach/beaglebone/beaglebone.c (modified) (7 diffs)
• arm32/src/mm/frame.c (modified) (1 diff)
• arm32/src/mm/page.c (modified) (1 diff)
• arm32/src/mm/tlb.c (modified) (5 diffs)
• arm32/src/ras.c (modified) (1 diff)
• ia32/Makefile.inc (modified) (1 diff)
• ia32/include/arch/cpu.h (modified) (2 diffs)
• ia32/include/arch/cpuid.h (modified) (1 diff)
• ia32/include/arch/mm/frame.h (modified) (1 diff)
• ia32/include/arch/mm/page.h (modified) (1 diff)
• ia32/include/arch/pm.h (modified) (2 diffs)
• ia32/src/boot/vesa_real.inc (modified) (3 diffs)
• ia32/src/cpu/cpu.c (modified) (1 diff)
• ia32/src/ddi/ddi.c (modified) (6 diffs)
• ia32/src/fpu_context.c (modified) (4 diffs)
• ia32/src/pm.c (modified) (1 diff)
• ia32/src/proc/task.c (modified) (1 diff)
• ia64/include/arch/mm/frame.h (modified) (1 diff)
• ia64/src/ddi/ddi.c (modified) (3 diffs)
• ia64/src/mm/vhpt.c (modified) (2 diffs)
• mips32/include/arch/asm.h (modified) (1 diff)
• mips32/include/arch/mm/frame.h (modified) (1 diff)
• mips32/include/arch/mm/page.h (modified) (3 diffs)
• mips32/src/mach/malta/malta.c (modified) (1 diff)
• mips32/src/mm/tlb.c (modified) (3 diffs)
• mips64/include/arch/mm/frame.h (modified) (1 diff)
• ppc32/include/arch/mm/frame.h (modified) (1 diff)
• ppc32/include/arch/mm/page.h (modified) (1 diff)
• sparc64/include/arch/mm/frame.h (modified) (1 diff)
• sparc64/include/arch/mm/sun4u/frame.h (modified) (4 diffs)
• sparc64/include/arch/mm/sun4v/frame.h (modified) (2 diffs)
• sparc64/include/arch/trap/sun4v/mmu.h (modified) (1 diff)
• sparc64/src/mm/sun4u/as.c (modified) (1 diff)
• sparc64/src/mm/sun4v/as.c (modified) (2 diffs)
• sparc64/src/mm/sun4v/frame.c (modified) (1 diff)
• sparc64/src/mm/sun4v/tlb.c (modified) (3 diffs)
• sparc64/src/sun4v/start.S (modified) (1 diff)

kernel/arch/abs32le/Makefile.inc

@@ -39 +39 @@
 endif
 
-ifeq ($(COMPILER),clang)
-        CLANG_ARCH = i386
-endif
-
 BITS = 32
 ENDIANESS = LE

kernel/arch/abs32le/include/arch/mm/frame.h

@@ -39 +39 @@
 #define FRAME_SIZE   (1 << FRAME_WIDTH)
 
+#define FRAME_LOWPRIO  0
+
 #include <typedefs.h>
 

kernel/arch/abs32le/include/arch/mm/page.h

@@ -57 +57 @@
 
 /* Page table sizes for each level. */
-#define PTL0_SIZE_ARCH  ONE_FRAME
-#define PTL1_SIZE_ARCH  0
-#define PTL2_SIZE_ARCH  0
-#define PTL3_SIZE_ARCH  ONE_FRAME
+#define PTL0_FRAMES_ARCH  1
+#define PTL1_FRAMES_ARCH  1
+#define PTL2_FRAMES_ARCH  1
+#define PTL3_FRAMES_ARCH  1
 
 /* Macros calculating indices for each level. */

kernel/arch/amd64/Makefile.inc

@@ -30 +30 @@
 BFD_ARCH = i386:x86-64
 BFD = binary
-CLANG_ARCH = x86_64
 
 FPU_NO_CFLAGS = -mno-sse -mno-sse2
@@ -36 +35 @@
 GCC_CFLAGS += $(CMN1)
 ICC_CFLAGS += $(CMN1)
+CLANG_CFLAGS += $(CMN1)
 
 BITS = 64

kernel/arch/amd64/include/arch/mm/frame.h

@@ -39 +39 @@
 #define FRAME_SIZE   (1 << FRAME_WIDTH)
 
+#define FRAME_LOWPRIO  0x1000
+
 #ifndef __ASM__
 

kernel/arch/amd64/include/arch/mm/page.h

@@ -61 +61 @@
 
 /* Page table sizes for each level. */
-#define PTL0_SIZE_ARCH  ONE_FRAME
-#define PTL1_SIZE_ARCH  ONE_FRAME
-#define PTL2_SIZE_ARCH  ONE_FRAME
-#define PTL3_SIZE_ARCH  ONE_FRAME
+#define PTL0_FRAMES_ARCH  1
+#define PTL1_FRAMES_ARCH  1
+#define PTL2_FRAMES_ARCH  1
+#define PTL3_FRAMES_ARCH  1
 
 /* Macros calculating indices into page tables in each level. */

kernel/arch/amd64/include/arch/pm.h

@@ -57 +57 @@
 #ifdef CONFIG_FB
 
-#define VESA_INIT_DES      8
 #define VESA_INIT_SEGMENT  0x8000
+#define VESA_INIT_CODE_DES      8
+#define VESA_INIT_DATA_DES      9
 
 #undef GDT_ITEMS
-#define GDT_ITEMS  9
+#define GDT_ITEMS  10
 
 #endif /* CONFIG_FB */

kernel/arch/amd64/src/ddi/ddi.c

@@ -42 +42 @@
 #include <errno.h>
 #include <arch/cpu.h>
+#include <cpu.h>
 #include <arch.h>
 #include <align.h>
@@ -58 +59 @@
 int ddi_iospace_enable_arch(task_t *task, uintptr_t ioaddr, size_t size)
 {
-        size_t bits = ioaddr + size;
-        if (bits > IO_PORTS)
+        size_t elements = ioaddr + size;
+        if (elements > IO_PORTS)
                 return ENOENT;
         
-        if (task->arch.iomap.bits < bits) {
+        if (task->arch.iomap.elements < elements) {
                 /*
                  * The I/O permission bitmap is too small and needs to be grown.
                  */
                 
-                uint8_t *newmap = (uint8_t *) malloc(BITS2BYTES(bits), FRAME_ATOMIC);
-                if (!newmap)
+                void *store = malloc(bitmap_size(elements), FRAME_ATOMIC);
+                if (!store)
                         return ENOMEM;
                 
                 bitmap_t oldiomap;
-                bitmap_initialize(&oldiomap, task->arch.iomap.map,
+                bitmap_initialize(&oldiomap, task->arch.iomap.elements,
                     task->arch.iomap.bits);
-                bitmap_initialize(&task->arch.iomap, newmap, bits);
+                
+                bitmap_initialize(&task->arch.iomap, elements, store);
                 
                 /*
                  * Mark the new range inaccessible.
                  */
-                bitmap_set_range(&task->arch.iomap, oldiomap.bits,
-                    bits - oldiomap.bits);
+                bitmap_set_range(&task->arch.iomap, oldiomap.elements,
+                    elements - oldiomap.elements);
                 
                 /*
@@ -88 +90 @@
                 if (oldiomap.bits) {
                         bitmap_copy(&task->arch.iomap, &oldiomap,
-                            oldiomap.bits);
-                        free(oldiomap.map);
+                            oldiomap.elements);
+                        
+                        free(oldiomap.bits);
                 }
         }
@@ -96 +99 @@
          * Enable the range and we are done.
          */
-        bitmap_clear_range(&task->arch.iomap, (size_t) ioaddr, (size_t) size);
+        bitmap_clear_range(&task->arch.iomap, (size_t) ioaddr, size);
         
         /*
@@ -118 +121 @@
         /* First, copy the I/O Permission Bitmap. */
         irq_spinlock_lock(&TASK->lock, false);
+        
         size_t ver = TASK->arch.iomapver;
-        size_t bits = TASK->arch.iomap.bits;
-        if (bits) {
-                ASSERT(TASK->arch.iomap.map);
+        size_t elements = TASK->arch.iomap.elements;
+        
+        if (elements > 0) {
+                ASSERT(TASK->arch.iomap.bits);
                 
                 bitmap_t iomap;
-                bitmap_initialize(&iomap, CPU->arch.tss->iomap,
-                    TSS_IOMAP_SIZE * 8);
-                bitmap_copy(&iomap, &TASK->arch.iomap, bits);
+                bitmap_initialize(&iomap, TSS_IOMAP_SIZE * 8,
+                    CPU->arch.tss->iomap);
+                bitmap_copy(&iomap, &TASK->arch.iomap, elements);
                 
                 /*
@@ -132 +137 @@
                  * I/O access.
                  */
-                bitmap_set_range(&iomap, bits, ALIGN_UP(bits, 8) - bits);
+                bitmap_set_range(&iomap, elements,
+                    ALIGN_UP(elements, 8) - elements);
+                
                 /*
                  * It is safe to set the trailing eight bits because of the
                  * extra convenience byte in TSS_IOMAP_SIZE.
                  */
-                bitmap_set_range(&iomap, ALIGN_UP(bits, 8), 8);
+                bitmap_set_range(&iomap, ALIGN_UP(elements, 8), 8);
         }
+        
         irq_spinlock_unlock(&TASK->lock, false);
         
         /*
          * Second, adjust TSS segment limit.
-         * Take the extra ending byte will all bits set into account. 
+         * Take the extra ending byte with all bits set into account.
          */
         ptr_16_64_t cpugdtr;
@@ -149 +157 @@
         
         descriptor_t *gdt_p = (descriptor_t *) cpugdtr.base;
-        gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE + BITS2BYTES(bits));
+        size_t size = bitmap_size(elements);
+        gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE + size);
         gdtr_load(&cpugdtr);
         

kernel/arch/amd64/src/pm.c

@@ -112 +112 @@
         /* VESA Init descriptor */
 #ifdef CONFIG_FB
-        {
-                0xffff, 0, VESA_INIT_SEGMENT >> 12, AR_PRESENT | AR_CODE | DPL_KERNEL,
-                    0xf, 0, 0, 0, 0, 0
-        }
+        { 0xffff, 0, VESA_INIT_SEGMENT >> 12, AR_PRESENT | AR_CODE | AR_READABLE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 },
+        { 0xffff, 0, VESA_INIT_SEGMENT >> 12, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 }
 #endif
 };

kernel/arch/amd64/src/proc/task.c

@@ -34 +34 @@
 
 #include <proc/task.h>
+#include <typedefs.h>
+#include <adt/bitmap.h>
 #include <mm/slab.h>
-#include <typedefs.h>
 
 /** Perform amd64 specific task initialization.
@@ -45 +46 @@
 {
         task->arch.iomapver = 0;
-        bitmap_initialize(&task->arch.iomap, NULL, 0);
+        bitmap_initialize(&task->arch.iomap, 0, NULL);
 }
 
@@ -55 +56 @@
 void task_destroy_arch(task_t *task)
 {
-        if (task->arch.iomap.map)
-                free(task->arch.iomap.map);
+        if (task->arch.iomap.bits != NULL)
+                free(task->arch.iomap.bits);
 }
 

kernel/arch/arm32/include/arch/asm.h

@@ -38 +38 @@
 
 #include <typedefs.h>
+#include <arch/cp15.h>
 #include <arch/stack.h>
 #include <config.h>
@@ -51 +52 @@
  * chapter 2.3.8 p.2-22 (52 in the PDF)
  *
- * @note Although mcr p15, 0, R0, c7, c0, 4 is defined in ARM Architecture
- * reference manual for armv4/5 CP15 implementation is mandatory only for
- * armv6+.
+ * @note Although CP15WFI (mcr p15, 0, R0, c7, c0, 4) is defined in ARM
+ * Architecture reference manual for armv4/5, CP15 implementation is mandatory
+ * only for armv6+.
  */
 NO_TRACE static inline void cpu_sleep(void)
@@ -60 +61 @@
         asm volatile ( "wfe" );
 #elif defined(PROCESSOR_ARCH_armv6) | defined(PROCESSOR_arm926ej_s) | defined(PROCESSOR_arm920t)
-        asm volatile ( "mcr p15, 0, R0, c7, c0, 4" );
+        WFI_write(0);
 #endif
 }

kernel/arch/arm32/include/arch/cp15.h

@@ -171 +171 @@
         CCSIDR_LINESIZE_MASK = 0x7,
         CCSIDR_LINESIZE_SHIFT = 0,
+#define CCSIDR_SETS(val) \
+        (((val >> CCSIDR_NUMSETS_SHIFT) & CCSIDR_NUMSETS_MASK) + 1)
+#define CCSIDR_WAYS(val) \
+        (((val >> CCSIDR_ASSOC_SHIFT) & CCSIDR_ASSOC_MASK) + 1)
+/* The register value is log(linesize_in_words) - 2 */
+#define CCSIDR_LINESIZE_LOG(val) \
+        (((val >> CCSIDR_LINESIZE_SHIFT) & CCSIDR_LINESIZE_MASK) + 2 + 2)
 };
 CONTROL_REG_GEN_READ(CCSIDR, c0, 1, c0, 0);
@@ -187 +194 @@
         CLIDR_UNI_CACHE = 0x4,
         CLIDR_CACHE_MASK = 0x7,
-#define CLIDR_CACHE(level, val)   ((val >> (level - 1) * 3) & CLIDR_CACHE_MASK)
+/** levels counted from 0 */
+#define CLIDR_CACHE(level, val)   ((val >> (level * 3)) & CLIDR_CACHE_MASK)
 };
 CONTROL_REG_GEN_READ(CLIDR, c0, 1, c0, 1);
@@ -294 +302 @@
 
 /* Memory protection and control registers */
+enum {
+        TTBR_ADDR_MASK = 0xffffff80,
+        TTBR_NOS_FLAG = 1 << 5,
+        TTBR_RGN_MASK = 0x3 << 3,
+        TTBR_RGN_NO_CACHE = 0x0 << 3,
+        TTBR_RGN_WBWA_CACHE = 0x1 << 3,
+        TTBR_RGN_WT_CACHE = 0x2 << 3,
+        TTBR_RGN_WB_CACHE = 0x3 << 3,
+        TTBR_S_FLAG = 1 << 1,
+        TTBR_C_FLAG = 1 << 0,
+};
 CONTROL_REG_GEN_READ(TTBR0, c2, 0, c0, 0);
 CONTROL_REG_GEN_WRITE(TTBR0, c2, 0, c0, 0);
@@ -364 +383 @@
 
 CONTROL_REG_GEN_WRITE(DCIMVAC, c7, 0, c6, 1);
-CONTROL_REG_GEN_WRITE(DCIMSW, c7, 0, c6, 2);
+CONTROL_REG_GEN_WRITE(DCISW, c7, 0, c6, 2);
 
 CONTROL_REG_GEN_WRITE(ATS1CPR, c7, 0, c8, 0);
@@ -370 +389 @@
 CONTROL_REG_GEN_WRITE(ATS1CUR, c7, 0, c8, 2);
 CONTROL_REG_GEN_WRITE(ATS1CUW, c7, 0, c8, 3);
-CONTROL_REG_GEN_WRITE(ATS1NSOPR, c7, 0, c8, 4);
-CONTROL_REG_GEN_WRITE(ATS1NSOPW, c7, 0, c8, 5);
-CONTROL_REG_GEN_WRITE(ATS1NSOUR, c7, 0, c8, 6);
-CONTROL_REG_GEN_WRITE(ATS1NSOUW, c7, 0, c8, 7);
+CONTROL_REG_GEN_WRITE(ATS12NSOPR, c7, 0, c8, 4);
+CONTROL_REG_GEN_WRITE(ATS12NSOPW, c7, 0, c8, 5);
+CONTROL_REG_GEN_WRITE(ATS12NSOUR, c7, 0, c8, 6);
+CONTROL_REG_GEN_WRITE(ATS12NSOUW, c7, 0, c8, 7);
 
 

kernel/arch/arm32/include/arch/mm/frame.h

@@ -39 +39 @@
 #define FRAME_WIDTH  12  /* 4KB frames */
 #define FRAME_SIZE   (1 << FRAME_WIDTH)
+
+#define FRAME_LOWPRIO  0
 
 #ifndef __ASM__

kernel/arch/arm32/include/arch/mm/page.h

@@ -41 +41 @@
 #include <arch/exception.h>
 #include <arch/barrier.h>
+#include <arch/cp15.h>
 #include <trace.h>
 
@@ -72 +73 @@
 
 /* Page table sizes for each level. */
-#define PTL0_SIZE_ARCH          FOUR_FRAMES
-#define PTL1_SIZE_ARCH          0
-#define PTL2_SIZE_ARCH          0
-#define PTL3_SIZE_ARCH          ONE_FRAME
+#define PTL0_FRAMES_ARCH  4
+#define PTL1_FRAMES_ARCH  1
+#define PTL2_FRAMES_ARCH  1
+#define PTL3_FRAMES_ARCH  1
 
 /* Macros calculating indices into page tables for each level. */
@@ -95 +96 @@
 /* Set PTE address accessors for each level. */
 #define SET_PTL0_ADDRESS_ARCH(ptl0) \
-        (set_ptl0_addr((pte_t *) (ptl0)))
+        set_ptl0_addr((pte_t *) (ptl0))
 #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
-        (((pte_t *) (ptl0))[(i)].l0.coarse_table_addr = (a) >> 10)
+        set_ptl1_addr((pte_t*) (ptl0), i, a)
 #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
 #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
 #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
-        (((pte_t *) (ptl3))[(i)].l1.frame_base_addr = (a) >> 12)
+        set_ptl3_addr((pte_t*) (ptl3), i, a)
 
 /* Get PTE flags accessors for each level. */
@@ -129 +130 @@
         set_pt_level1_present((pte_t *) (ptl3), (size_t) (i))
 
+
+#define pt_coherence(page) pt_coherence_m(page, 1)
+
 #if defined(PROCESSOR_ARCH_armv6) | defined(PROCESSOR_ARCH_armv7_a)
 #include "page_armv6.h"
@@ -137 +141 @@
 #endif
 
+/** Sets the address of level 0 page table.
+ *
+ * @param pt Pointer to the page table to set.
+ *
+ * Page tables are always in cacheable memory.
+ * Make sure the memory type is correct, and in sync with:
+ * init_boot_pt (boot/arch/arm32/src/mm.c)
+ * init_ptl0_section (boot/arch/arm32/src/mm.c)
+ * set_pt_level1_flags (kernel/arch/arm32/include/arch/mm/page_armv6.h)
+ */
+NO_TRACE static inline void set_ptl0_addr(pte_t *pt)
+{
+        uint32_t val = (uint32_t)pt & TTBR_ADDR_MASK;
+        val |= TTBR_RGN_WBWA_CACHE | TTBR_C_FLAG;
+        TTBR0_write(val);
+}
+
+NO_TRACE static inline void set_ptl1_addr(pte_t *pt, size_t i, uintptr_t address)
+{
+        pt[i].l0.coarse_table_addr = address >> 10;
+        pt_coherence(&pt[i].l0);
+}
+
+NO_TRACE static inline void set_ptl3_addr(pte_t *pt, size_t i, uintptr_t address)
+{
+        pt[i].l1.frame_base_addr = address >> 12;
+        pt_coherence(&pt[i].l1);
+}
+
 #endif
 

kernel/arch/arm32/include/arch/mm/page_armv4.h

@@ -120 +120 @@
 #define PTE_DESCRIPTOR_SMALL_PAGE       2
 
-
-/** Sets the address of level 0 page table.
- *
- * @param pt Pointer to the page table to set.
- *
- */
-NO_TRACE static inline void set_ptl0_addr(pte_t *pt)
-{
-        asm volatile (
-                "mcr p15, 0, %[pt], c2, c0, 0\n"
-                :: [pt] "r" (pt)
-        );
-}
-
+#define pt_coherence_m(pt, count) \
+do { \
+        for (unsigned i = 0; i < count; ++i) \
+                DCCMVAU_write((uintptr_t)(pt + i)); \
+        read_barrier(); \
+} while (0)
 
 /** Returns level 0 page table entry flags.
@@ -223 +215 @@
         
         /* default access permission */
-        p->access_permission_0 = p->access_permission_1 = 
+        p->access_permission_0 = p->access_permission_1 =
             p->access_permission_2 = p->access_permission_3 =
             PTE_AP_USER_NO_KERNEL_RW;
@@ -229 +221 @@
         if (flags & PAGE_USER)  {
                 if (flags & PAGE_READ) {
-                        p->access_permission_0 = p->access_permission_1 = 
-                            p->access_permission_2 = p->access_permission_3 = 
+                        p->access_permission_0 = p->access_permission_1 =
+                            p->access_permission_2 = p->access_permission_3 =
                             PTE_AP_USER_RO_KERNEL_RW;
                 }
                 if (flags & PAGE_WRITE) {
-                        p->access_permission_0 = p->access_permission_1 = 
-                            p->access_permission_2 = p->access_permission_3 = 
-                            PTE_AP_USER_RW_KERNEL_RW; 
+                        p->access_permission_0 = p->access_permission_1 =
+                            p->access_permission_2 = p->access_permission_3 =
+                            PTE_AP_USER_RW_KERNEL_RW;
                 }
         }

kernel/arch/arm32/include/arch/mm/page_armv6.h

@@ -40 +40 @@
 #error "Do not include arch specific page.h directly use generic page.h instead"
 #endif
+
 
 /* Macros for querying the last-level PTE entries. */
@@ -125 +126 @@
 #define PTE_DESCRIPTOR_SMALL_PAGE_NX    3
 
-/** Sets the address of level 0 page table.
- *
- * @param pt Pointer to the page table to set.
- *
- */
-NO_TRACE static inline void set_ptl0_addr(pte_t *pt)
-{
-        asm volatile (
-                "mcr p15, 0, %[pt], c2, c0, 0\n"
-                :: [pt] "r" (pt)
-        );
-}
+
+/**
+ * For an ARMv7 implementation that does not include the Large Physical Address Extension,
+ * and in implementations of architecture versions before ARMv7, if the translation tables
+ * are held in Write-Back Cacheable memory, the caches must be cleaned to the point of
+ * unification after writing to the translation tables and before the DSB instruction. This
+ * ensures that the updated translation table are visible to a hardware translation table walk.
+ *
+ * Therefore, an example instruction sequence for writing a translation table entry,
+ * covering changes to the instruction
+ * or data mappings in a uniprocessor system is:
+ * STR rx, [Translation table entry]
+ * ; write new entry to the translation table
+ * Clean cache line [Translation table entry] : This operation is not required with the
+ * ; Multiprocessing Extensions.
+ * DSB
+ * ; ensures visibility of the data cleaned from the D Cache
+ * Invalidate TLB entry by MVA (and ASID if non-global) [page address]
+ * Invalidate BTC
+ * DSB
+ * ; ensure completion of the Invalidate TLB operation
+ * ISB
+ * ; ensure table changes visible to instruction fetch
+ *
+ * ARM Architecture reference chp. B3.10.1 p. B3-1375
+ * @note: see TTRB0/1 for pt memory type
+ */
+#define pt_coherence_m(pt, count) \
+do { \
+        for (unsigned i = 0; i < count; ++i) \
+                DCCMVAU_write((uintptr_t)(pt + i)); \
+        read_barrier(); \
+} while (0)
 
 
@@ -206 +228 @@
                 p->ns = 0;
         }
+        pt_coherence(p);
 }
 
@@ -232 +255 @@
                         p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE_NX;
         }
-        
-        /* tex=0 buf=1 and cache=1 => normal memory
-         * tex=0 buf=1 and cache=0 => shareable device mmio
-         */
-        p->cacheable = (flags & PAGE_CACHEABLE);
-        p->bufferable = 1;
-        p->tex = 0;
+
+        if (flags & PAGE_CACHEABLE) {
+                /*
+                 * Write-through, no write-allocate memory, see ch. B3.8.2
+                 * (p. B3-1358) of ARM Architecture reference manual.
+                 * Make sure the memory type is correct, and in sync with:
+                 * init_boot_pt (boot/arch/arm32/src/mm.c)
+                 * init_ptl0_section (boot/arch/arm32/src/mm.c)
+                 * set_ptl0_addr (kernel/arch/arm32/include/arch/mm/page.h)
+                 */
+                p->tex = 5;
+                p->cacheable = 0;
+                p->bufferable = 1;
+        } else {
+                /*
+                 * Shareable device memory, see ch. B3.8.2 (p. B3-1358) of
+                 * ARM Architecture reference manual.
+                 */
+                p->tex = 0;
+                p->cacheable = 0;
+                p->bufferable = 1;
+        }
         
         /* Shareable is ignored for devices (non-cacheable),
-         * turn it on for normal memory. */
-        p->shareable = 1;
+         * turn it off for normal memory. */
+        p->shareable = 0;
         
         p->non_global = !(flags & PAGE_GLOBAL);
@@ -256 +294 @@
                         p->access_permission_1 = PTE_AP1_RO;
         }
+        pt_coherence(p);
 }
 
@@ -264 +303 @@
         p->should_be_zero_0 = 0;
         p->should_be_zero_1 = 0;
-        write_barrier();
         p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
+        pt_coherence(p);
 }
 
@@ -273 +312 @@
 
         p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE;
+        pt_coherence(p);
 }
 

kernel/arch/arm32/src/cpu/cpu.c

@@ -157 +157 @@
 #endif
 #ifdef PROCESSOR_ARCH_armv7_a
-         /* ICache coherency is elaborate on in barrier.h.
+         /* ICache coherency is elaborated on in barrier.h.
           * VIPT and PIPT caches need maintenance only on code modify,
           * so it should be safe for general use.
@@ -166 +166 @@
                 control_reg |=
                     SCTLR_INST_CACHE_EN_FLAG | SCTLR_BRANCH_PREDICT_EN_FLAG;
+        } else {
+                control_reg &=
+                    ~(SCTLR_INST_CACHE_EN_FLAG | SCTLR_BRANCH_PREDICT_EN_FLAG);
         }
 #endif
@@ -204 +207 @@
 #ifdef PROCESSOR_ARCH_armv7_a
         CSSELR_write((level & CCSELR_LEVEL_MASK) << CCSELR_LEVEL_SHIFT);
-        const unsigned ls_log = 2 +
-            ((CCSIDR_read() >> CCSIDR_LINESIZE_SHIFT) & CCSIDR_LINESIZE_MASK);
-        return ls_log + 2; //return log2(bytes)
+        const uint32_t ccsidr = CCSIDR_read();
+        return CCSIDR_LINESIZE_LOG(ccsidr);
 #endif
         return 0;
@@ -217 +219 @@
 #ifdef PROCESSOR_ARCH_armv7_a
         CSSELR_write((level & CCSELR_LEVEL_MASK) << CCSELR_LEVEL_SHIFT);
-        const unsigned ways = 1 +
-            ((CCSIDR_read() >> CCSIDR_ASSOC_SHIFT) & CCSIDR_ASSOC_MASK);
-        return ways;
+        const uint32_t ccsidr = CCSIDR_read();
+        return CCSIDR_WAYS(ccsidr);
 #endif
         return 0;
@@ -229 +230 @@
 #ifdef PROCESSOR_ARCH_armv7_a
         CSSELR_write((level & CCSELR_LEVEL_MASK) << CCSELR_LEVEL_SHIFT);
-        const unsigned sets = 1 +
-            ((CCSIDR_read() >> CCSIDR_NUMSETS_SHIFT) & CCSIDR_NUMSETS_MASK);
-        return sets;
+        const uint32_t ccsidr = CCSIDR_read();
+        return CCSIDR_SETS(ccsidr);
 #endif
         return 0;
@@ -241 +241 @@
 #ifdef PROCESSOR_ARCH_armv7_a
         const uint32_t val = CLIDR_read();
-        for (unsigned i = 1; i <= 7; ++i) {
+        for (unsigned i = 0; i < 8; ++i) {
                 const unsigned ctype = CLIDR_CACHE(i, val);
                 switch (ctype) {
@@ -280 +280 @@
                 const unsigned ways = dcache_ways(i);
                 const unsigned sets = dcache_sets(i);
-                const unsigned way_shift =  31 - log2(ways);
+                const unsigned way_shift = 32 - log2(ways);
                 const unsigned set_shift = dcache_linesize_log(i);
                 dcache_clean_manual(i, false, ways, sets, way_shift, set_shift);
@@ -293 +293 @@
                 const unsigned ways = dcache_ways(i);
                 const unsigned sets = dcache_sets(i);
-                const unsigned way_shift =  31 - log2(ways);
+                const unsigned way_shift = 32 - log2(ways);
                 const unsigned set_shift = dcache_linesize_log(i);
                 dcache_clean_manual(i, true, ways, sets, way_shift, set_shift);

kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c

@@ -60 +60 @@
 
 static struct beagleboard {
-        amdm37x_irc_regs_t *irc_addr;
-        amdm37x_uart_t uart;
+        omap_irc_regs_t *irc_addr;
+        omap_uart_t uart;
         amdm37x_gpt_t timer;
 } beagleboard;
@@ -85 +85 @@
 static void bb_timer_irq_handler(irq_t *irq)
 {
+        amdm37x_gpt_irq_ack(&beagleboard.timer);
+
         /*
          * We are holding a lock which prevents preemption.
          * Release the lock, call clock() and reacquire the lock again.
          */
-        amdm37x_gpt_irq_ack(&beagleboard.timer);
         spinlock_unlock(&irq->lock);
         clock();
@@ -102 +103 @@
             PAGE_NOT_CACHEABLE);
         ASSERT(beagleboard.irc_addr);
-        amdm37x_irc_init(beagleboard.irc_addr);
+        omap_irc_init(beagleboard.irc_addr);
 
         /* Initialize timer. Use timer1, because it is in WKUP power domain
@@ -122 +123 @@
 
         /* Enable timer interrupt */
-        amdm37x_irc_enable(beagleboard.irc_addr, AMDM37x_GPT1_IRQ);
+        omap_irc_enable(beagleboard.irc_addr, AMDM37x_GPT1_IRQ);
 
         /* Start timer here */
@@ -146 +147 @@
 static void bbxm_irq_exception(unsigned int exc_no, istate_t *istate)
 {
-        const unsigned inum = amdm37x_irc_inum_get(beagleboard.irc_addr);
-        amdm37x_irc_irq_ack(beagleboard.irc_addr);
+        const unsigned inum = omap_irc_inum_get(beagleboard.irc_addr);
 
         irq_t *irq = irq_dispatch_and_lock(inum);
@@ -159 +159 @@
                     CPU->id, inum);
         }
+        /** amdm37x manual ch. 12.5.2 (p. 2428) places irc ack at the end
+         * of ISR. DO this to avoid strange behavior. */
+        omap_irc_irq_ack(beagleboard.irc_addr);
 }
 
@@ -167 +170 @@
 static void bbxm_output_init(void)
 {
+#ifdef CONFIG_OMAP_UART
         /* UART3 is wired to external RS232 connector */
-        const bool ok = amdm37x_uart_init(&beagleboard.uart,
+        const bool ok = omap_uart_init(&beagleboard.uart,
             AMDM37x_UART3_IRQ, AMDM37x_UART3_BASE_ADDRESS, AMDM37x_UART3_SIZE);
         if (ok) {
                 stdout_wire(&beagleboard.uart.outdev);
         }
+#endif
 }
 
 static void bbxm_input_init(void)
 {
+#ifdef CONFIG_OMAP_UART
         srln_instance_t *srln_instance = srln_init();
         if (srln_instance) {
                 indev_t *sink = stdin_wire();
                 indev_t *srln = srln_wire(srln_instance, sink);
-                amdm37x_uart_input_wire(&beagleboard.uart, srln);
-                amdm37x_irc_enable(beagleboard.irc_addr, AMDM37x_UART3_IRQ);
+                omap_uart_input_wire(&beagleboard.uart, srln);
+                omap_irc_enable(beagleboard.irc_addr, AMDM37x_UART3_IRQ);
         }
+#endif
 }
 

kernel/arch/arm32/src/mach/beaglebone/beaglebone.c

@@ -63 +63 @@
 
 static struct beaglebone {
-        am335x_irc_regs_t *irc_addr;
+        omap_irc_regs_t *irc_addr;
         am335x_cm_per_regs_t *cm_per_addr;
         am335x_cm_dpll_regs_t *cm_dpll_addr;
         am335x_ctrl_module_t  *ctrl_module;
         am335x_timer_t timer;
-        am335x_uart_t uart;
+        omap_uart_t uart;
 } bbone;
 
@@ -104 +104 @@
 
         /* Initialize the interrupt controller */
-        am335x_irc_init(bbone.irc_addr);
+        omap_irc_init(bbone.irc_addr);
 }
 
@@ -153 +153 @@
         }
         /* Enable the interrupt */
-        am335x_irc_enable(bbone.irc_addr, AM335x_DMTIMER2_IRQ);
+        omap_irc_enable(bbone.irc_addr, AM335x_DMTIMER2_IRQ);
         /* Start the timer */
         am335x_timer_start(&bbone.timer);
@@ -176 +176 @@
 static void bbone_irq_exception(unsigned int exc_no, istate_t *istate)
 {
-        const unsigned inum = am335x_irc_inum_get(bbone.irc_addr);
-        am335x_irc_irq_ack(bbone.irc_addr);
+        const unsigned inum = omap_irc_inum_get(bbone.irc_addr);
 
         irq_t *irq = irq_dispatch_and_lock(inum);
@@ -187 +186 @@
                 printf("Spurious interrupt\n");
         }
+
+        omap_irc_irq_ack(bbone.irc_addr);
 }
 
@@ -195 +196 @@
 static void bbone_output_init(void)
 {
-        const bool ok = am335x_uart_init(&bbone.uart,
+#ifdef CONFIG_OMAP_UART
+        const bool ok = omap_uart_init(&bbone.uart,
             AM335x_UART0_IRQ, AM335x_UART0_BASE_ADDRESS,
             AM335x_UART0_SIZE);
@@ -201 +203 @@
         if (ok)
                 stdout_wire(&bbone.uart.outdev);
+#endif
 }
 
 static void bbone_input_init(void)
 {
+#ifdef CONFIG_OMAP_UART
         srln_instance_t *srln_instance = srln_init();
         if (srln_instance) {
                 indev_t *sink = stdin_wire();
                 indev_t *srln = srln_wire(srln_instance, sink);
-                am335x_uart_input_wire(&bbone.uart, srln);
-                am335x_irc_enable(bbone.irc_addr, AM335x_UART0_IRQ);
+                omap_uart_input_wire(&bbone.uart, srln);
+                omap_irc_enable(bbone.irc_addr, AM335x_UART0_IRQ);
         }
+#endif
 }
 

kernel/arch/arm32/src/mm/frame.c

@@ -88 +88 @@
 void boot_page_table_free(void)
 {
-        unsigned int i;
-        for (i = 0; i < BOOT_PAGE_TABLE_SIZE_IN_FRAMES; i++)
-                frame_free(i * FRAME_SIZE + BOOT_PAGE_TABLE_ADDRESS);
+        frame_free(BOOT_PAGE_TABLE_ADDRESS,
+            BOOT_PAGE_TABLE_SIZE_IN_FRAMES);
 }
 

kernel/arch/arm32/src/mm/page.c

@@ -73 +73 @@
 #ifdef HIGH_EXCEPTION_VECTORS
         /* Create mapping for exception table at high offset */
-        uintptr_t ev_frame = (uintptr_t) frame_alloc(ONE_FRAME, FRAME_NONE);
+        uintptr_t ev_frame = frame_alloc(1, FRAME_NONE, 0);
         page_mapping_insert(AS_KERNEL, EXC_BASE_ADDRESS, ev_frame, flags);
 #else

kernel/arch/arm32/src/mm/tlb.c

@@ -37 +37 @@
 #include <arch/mm/asid.h>
 #include <arch/asm.h>
+#include <arch/cp15.h>
 #include <typedefs.h>
 #include <arch/mm/page.h>
+#include <arch/cache.h>
 
 /** Invalidate all entries in TLB.
@@ -46 +48 @@
 void tlb_invalidate_all(void)
 {
-        asm volatile (
-                "eor r1, r1\n"
-                "mcr p15, 0, r1, c8, c7, 0\n"
-                ::: "r1"
-        );
+        TLBIALL_write(0);
+        /*
+         * "A TLB maintenance operation is only guaranteed to be complete after
+         * the execution of a DSB instruction."
+         * "An ISB instruction, or a return from an exception, causes the
+         * effect of all completed TLB maintenance operations that appear in
+         * program order before the ISB or return from exception to be visible
+         * to all subsequent instructions, including the instruction fetches
+         * for those instructions."
+         * ARM Architecture reference Manual ch. B3.10.1 p. B3-1374 B3-1375
+         */
+        read_barrier();
+        inst_barrier();
 }
 
@@ -60 +70 @@
 {
         tlb_invalidate_all();
+        // TODO: why not TLBIASID_write(asid) ?
 }
 
@@ -65 +76 @@
  *
  * @param page Virtual adress of the page
- */ 
+ */
 static inline void invalidate_page(uintptr_t page)
 {
-        asm volatile (
-                "mcr p15, 0, %[page], c8, c7, 1\n"
-                :: [page] "r" (page)
-        );
+        //TODO: What about TLBIMVAA?
+        TLBIMVA_write(page);
+        /*
+         * "A TLB maintenance operation is only guaranteed to be complete after
+         * the execution of a DSB instruction."
+         * "An ISB instruction, or a return from an exception, causes the
+         * effect of all completed TLB maintenance operations that appear in
+         * program order before the ISB or return from exception to be visible
+         * to all subsequent instructions, including the instruction fetches
+         * for those instructions."
+         * ARM Architecture reference Manual ch. B3.10.1 p. B3-1374 B3-1375
+         */
+        read_barrier();
+        inst_barrier();
 }
 
@@ -83 +104 @@
 void tlb_invalidate_pages(asid_t asid __attribute__((unused)), uintptr_t page, size_t cnt)
 {
-        unsigned int i;
-
-        for (i = 0; i < cnt; i++)
+        for (unsigned i = 0; i < cnt; i++)
                 invalidate_page(page + i * PAGE_SIZE);
 }

kernel/arch/arm32/src/ras.c

@@ -51 +51 @@
 void ras_init(void)
 {
-        uintptr_t frame;
-
-        frame = (uintptr_t) frame_alloc(ONE_FRAME,
-            FRAME_ATOMIC | FRAME_HIGHMEM);
+        uintptr_t frame =
+            frame_alloc(1, FRAME_ATOMIC | FRAME_HIGHMEM, 0);
         if (!frame)
-                frame = (uintptr_t) frame_alloc(ONE_FRAME, FRAME_LOWMEM);
+                frame = frame_alloc(1, FRAME_LOWMEM, 0);
+        
         ras_page = (uintptr_t *) km_map(frame,
             PAGE_SIZE, PAGE_READ | PAGE_WRITE | PAGE_USER | PAGE_CACHEABLE);
-
+        
         memsetb(ras_page, PAGE_SIZE, 0); 
         ras_page[RAS_START] = 0;

kernel/arch/ia32/Makefile.inc

@@ -30 +30 @@
 BFD_ARCH = i386
 BFD = binary
-CLANG_ARCH = i386
 
 BITS = 32

kernel/arch/ia32/include/arch/cpu.h

@@ -41 +41 @@
 #define EFLAGS_RF       (1 << 16)
 
-#define CR4_OSFXSR_MASK (1<<9)
+#define CR4_OSFXSR_MASK      (1 << 9)
+#define CR4_OSXMMEXCPT_MASK  (1 << 10)
 
 /* Support for SYSENTER and SYSEXIT */
@@ -59 +60 @@
         unsigned int model;
         unsigned int stepping;
-        cpuid_feature_info fi;
-
+        cpuid_feature_info_t fi;
+        
         tss_t *tss;
         

kernel/arch/ia32/include/arch/cpuid.h

@@ -50 +50 @@
         uint32_t cpuid_ecx;
         uint32_t cpuid_edx;
-} __attribute__ ((packed)) cpu_info_t;
+} __attribute__((packed)) cpu_info_t;
 
-struct __cpuid_extended_feature_info {
-        unsigned sse3 :  1;
-        unsigned      : 31;
-} __attribute__ ((packed));
+struct cpuid_extended_feature_info {
+        unsigned int sse3 : 1;
+        unsigned int : 31;
+} __attribute__((packed));
 
-typedef union cpuid_extended_feature_info {
-        struct __cpuid_extended_feature_info bits;
+typedef union {
+        struct cpuid_extended_feature_info bits;
         uint32_t word;
-} cpuid_extended_feature_info;
+} cpuid_extended_feature_info_t;
 
-struct __cpuid_feature_info {
-        unsigned      : 11;
-        unsigned sep  :  1;
-        unsigned      : 11;
-        unsigned mmx  :  1;
-        unsigned fxsr :  1;
-        unsigned sse  :  1;
-        unsigned sse2 :  1;
-        unsigned      :  5;
-} __attribute__ ((packed));
+struct cpuid_feature_info {
+        unsigned int : 11;
+        unsigned int sep  : 1;
+        unsigned int : 11;
+        unsigned int mmx  : 1;
+        unsigned int fxsr : 1;
+        unsigned int sse  : 1;
+        unsigned int sse2 : 1;
+        unsigned int : 5;
+} __attribute__((packed));
 
-typedef union cpuid_feature_info {
-        struct __cpuid_feature_info bits;
+typedef union {
+        struct cpuid_feature_info bits;
         uint32_t word;
-} cpuid_feature_info;
-
+} cpuid_feature_info_t;
 
 static inline uint32_t has_cpuid(void)
 {
-        uint32_t val, ret;
+        uint32_t val;
+        uint32_t ret;
         
         asm volatile (

kernel/arch/ia32/include/arch/mm/frame.h

@@ -39 +39 @@
 #define FRAME_SIZE   (1 << FRAME_WIDTH)
 
+#define FRAME_LOWPRIO  0x1000
+
 #ifndef __ASM__
 

kernel/arch/ia32/include/arch/mm/page.h

@@ -66 +66 @@
 
 /* Page table sizes for each level. */
-#define PTL0_SIZE_ARCH  ONE_FRAME
-#define PTL1_SIZE_ARCH  0
-#define PTL2_SIZE_ARCH  0
-#define PTL3_SIZE_ARCH  ONE_FRAME
+#define PTL0_FRAMES_ARCH  1
+#define PTL1_FRAMES_ARCH  1
+#define PTL2_FRAMES_ARCH  1
+#define PTL3_FRAMES_ARCH  1
 
 /* Macros calculating indices for each level. */

kernel/arch/ia32/include/arch/pm.h

@@ -50 +50 @@
 
 #define VESA_INIT_SEGMENT  0x8000
-#define VESA_INIT_DES      7
+#define VESA_INIT_CODE_DES      7
+#define VESA_INIT_DATA_DES      8
 #define KTEXT32_DES        KTEXT_DES
 
 #undef GDT_ITEMS
-#define GDT_ITEMS  8
+#define GDT_ITEMS  9
 
 #endif /* CONFIG_FB */
@@ -67 +68 @@
 #define AR_CODE       (3 << 3)
 #define AR_WRITABLE   (1 << 1)
+#define AR_READABLE   (1 << 1)
 #define AR_INTERRUPT  (0xe)
 #define AR_TRAP       (0xf)

kernel/arch/ia32/src/boot/vesa_real.inc

@@ -31 +31 @@
 vesa_init:
         lidtl vesa_idtr
-        jmp $GDT_SELECTOR(VESA_INIT_DES), $vesa_init_real - vesa_init
+        
+        mov $GDT_SELECTOR(VESA_INIT_DATA_DES), %bx
+        
+        mov %bx, %es
+        mov %bx, %fs
+        mov %bx, %gs
+        mov %bx, %ds
+        mov %bx, %ss
+        
+        jmp $GDT_SELECTOR(VESA_INIT_CODE_DES), $vesa_init_real - vesa_init
 
 vesa_idtr:
@@ -39 +48 @@
 .code16
 vesa_init_real:
-        
         mov %cr0, %eax
         and $~1, %eax
@@ -45 +53 @@
         
         jmp $VESA_INIT_SEGMENT, $vesa_init_real2 - vesa_init
-        
+
 vesa_init_real2:
         mov $VESA_INIT_SEGMENT, %bx

kernel/arch/ia32/src/cpu/cpu.c

@@ -115 +115 @@
                         "mov %[help], %%cr4\n"
                         : [help] "+r" (help)
-                        : [mask] "i" (CR4_OSFXSR_MASK | (1 << 10))
+                        : [mask] "i" (CR4_OSFXSR_MASK | CR4_OSXMMEXCPT_MASK)
                 );
         }
-
+        
 #ifndef PROCESSOR_i486
         if (CPU->arch.fi.bits.sep) {

kernel/arch/ia32/src/ddi/ddi.c

@@ -59 +59 @@
 int ddi_iospace_enable_arch(task_t *task, uintptr_t ioaddr, size_t size)
 {
-        size_t bits = ioaddr + size;
-        if (bits > IO_PORTS)
+        size_t elements = ioaddr + size;
+        if (elements > IO_PORTS)
                 return ENOENT;
         
-        if (task->arch.iomap.bits < bits) {
+        if (task->arch.iomap.elements < elements) {
                 /*
                  * The I/O permission bitmap is too small and needs to be grown.
                  */
                 
-                uint8_t *newmap = (uint8_t *) malloc(BITS2BYTES(bits), FRAME_ATOMIC);
-                if (!newmap)
+                void *store = malloc(bitmap_size(elements), FRAME_ATOMIC);
+                if (!store)
                         return ENOMEM;
                 
                 bitmap_t oldiomap;
-                bitmap_initialize(&oldiomap, task->arch.iomap.map,
+                bitmap_initialize(&oldiomap, task->arch.iomap.elements,
                     task->arch.iomap.bits);
-                bitmap_initialize(&task->arch.iomap, newmap, bits);
+                
+                bitmap_initialize(&task->arch.iomap, elements, store);
                 
                 /*
                  * Mark the new range inaccessible.
                  */
-                bitmap_set_range(&task->arch.iomap, oldiomap.bits,
-                    bits - oldiomap.bits);
+                bitmap_set_range(&task->arch.iomap, oldiomap.elements,
+                    elements - oldiomap.elements);
                 
                 /*
@@ -89 +90 @@
                 if (oldiomap.bits) {
                         bitmap_copy(&task->arch.iomap, &oldiomap,
-                            oldiomap.bits);
-                        free(oldiomap.map);
+                            oldiomap.elements);
+                        
+                        free(oldiomap.bits);
                 }
         }
@@ -97 +99 @@
          * Enable the range and we are done.
          */
-        bitmap_clear_range(&task->arch.iomap, (size_t) ioaddr, (size_t) size);
+        bitmap_clear_range(&task->arch.iomap, (size_t) ioaddr, size);
         
         /*
@@ -119 +121 @@
         /* First, copy the I/O Permission Bitmap. */
         irq_spinlock_lock(&TASK->lock, false);
+        
         size_t ver = TASK->arch.iomapver;
-        size_t bits = TASK->arch.iomap.bits;
-        if (bits) {
-                ASSERT(TASK->arch.iomap.map);
+        size_t elements = TASK->arch.iomap.elements;
+        
+        if (elements > 0) {
+                ASSERT(TASK->arch.iomap.bits);
                 
                 bitmap_t iomap;
-                bitmap_initialize(&iomap, CPU->arch.tss->iomap,
-                    TSS_IOMAP_SIZE * 8);
-                bitmap_copy(&iomap, &TASK->arch.iomap, bits);
+                bitmap_initialize(&iomap, TSS_IOMAP_SIZE * 8,
+                    CPU->arch.tss->iomap);
+                bitmap_copy(&iomap, &TASK->arch.iomap, elements);
                 
                 /*
@@ -133 +137 @@
                  * I/O access.
                  */
-                bitmap_set_range(&iomap, bits, ALIGN_UP(bits, 8) - bits);
+                bitmap_set_range(&iomap, elements,
+                    ALIGN_UP(elements, 8) - elements);
+                
                 /*
                  * It is safe to set the trailing eight bits because of the
                  * extra convenience byte in TSS_IOMAP_SIZE.
                  */
-                bitmap_set_range(&iomap, ALIGN_UP(bits, 8), 8);
+                bitmap_set_range(&iomap, ALIGN_UP(elements, 8), 8);
         }
+        
         irq_spinlock_unlock(&TASK->lock, false);
         
@@ -150 +157 @@
         
         descriptor_t *gdt_p = (descriptor_t *) cpugdtr.base;
-        gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE + BITS2BYTES(bits));
+        size_t size = bitmap_size(elements);
+        gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE + size);
         gdtr_load(&cpugdtr);
         

kernel/arch/ia32/src/fpu_context.c

@@ -27 +27 @@
  */
 
-/** @addtogroup ia32    
+/** @addtogroup ia32
  * @{
  */
@@ -37 +37 @@
 #include <arch.h>
 #include <cpu.h>
-
 
 /** x87 FPU scr values (P3+ MMX2) */
@@ -60 +59 @@
         X87_DENORMAL_EXC_FLAG = (1 << 1),
         X87_INVALID_OP_EXC_FLAG = (1 << 0),
-
+        
         X87_ALL_MASK = X87_PRECISION_MASK | X87_UNDERFLOW_MASK | X87_OVERFLOW_MASK | X87_ZERO_DIV_MASK | X87_DENORMAL_OP_MASK | X87_INVALID_OP_MASK,
 };
 
-
 typedef void (*fpu_context_function)(fpu_context_t *fctx);
 
-static fpu_context_function fpu_save, fpu_restore;
+static fpu_context_function fpu_save;
+static fpu_context_function fpu_restore;
 
 static void fpu_context_f_save(fpu_context_t *fctx)
@@ -104 +103 @@
 void fpu_fxsr(void)
 {
-        fpu_save=fpu_context_fx_save;
-        fpu_restore=fpu_context_fx_restore;
+        fpu_save = fpu_context_fx_save;
+        fpu_restore = fpu_context_fx_restore;
 }
 

kernel/arch/ia32/src/pm.c

@@ -75 +75 @@
         /* VESA Init descriptor */
 #ifdef CONFIG_FB
-        { 0xffff, 0, VESA_INIT_SEGMENT >> 12, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 }
+        { 0xffff, 0, VESA_INIT_SEGMENT >> 12, AR_PRESENT | AR_CODE | AR_READABLE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 },
+        { 0xffff, 0, VESA_INIT_SEGMENT >> 12, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 }
 #endif
 };

kernel/arch/ia32/src/proc/task.c

@@ -40 +40 @@
 /** Perform ia32 specific task initialization.
  *
- * @param t Task to be initialized.
+ * @param task Task to be initialized.
+ *
  */
-void task_create_arch(task_t *t)
+void task_create_arch(task_t *task)
 {
-        t->arch.iomapver = 0;
-        bitmap_initialize(&t->arch.iomap, NULL, 0);
+        task->arch.iomapver = 0;
+        bitmap_initialize(&task->arch.iomap, 0, NULL);
 }
 
 /** Perform ia32 specific task destruction.
  *
- * @param t Task to be initialized.
+ * @param task Task to be initialized.
+ *
  */
-void task_destroy_arch(task_t *t)
+void task_destroy_arch(task_t *task)
 {
-        if (t->arch.iomap.map)
-                free(t->arch.iomap.map);
+        if (task->arch.iomap.bits != NULL)
+                free(task->arch.iomap.bits);
 }
 

kernel/arch/ia64/include/arch/mm/frame.h

@@ -39 +39 @@
 #define FRAME_SIZE   (1 << FRAME_WIDTH)
 
+#define FRAME_LOWPRIO  0
+
 #ifndef __ASM__
 

kernel/arch/ia64/src/ddi/ddi.c

@@ -1 +1 @@
 /*
  * Copyright (c) 2006 Jakub Jermar
- * Copyright (c) 2008 Jakub vana
+ * Copyright (c) 2008 Jakub Vana
  * All rights reserved.
  *
@@ -56 +56 @@
 {
         if (!task->arch.iomap) {
-                uint8_t *map;
-
                 task->arch.iomap = malloc(sizeof(bitmap_t), 0);
-                map = malloc(BITS2BYTES(IO_MEMMAP_PAGES), 0);
-                if(!map)
+                if (task->arch.iomap == NULL)
                         return ENOMEM;
-                bitmap_initialize(task->arch.iomap, map, IO_MEMMAP_PAGES);
+                
+                void *store = malloc(bitmap_size(IO_MEMMAP_PAGES), 0);
+                if (store == NULL)
+                        return ENOMEM;
+                
+                bitmap_initialize(task->arch.iomap, IO_MEMMAP_PAGES, store);
                 bitmap_clear_range(task->arch.iomap, 0, IO_MEMMAP_PAGES);
         }
@@ -69 +71 @@
         size = ALIGN_UP(size + ioaddr - 4 * iopage, PORTS_PER_PAGE);
         bitmap_set_range(task->arch.iomap, iopage, size / 4);
-
+        
         return 0;
 }

kernel/arch/ia64/src/mm/vhpt.c

@@ -42 +42 @@
 uintptr_t vhpt_set_up(void)
 {
-        vhpt_base = frame_alloc(VHPT_WIDTH - FRAME_WIDTH,
-            FRAME_KA | FRAME_ATOMIC);
-        if (!vhpt_base)
+        uintptr_t vhpt_frame =
+            frame_alloc(SIZE2FRAMES(VHPT_SIZE), FRAME_ATOMIC, 0);
+        if (!vhpt_frame)
                 panic("Kernel configured with VHPT but no memory for table.");
+        
+        vhpt_base = (vhpt_entry_t *) PA2KA(vhpt_frame);
         vhpt_invalidate_all();
         return (uintptr_t) vhpt_base;
@@ -82 +84 @@
 void vhpt_invalidate_all()
 {
-        memsetb(vhpt_base, 1 << VHPT_WIDTH, 0);
+        memsetb(vhpt_base, VHPT_SIZE, 0);
 }
 

kernel/arch/mips32/include/arch/asm.h

@@ -42 +42 @@
 NO_TRACE static inline void cpu_sleep(void)
 {
-        /*
-         * Unfortunatelly most of the simulators do not support
-         *
-         * asm volatile (
-         *     "wait"
-         * );
-         *
-         */
+        asm volatile ("wait");
 }
 

kernel/arch/mips32/include/arch/mm/frame.h

@@ -39 +39 @@
 #define FRAME_SIZE   (1 << FRAME_WIDTH)
 
+#define FRAME_LOWPRIO  0
+
 #ifndef __ASM__
 

kernel/arch/mips32/include/arch/mm/page.h

@@ -27 +27 @@
  */
 
-/** @addtogroup mips32mm        
+/** @addtogroup mips32mm
  * @{
  */
@@ -70 +70 @@
  * - PTL3 has 4096 entries (12 bits)
  */
- 
+
 /* Macros describing number of entries in each level. */
-#define PTL0_ENTRIES_ARCH       64
-#define PTL1_ENTRIES_ARCH       0
-#define PTL2_ENTRIES_ARCH       0
-#define PTL3_ENTRIES_ARCH       4096
+#define PTL0_ENTRIES_ARCH  64
+#define PTL1_ENTRIES_ARCH  0
+#define PTL2_ENTRIES_ARCH  0
+#define PTL3_ENTRIES_ARCH  4096
 
 /* Macros describing size of page tables in each level. */
-#define PTL0_SIZE_ARCH          ONE_FRAME
-#define PTL1_SIZE_ARCH          0
-#define PTL2_SIZE_ARCH          0
-#define PTL3_SIZE_ARCH          ONE_FRAME
+#define PTL0_FRAMES_ARCH  1
+#define PTL1_FRAMES_ARCH  1
+#define PTL2_FRAMES_ARCH  1
+#define PTL3_FRAMES_ARCH  1
 
 /* Macros calculating entry indices for each level. */
-#define PTL0_INDEX_ARCH(vaddr)  ((vaddr) >> 26) 
-#define PTL1_INDEX_ARCH(vaddr)  0
-#define PTL2_INDEX_ARCH(vaddr)  0
-#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 14) & 0xfff)
+#define PTL0_INDEX_ARCH(vaddr)  ((vaddr) >> 26)
+#define PTL1_INDEX_ARCH(vaddr)  0
+#define PTL2_INDEX_ARCH(vaddr)  0
+#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 14) & 0xfff)
 
 /* Set accessor for PTL0 address. */
 #define SET_PTL0_ADDRESS_ARCH(ptl0)
 
-/* Get PTE address accessors for each level. */ 
+/* Get PTE address accessors for each level. */
 #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
         (((pte_t *) (ptl0))[(i)].pfn << 12)
@@ -196 +196 @@
         p->p = 1;
 }
-        
 
 extern void page_arch_init(void);

kernel/arch/mips32/src/mach/malta/malta.c

@@ -103 +103 @@
 void malta_input_init(void)
 {
+        (void) stdin_wire();
 }
 

kernel/arch/mips32/src/mm/tlb.c

@@ -48 +48 @@
 #include <symtab.h>
 
-#define PFN_SHIFT       12
-#define VPN_SHIFT       12
-#define ADDR2VPN(a)     ((a) >> VPN_SHIFT)
-#define ADDR2VPN2(a)    (ADDR2VPN((a)) >> 1)
-#define VPN2ADDR(vpn)   ((vpn) << VPN_SHIFT)
-#define VPN22ADDR(vpn2) (VPN2ADDR(vpn2) << 1)
-#define PFN2ADDR(pfn)   ((pfn) << PFN_SHIFT)
-
-#define BANK_SELECT_BIT(a)      (((a) >> PAGE_WIDTH) & 1) 
-        
+#define PFN_SHIFT  12
+#define VPN_SHIFT  12
+
+#define ADDR2HI_VPN(a)   ((a) >> VPN_SHIFT)
+#define ADDR2HI_VPN2(a)  (ADDR2HI_VPN((a)) >> 1)
+
+#define HI_VPN2ADDR(vpn)    ((vpn) << VPN_SHIFT)
+#define HI_VPN22ADDR(vpn2)  (HI_VPN2ADDR(vpn2) << 1)
+
+#define LO_PFN2ADDR(pfn)  ((pfn) << PFN_SHIFT)
+
+#define BANK_SELECT_BIT(a)  (((a) >> PAGE_WIDTH) & 1)
 
 /** Initialize TLB.
@@ -266 +268 @@
 {
         hi->value = 0;
-        hi->vpn2 = ADDR2VPN2(ALIGN_DOWN(addr, PAGE_SIZE));
+        hi->vpn2 = ADDR2HI_VPN2(ALIGN_DOWN(addr, PAGE_SIZE));
         hi->asid = asid;
 }
@@ -295 +297 @@
                 
                 printf("%-4u %-6u %0#10x %-#6x  %1u%1u%1u%1u  %0#10x\n",
-                    i, hi.asid, VPN22ADDR(hi.vpn2), mask.mask,
-                    lo0.g, lo0.v, lo0.d, lo0.c, PFN2ADDR(lo0.pfn));
+                    i, hi.asid, HI_VPN22ADDR(hi.vpn2), mask.mask,
+                    lo0.g, lo0.v, lo0.d, lo0.c, LO_PFN2ADDR(lo0.pfn));
                 printf("                               %1u%1u%1u%1u  %0#10x\n",
-                    lo1.g, lo1.v, lo1.d, lo1.c, PFN2ADDR(lo1.pfn));
+                    lo1.g, lo1.v, lo1.d, lo1.c, LO_PFN2ADDR(lo1.pfn));
         }
         

kernel/arch/mips64/include/arch/mm/frame.h

@@ -39 +39 @@
 #define FRAME_SIZE   (1 << FRAME_WIDTH)
 
+#define FRAME_LOWPRIO  0
+
 #ifndef __ASM__
 

kernel/arch/ppc32/include/arch/mm/frame.h

@@ -39 +39 @@
 #define FRAME_SIZE   (1 << FRAME_WIDTH)
 
+#define FRAME_LOWPRIO  0
+
 #ifndef __ASM__
 

kernel/arch/ppc32/include/arch/mm/page.h

@@ -70 +70 @@
 
 /* Page table sizes for each level. */
-#define PTL0_SIZE_ARCH  ONE_FRAME
-#define PTL1_SIZE_ARCH  0
-#define PTL2_SIZE_ARCH  0
-#define PTL3_SIZE_ARCH  ONE_FRAME
+#define PTL0_FRAMES_ARCH  1
+#define PTL1_FRAMES_ARCH  1
+#define PTL2_FRAMES_ARCH  1
+#define PTL3_FRAMES_ARCH  1
 
 /* Macros calculating indices into page tables on each level. */

kernel/arch/sparc64/include/arch/mm/frame.h

@@ -46 +46 @@
 #endif
 
+#ifndef __ASM__
+
+#include <typedefs.h>
+
+extern uintptr_t end_of_identity;
+
+extern void frame_low_arch_init(void);
+extern void frame_high_arch_init(void);
+#define physmem_print()
+
+#endif
+
 #endif
 

kernel/arch/sparc64/include/arch/mm/sun4u/frame.h

@@ -27 +27 @@
  */
 
-/** @addtogroup sparc64mm       
+/** @addtogroup sparc64mm
  * @{
  */
@@ -41 +41 @@
  * Therefore, the kernel uses 8K only internally on the TLB and TSB levels.
  */
-#define MMU_FRAME_WIDTH         13      /* 8K */
-#define MMU_FRAME_SIZE          (1 << MMU_FRAME_WIDTH)
+#define MMU_FRAME_WIDTH  13  /* 8K */
+#define MMU_FRAME_SIZE   (1 << MMU_FRAME_WIDTH)
 
 /*
@@ -49 +49 @@
  * each 16K page with a pair of adjacent 8K pages.
  */
-#define FRAME_WIDTH             14      /* 16K */
-#define FRAME_SIZE              (1 << FRAME_WIDTH)
+#define FRAME_WIDTH  14  /* 16K */
+#define FRAME_SIZE   (1 << FRAME_WIDTH)
+
+#define FRAME_LOWPRIO  0
 
 #ifndef __ASM__
@@ -72 +74 @@
 typedef union frame_address frame_address_t;
 
-extern uintptr_t end_of_identity;
-
-extern void frame_low_arch_init(void);
-extern void frame_high_arch_init(void);
-#define physmem_print()
-
 #endif
 

kernel/arch/sparc64/include/arch/mm/sun4v/frame.h

@@ -27 +27 @@
  */
 
-/** @addtogroup sparc64mm       
+/** @addtogroup sparc64mm
  * @{
  */
@@ -36 +36 @@
 #define KERN_sparc64_sun4v_FRAME_H_
 
-#define MMU_FRAME_WIDTH         13      /* 8K */
-#define MMU_FRAME_SIZE          (1 << MMU_FRAME_WIDTH)
+#define MMU_FRAME_WIDTH  13  /* 8K */
+#define MMU_FRAME_SIZE   (1 << MMU_FRAME_WIDTH)
 
-#define FRAME_WIDTH             13
-#define FRAME_SIZE              (1 << FRAME_WIDTH)
+#define FRAME_WIDTH  13
+#define FRAME_SIZE   (1 << FRAME_WIDTH)
 
-#ifndef __ASM__
-
-#include <typedefs.h>
-
-extern void frame_low_arch_init(void);
-extern void frame_high_arch_init(void);
-#define physmem_print()
-
-#endif
+#define FRAME_LOWPRIO  0
 
 #endif

kernel/arch/sparc64/include/arch/trap/sun4v/mmu.h

@@ -102 +102 @@
         nop
 
+        /* exclude pages beyond the end of memory from the identity mapping */
+        sethi %hi(end_of_identity), %g4
+        ldx [%g4 + %lo(end_of_identity)], %g4
+        cmp %g1, %g4
+        bgeu %xcc, 0f
+        nop
+
         /*
          * Installing the identity does not fit into 32 instructions, call

kernel/arch/sparc64/src/mm/sun4u/as.c

@@ -63 +63 @@
 {
 #ifdef CONFIG_TSB
-        /*
-         * The order must be calculated with respect to the emulated
-         * 16K page size.
-         *
-         */
-        uint8_t order = fnzb32(((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
-            sizeof(tsb_entry_t)) >> FRAME_WIDTH);
-        
-        uintptr_t tsb = (uintptr_t) frame_alloc(order, flags | FRAME_KA);
-        
-        if (!tsb)
+        uintptr_t tsb_phys =
+            frame_alloc(SIZE2FRAMES((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
+            sizeof(tsb_entry_t)), flags, 0);
+        if (!tsb_phys)
                 return -1;
         
-        as->arch.itsb = (tsb_entry_t *) tsb;
-        as->arch.dtsb = (tsb_entry_t *) (tsb + ITSB_ENTRY_COUNT *
+        tsb_entry_t *tsb = (tsb_entry_t *) PA2KA(tsb_phys);
+        
+        as->arch.itsb = tsb;
+        as->arch.dtsb = tsb + ITSB_ENTRY_COUNT;
+        
+        memsetb(as->arch.itsb, (ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
+            sizeof(tsb_entry_t), 0);
+#endif
+        
+        return 0;
+}
+
+int as_destructor_arch(as_t *as)
+{
+#ifdef CONFIG_TSB
+        size_t frames = SIZE2FRAMES((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
             sizeof(tsb_entry_t));
-        
-        memsetb(as->arch.itsb,
-            (ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * sizeof(tsb_entry_t), 0);
-#endif
-        
-        return 0;
-}
-
-int as_destructor_arch(as_t *as)
-{
-#ifdef CONFIG_TSB
-        /*
-         * The count must be calculated with respect to the emualted 16K page
-         * size.
-         */
-        size_t cnt = ((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
-            sizeof(tsb_entry_t)) >> FRAME_WIDTH;
-        frame_free(KA2PA((uintptr_t) as->arch.itsb));
-        
-        return cnt;
+        frame_free(KA2PA((uintptr_t) as->arch.itsb), frames);
+        
+        return frames;
 #else
         return 0;

kernel/arch/sparc64/src/mm/sun4v/as.c

@@ -66 +66 @@
 {
 #ifdef CONFIG_TSB
-        uint8_t order = fnzb32(
-                (TSB_ENTRY_COUNT * sizeof(tsb_entry_t)) >> FRAME_WIDTH);
-        
-        uintptr_t tsb = (uintptr_t) frame_alloc(order, flags);
-        
+        uintptr_t tsb =
+            frame_alloc(SIZE2FRAMES(TSB_ENTRY_COUNT * sizeof(tsb_entry_t)),
+            flags, 0);
         if (!tsb)
                 return -1;
@@ -92 +90 @@
 {
 #ifdef CONFIG_TSB
-        size_t cnt = (TSB_ENTRY_COUNT * sizeof(tsb_entry_t)) >> FRAME_WIDTH;
-        frame_free((uintptr_t) as->arch.tsb_description.tsb_base);
+        size_t frames = SIZE2FRAMES(TSB_ENTRY_COUNT * sizeof(tsb_entry_t));
+        frame_free(as->arch.tsb_description.tsb_base, frames);
         
-        return cnt;
+        return frames;
 #else
         return 0;

kernel/arch/sparc64/src/mm/sun4v/frame.c

@@ -101 +101 @@
          */
         frame_mark_unavailable(ADDR2PFN(KA2PA(PFN2ADDR(0))), 1);
+
+        /* PA2KA will work only on low-memory. */
+        end_of_identity = PA2KA(config.physmem_end - FRAME_SIZE) + PAGE_SIZE;
 }
 

kernel/arch/sparc64/src/mm/sun4v/tlb.c

@@ -251 +251 @@
         uintptr_t va = DMISS_ADDRESS(page_and_ctx);
         uint16_t ctx = DMISS_CONTEXT(page_and_ctx);
+        as_t *as = AS;
 
         if (ctx == ASID_KERNEL) {
@@ -256 +257 @@
                         /* NULL access in kernel */
                         panic("NULL pointer dereference.");
+                } else if (va >= end_of_identity) {
+                        /* Kernel non-identity */
+                        as = AS_KERNEL;
+                } else {
+                        panic("Unexpected kernel page fault.");
                 }
-                panic("Unexpected kernel page fault.");
-        }
-
-        t = page_mapping_find(AS, va, true);
+        }
+
+        t = page_mapping_find(as, va, true);
         if (t) {
                 /*
@@ -295 +300 @@
         uintptr_t va = DMISS_ADDRESS(page_and_ctx);
         uint16_t ctx = DMISS_CONTEXT(page_and_ctx);
-
-        t = page_mapping_find(AS, va, true);
+        as_t *as = AS;
+
+        if (ctx == ASID_KERNEL)
+                as = AS_KERNEL;
+
+        t = page_mapping_find(as, va, true);
         if (t && PTE_WRITABLE(t)) {
                 /*

kernel/arch/sparc64/src/sun4v/start.S

@@ -345 +345 @@
         .quad 0
 
+/*
+ * This variable is used by the fast_data_access_MMU_miss trap handler.
+ * In runtime, it is modified to contain the address of the end of physical
+ * memory.
+ */
+.global end_of_identity
+end_of_identity:
+        .quad -1
+
 .global kernel_8k_tlb_data_template
 kernel_8k_tlb_data_template: