Changeset bad1f53 in mainline for kernel/arch/arm32/include/cp15.h
- Timestamp:
- 2013-01-19T16:35:17Z (13 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 827aae5
- Parents:
- 5fcd537
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/arm32/include/cp15.h
r5fcd537 rbad1f53 104 104 CONTROL_REG_GEN_READ(ID_ISAR5, c0, 0, c2, 5); 105 105 106 enum { 107 CCSIDR_WT_FLAG = 1 << 31, 108 CCSIDR_WB_FLAG = 1 << 30, 109 CCSIDR_RA_FLAG = 1 << 29, 110 CCSIDR_WA_FLAG = 1 << 28, 111 CCSIDR_NUMSETS_MASK = 0x7fff, 112 CCSIDR_NUMSETS_SHIFT = 13, 113 CCSIDR_ASSOC_MASK = 0x3ff, 114 CCSIDR_ASSOC_SHIFT = 3, 115 CCSIDR_LINESIZE_MASK = 0x7, 116 CCSIDR_LINESIZE_SHIFT = 0, 117 }; 106 118 CONTROL_REG_GEN_READ(CCSIDR, c0, 1, c0, 0); 119 120 enum { 121 CLIDR_LOUU_MASK = 0x7, 122 CLIDR_LOUU_SHIFT = 27, 123 CLIDR_LOC_MASK = 0x7, 124 CLIDR_LOC_SHIFT = 24, 125 CLIDR_LOUIS_MASK = 0x7, 126 CLIDR_LOUIS_SHIFT = 21, 127 CLIDR_NOCACHE = 0x0, 128 CLIDR_ICACHE_ONLY = 0x1, 129 CLIDR_DCACHE_ONLY = 0x2, 130 CLIDR_SEP_CACHE = 0x3, 131 CLIDR_UNI_CACHE = 0x4, 132 CLIDR_CACHE_MASK = 0x7, 133 #define CLIDR_CACHE(level, val) ((val >> (level - 1) * 3) & CLIDR_CACHE_MASK) 134 }; 107 135 CONTROL_REG_GEN_READ(CLIDR, c0, 1, c0, 1); 108 136 CONTROL_REG_GEN_READ(AIDR, c0, 1, c0, 7); /* Implementation defined or MIDR */ 109 137 138 enum { 139 CCSELR_LEVEL_MASK = 0x7, 140 CCSELR_LEVEL_SHIFT = 1, 141 CCSELR_INSTRUCTION_FLAG = 1 << 0, 142 }; 110 143 CONTROL_REG_GEN_READ(CSSELR, c0, 2, c0, 0); 111 144 CONTROL_REG_GEN_WRITE(CSSELR, c0, 2, c0, 0);
Note:
See TracChangeset
for help on using the changeset viewer.