Changeset bad1f53 in mainline for kernel/arch/arm32/include/cp15.h

Timestamp:

2013-01-19T16:35:17Z (13 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

827aae5

Parents:

5fcd537

Message:

arm32: Detect caches on armv7

File:

• kernel/arch/arm32/include/cp15.h (modified) (1 diff)

kernel/arch/arm32/include/cp15.h

@@ -104 +104 @@
 CONTROL_REG_GEN_READ(ID_ISAR5, c0, 0, c2, 5);
 
+enum {
+        CCSIDR_WT_FLAG = 1 << 31,
+        CCSIDR_WB_FLAG = 1 << 30,
+        CCSIDR_RA_FLAG = 1 << 29,
+        CCSIDR_WA_FLAG = 1 << 28,
+        CCSIDR_NUMSETS_MASK = 0x7fff,
+        CCSIDR_NUMSETS_SHIFT = 13,
+        CCSIDR_ASSOC_MASK = 0x3ff,
+        CCSIDR_ASSOC_SHIFT = 3,
+        CCSIDR_LINESIZE_MASK = 0x7,
+        CCSIDR_LINESIZE_SHIFT = 0,
+};
 CONTROL_REG_GEN_READ(CCSIDR, c0, 1, c0, 0);
+
+enum {
+        CLIDR_LOUU_MASK = 0x7,
+        CLIDR_LOUU_SHIFT = 27,
+        CLIDR_LOC_MASK = 0x7,
+        CLIDR_LOC_SHIFT = 24,
+        CLIDR_LOUIS_MASK = 0x7,
+        CLIDR_LOUIS_SHIFT = 21,
+        CLIDR_NOCACHE = 0x0,
+        CLIDR_ICACHE_ONLY = 0x1,
+        CLIDR_DCACHE_ONLY = 0x2,
+        CLIDR_SEP_CACHE = 0x3,
+        CLIDR_UNI_CACHE = 0x4,
+        CLIDR_CACHE_MASK = 0x7,
+#define CLIDR_CACHE(level, val)   ((val >> (level - 1) * 3) & CLIDR_CACHE_MASK)
+};
 CONTROL_REG_GEN_READ(CLIDR, c0, 1, c0, 1);
 CONTROL_REG_GEN_READ(AIDR, c0, 1, c0, 7); /* Implementation defined or MIDR */
 
+enum {
+        CCSELR_LEVEL_MASK = 0x7,
+        CCSELR_LEVEL_SHIFT = 1,
+        CCSELR_INSTRUCTION_FLAG = 1 << 0,
+};
 CONTROL_REG_GEN_READ(CSSELR, c0, 2, c0, 0);
 CONTROL_REG_GEN_WRITE(CSSELR, c0, 2, c0, 0);