Changeset b183ce0a in mainline for kernel

Timestamp:

2013-03-24T15:34:29Z (13 years ago)

Author:

Vojtech Horky <vojtechhorky@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

8a26f82

Parents:

b92a0ee (diff), 119b46e (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge mainline changes

Location:

kernel

Files:

• arch/mips32/Makefile.inc (modified) (3 diffs)
• arch/mips32/_link.ld.in (modified) (1 diff)
• arch/mips32/include/arch/arch.h (modified) (2 diffs)
• arch/mips32/include/arch/cp0.h (modified) (1 diff)
• arch/mips32/include/arch/mach/malta/malta.h (added)
• arch/mips32/include/arch/mach/msim/msim.h (added)
• arch/mips32/include/arch/machine_func.h (added)
• arch/mips32/include/arch/mm/tlb.h (modified) (2 diffs)
• arch/mips32/src/exception.c (modified) (1 diff)
• arch/mips32/src/interrupt.c (modified) (5 diffs)
• arch/mips32/src/mach/malta/malta.c (added)
• arch/mips32/src/mach/msim/msim.c (added)
• arch/mips32/src/machine_func.c (added)
• arch/mips32/src/mips32.c (modified) (5 diffs)
• arch/mips32/src/mm/frame.c (modified) (4 diffs)
• arch/mips32/src/mm/tlb.c (modified) (19 diffs)
• arch/mips64/src/mips64.c (modified) (3 diffs)
• arch/mips64/src/mm/frame.c (modified) (1 diff)
• generic/include/mm/tlb.h (modified) (1 diff)

kernel/arch/mips32/Makefile.inc

@@ -29 +29 @@
 BFD_ARCH = mips
 BFD = binary
-GCC_CFLAGS += -msoft-float -mno-abicalls -G 0 -fno-zero-initialized-in-bss -mips3 -mabi=32
+GCC_CFLAGS += -msoft-float -mno-abicalls -G 0 -fno-zero-initialized-in-bss -mabi=32
 
 BITS = 32
@@ -36 +36 @@
 #
 
-ifeq ($(MACHINE),lgxemul)
-        BFD_NAME = elf32-tradlittlemips
-        ENDIANESS = LE
-endif
-ifeq ($(MACHINE),bgxemul)
-        BFD_NAME = elf32-tradbigmips
-        ENDIANESS = BE
-        GCC_CFLAGS += -D__BE__
-endif
 ifeq ($(MACHINE),msim)
         BFD_NAME = elf32-tradlittlemips
         ENDIANESS = LE
+        GCC_CFLAGS += -march=r4000
+endif
+ifeq ($(MACHINE),bmalta)
+        BFD_NAME = elf32-tradbigmips
+        ENDIANESS = BE
+        GCC_CFLAGS += -D__BE__ -march=4kc
+endif
+ifeq ($(MACHINE),lmalta)
+        BFD_NAME = elf32-tradlittlemips
+        ENDIANESS = LE
+        GCC_CFLAGS += -march=4kc
 endif
 
@@ -69 +71 @@
         arch/$(KARCH)/src/fpu_context.c \
         arch/$(KARCH)/src/ddi/ddi.c \
-        arch/$(KARCH)/src/smp/dorder.c \
-        arch/$(KARCH)/src/smp/smp.c
+        arch/$(KARCH)/src/smp/smp.c \
+        arch/$(KARCH)/src/machine_func.c
+
+ifeq ($(MACHINE),msim)
+        ARCH_SOURCES += \
+                arch/$(KARCH)/src/smp/dorder.c
+endif
+
+ifeq ($(MACHINE),$(filter lmalta bmalta,$(MACHINE)))
+        ARCH_SOURCES += arch/$(KARCH)/src/mach/malta/malta.c
+endif
+ifeq ($(MACHINE),msim)
+        ARCH_SOURCES += arch/$(KARCH)/src/mach/msim/msim.c
+endif
+

kernel/arch/mips32/_link.ld.in

@@ -10 +10 @@
 #define mips mips
 
+#if defined(MACHINE_msim)
 #define KERNEL_LOAD_ADDRESS 0x80100000
+#endif
+
+#if defined(MACHINE_lmalta) || defined(MACHINE_bmalta)
+#define KERNEL_LOAD_ADDRESS 0x80200000
+#endif
 
 OUTPUT_ARCH(mips)

kernel/arch/mips32/include/arch/arch.h

@@ -44 +44 @@
 extern size_t cpu_count;
 
+#if defined(MACHINE_lmalta) || defined(MACHINE_bmalta)
+extern size_t sdram_size;
+#endif
+
 typedef struct {
         void *addr;
@@ -51 +55 @@
 
 typedef struct {
+#if defined(MACHINE_lmalta) || defined(MACHINE_bmalta)
+        uint32_t sdram_size;
+#endif
         uint32_t cpumap;
         size_t cnt;

kernel/arch/mips32/include/arch/cp0.h

@@ -45 +45 @@
 #define cp0_status_im_shift  8
 #define cp0_status_im_mask   0xff00
+
+#define cp0_cause_ip_shift  8
+#define cp0_cause_ip_mask   0xff00
 
 #define cp0_cause_excno(cause)   ((cause >> 2) & 0x1f)

kernel/arch/mips32/include/arch/mm/tlb.h

@@ -41 +41 @@
 #include <trace.h>
 
+#if defined(PROCESSOR_R4000)
 #define TLB_ENTRY_COUNT  48
+#define TLB_INDEX_BITS   6
+#elif defined(PROCESSOR_4Kc)
+#define TLB_ENTRY_COUNT  16
+#define TLB_INDEX_BITS   4
+#else
+#error Please define TLB_ENTRY_COUNT for the target processor.
+#endif
 
-#define TLB_WIRED               1
-#define TLB_KSTACK_WIRED_INDEX  0
+#define TLB_WIRED               0 
 
 #define TLB_PAGE_MASK_4K    (0x000 << 13)
@@ -112 +119 @@
 #ifdef __BE__
                 unsigned p : 1;
-                unsigned : 25;
-                unsigned index : 6;
+                unsigned : 32 - TLB_INDEX_BITS - 1;
+                unsigned index : TLB_INDEX_BITS;
 #else
-                unsigned index : 6;
-                unsigned : 25;
+                unsigned index : TLB_INDEX_BITS;
+                unsigned : 32 - TLB_INDEX_BITS - 1;
                 unsigned p : 1;
 #endif

kernel/arch/mips32/src/exception.c

@@ -165 +165 @@
 static void interrupt_exception(unsigned int n, istate_t *istate)
 {
+        uint32_t ip;
+        uint32_t im;
+
         /* Decode interrupt number and process the interrupt */
-        uint32_t cause = (cp0_cause_read() >> 8) & 0xff;
+        ip = (cp0_cause_read() & cp0_cause_ip_mask) >> cp0_cause_ip_shift;
+        im = (cp0_status_read() & cp0_status_im_mask) >> cp0_status_im_shift;
         
         unsigned int i;
         for (i = 0; i < 8; i++) {
-                if (cause & (1 << i)) {
+
+                /*
+                 * The interrupt could only occur if it is unmasked in the
+                 * status register. On the other hand, an interrupt can be
+                 * apparently pending even if it is masked, so we need to
+                 * check both the masked and pending interrupts.
+                 */
+                if (im & ip & (1 << i)) {
                         irq_t *irq = irq_dispatch_and_lock(i);
                         if (irq) {

kernel/arch/mips32/src/interrupt.c

@@ -45 +45 @@
 #define IRQ_COUNT   8
 #define TIMER_IRQ   7
+
+#ifdef MACHINE_msim
 #define DORDER_IRQ  5
+#endif
 
 function virtual_timer_fnc = NULL;
 static irq_t timer_irq;
+
+#ifdef MACHINE_msim
 static irq_t dorder_irq;
+#endif
 
 // TODO: This is SMP unsafe!!!
@@ -151 +157 @@
 }
 
+#ifdef MACHINE_msim
 static irq_ownership_t dorder_claim(irq_t *irq)
 {
@@ -160 +167 @@
         dorder_ipi_ack(1 << dorder_cpuid());
 }
+#endif
 
 /* Initialize basic tables for exception dispatching */
@@ -176 +184 @@
         cp0_unmask_int(TIMER_IRQ);
         
+#ifdef MACHINE_msim
         irq_initialize(&dorder_irq);
         dorder_irq.devno = device_assign_devno();
@@ -184 +193 @@
         
         cp0_unmask_int(DORDER_IRQ);
+#endif
 }
 

kernel/arch/mips32/src/mips32.c

@@ -41 +41 @@
 #include <memstr.h>
 #include <userspace.h>
-#include <console/console.h>
 #include <syscall/syscall.h>
 #include <sysinfo/sysinfo.h>
 #include <arch/debug.h>
 #include <arch/debugger.h>
-#include <arch/drivers/msim.h>
-#include <genarch/fb/fb.h>
-#include <genarch/drivers/dsrln/dsrlnin.h>
-#include <genarch/drivers/dsrln/dsrlnout.h>
-#include <genarch/srln/srln.h>
+#include <arch/machine_func.h>
 
 /* Size of the code jumping to the exception handler code
@@ -70 +65 @@
 
 size_t cpu_count = 0;
+
+#if defined(MACHINE_lmalta) || defined(MACHINE_bmalta)
+size_t sdram_size = 0;
+#endif
 
 /** Performs mips32-specific initialization before main_bsp() is called. */
@@ -88 +87 @@
                         cpu_count++;
         }
+
+#if defined(MACHINE_lmalta) || defined(MACHINE_bmalta)
+        sdram_size = bootinfo->sdram_size;
+#endif
+
+        /* Initialize machine_ops pointer. */
+        machine_ops_init();
 }
 
@@ -124 +130 @@
 {
         interrupt_init();
-        
-#ifdef CONFIG_FB
-        /* GXemul framebuffer */
-        fb_properties_t gxemul_prop = {
-                .addr = 0x12000000,
-                .offset = 0,
-                .x = 640,
-                .y = 480,
-                .scan = 1920,
-                .visual = VISUAL_RGB_8_8_8,
-        };
-        
-        outdev_t *fbdev = fb_init(&gxemul_prop);
-        if (fbdev)
-                stdout_wire(fbdev);
-#endif
-
-#ifdef CONFIG_MIPS_PRN
-        outdev_t *dsrlndev = dsrlnout_init((ioport8_t *) MSIM_KBD_ADDRESS);
-        if (dsrlndev)
-                stdout_wire(dsrlndev);
-#endif
+
+        machine_init();
+        machine_output_init();
 }
 
@@ -158 +145 @@
 void arch_post_smp_init(void)
 {
-        static const char *platform;
-
         /* Set platform name. */
-#ifdef MACHINE_msim
-        platform = "msim";
-#endif
-#ifdef MACHINE_bgxemul
-        platform = "gxemul";
-#endif
-#ifdef MACHINE_lgxemul
-        platform = "gxemul";
-#endif
-        sysinfo_set_item_data("platform", NULL, (void *) platform,
-            str_size(platform));
-
-#ifdef CONFIG_MIPS_KBD
-        /*
-         * Initialize the msim/GXemul keyboard port. Then initialize the serial line
-         * module and connect it to the msim/GXemul keyboard. Enable keyboard interrupts.
-         */
-        dsrlnin_instance_t *dsrlnin_instance
-            = dsrlnin_init((dsrlnin_t *) MSIM_KBD_ADDRESS, MSIM_KBD_IRQ);
-        if (dsrlnin_instance) {
-                srln_instance_t *srln_instance = srln_init();
-                if (srln_instance) {
-                        indev_t *sink = stdin_wire();
-                        indev_t *srln = srln_wire(srln_instance, sink);
-                        dsrlnin_wire(dsrlnin_instance, srln);
-                        cp0_unmask_int(MSIM_KBD_IRQ);
-                }
-        }
-        
-        /*
-         * This is the necessary evil until the userspace driver is entirely
-         * self-sufficient.
-         */
-        sysinfo_set_item_val("kbd", NULL, true);
-        sysinfo_set_item_val("kbd.inr", NULL, MSIM_KBD_IRQ);
-        sysinfo_set_item_val("kbd.address.physical", NULL,
-            PA2KA(MSIM_KBD_ADDRESS));
-#endif
+        sysinfo_set_item_data("platform", NULL,
+            (void *) machine_get_platform_name(),
+            str_size(machine_get_platform_name()));
+
+        machine_input_init();
 }
 

kernel/arch/mips32/src/mm/frame.c

@@ -40 +40 @@
 #include <mm/asid.h>
 #include <config.h>
+#ifdef MACHINE_msim
 #include <arch/drivers/msim.h>
+#endif
+#include <arch/arch.h>
 #include <print.h>
 
@@ -84 +87 @@
                 return false;
 #endif
-        
-#if defined(MACHINE_lgxemul) || defined(MACHINE_bgxemul)
-        /* gxemul devices */
-        if (overlaps(frame << ZERO_PAGE_WIDTH, ZERO_PAGE_SIZE,
-            0x10000000, MiB2SIZE(256)))
+
+#if defined(MACHINE_lmalta) || defined(MACHINE_bmalta)
+        if (frame >= (sdram_size >> ZERO_PAGE_WIDTH))
                 return false;
 #endif
@@ -225 +226 @@
                                         if (ZERO_PAGE_VALUE != 0xdeadbeef)
                                                 avail = false;
-#if defined(MACHINE_lgxemul) || defined(MACHINE_bgxemul)
-                                        else {
-                                                ZERO_PAGE_VALUE_KSEG1(frame) = 0xaabbccdd;
-                                                if (ZERO_PAGE_VALUE_KSEG1(frame) != 0xaabbccdd)
-                                                        avail = false;
-                                        }
-#endif
                                 }
                         }
@@ -247 +241 @@
         /* Blacklist interrupt vector frame */
         frame_mark_unavailable(0, 1);
+
+#if defined(MACHINE_lmalta) || defined(MACHINE_bmalta)
+        /* Blacklist memory regions used by YAMON.
+         *
+         * The YAMON User's Manual vaguely says the following physical addresses
+         * are taken by YAMON:
+         *
+         * 0x1000       YAMON functions
+         * 0x5000       YAMON code
+         *
+         * These addresses overlap with the beginning of the SDRAM so we need to
+         * make sure they cannot be allocated.
+         *
+         * The User's Manual unfortunately does not say where does the SDRAM
+         * portion used by YAMON end.
+         *
+         * Looking into the YAMON 02.21 sources, it looks like the first free
+         * address is computed dynamically and depends on the size of the YAMON
+         * image. From the YAMON binary, it appears to be 0xc0d50 or roughly
+         * 772 KiB for that particular version.
+         *
+         * Linux is linked to 1MiB which seems to be a safe bet and a reasonable
+         * upper bound for memory taken by YAMON. We will use it too.
+         */
+        frame_mark_unavailable(0, 1024 * 1024 / FRAME_SIZE);
+#endif
         
         /* Cleanup */

kernel/arch/mips32/src/mm/tlb.c

@@ -48 +48 @@
 #include <symtab.h>
 
-static pte_t *find_mapping_and_check(uintptr_t, int, istate_t *);
+#define PFN_SHIFT       12
+#define VPN_SHIFT       12
+#define ADDR2VPN(a)     ((a) >> VPN_SHIFT)
+#define ADDR2VPN2(a)    (ADDR2VPN((a)) >> 1)
+#define VPN2ADDR(vpn)   ((vpn) << VPN_SHIFT)
+#define VPN22ADDR(vpn2) (VPN2ADDR(vpn2) << 1)
+#define PFN2ADDR(pfn)   ((pfn) << PFN_SHIFT)
+
+#define BANK_SELECT_BIT(a)      (((a) >> PAGE_WIDTH) & 1) 
+        
 
 /** Initialize TLB.
@@ -84 +93 @@
 {
         entry_lo_t lo;
-        entry_hi_t hi;
-        asid_t asid;
         uintptr_t badvaddr;
+        uintptr_t page;
         pte_t *pte;
         
         badvaddr = cp0_badvaddr_read();
-        asid = AS->asid;
-        
-        pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate);
-        if (pte) {
+        page = ALIGN_DOWN(badvaddr, PAGE_SIZE);
+
+        pte = page_mapping_find(AS, page, true);
+        if (pte && pte->p) {
                 /*
                  * Record access to PTE.
@@ -99 +107 @@
                 pte->a = 1;
 
-                tlb_prepare_entry_hi(&hi, asid, badvaddr);
                 tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d,
                     pte->cacheable, pte->pfn);
@@ -106 +113 @@
                  * New entry is to be inserted into TLB
                  */
-                cp0_entry_hi_write(hi.value);
-                if ((badvaddr / PAGE_SIZE) % 2 == 0) {
+                if (BANK_SELECT_BIT(badvaddr) == 0) {
                         cp0_entry_lo0_write(lo.value);
                         cp0_entry_lo1_write(0);
@@ -116 +122 @@
                 cp0_pagemask_write(TLB_PAGE_MASK_16K);
                 tlbwr();
-        }
+                return;
+        }
+
+        (void) as_page_fault(page, PF_ACCESS_READ, istate);
 }
 
@@ -125 +134 @@
 void tlb_invalid(istate_t *istate)
 {
+        entry_lo_t lo;
         tlb_index_t index;
         uintptr_t badvaddr;
-        entry_lo_t lo;
-        entry_hi_t hi;
+        uintptr_t page;
         pte_t *pte;
-
-        badvaddr = cp0_badvaddr_read();
 
         /*
          * Locate the faulting entry in TLB.
          */
-        hi.value = cp0_entry_hi_read();
-        tlb_prepare_entry_hi(&hi, hi.asid, badvaddr);
-        cp0_entry_hi_write(hi.value);
         tlbp();
         index.value = cp0_index_read();
 
+#if defined(PROCESSOR_4Kc)
+        /*
+         * This can happen on a 4Kc when Status.EXL is 1 and there is a TLB miss.
+         * EXL is 1 when interrupts are disabled. The combination of a TLB miss
+         * and disabled interrupts is possible in copy_to/from_uspace().
+         */
+        if (index.p) {
+                tlb_refill(istate);
+                return;
+        }
+#endif
+
         ASSERT(!index.p);
 
-        pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate);
-        if (pte) {
+        badvaddr = cp0_badvaddr_read();
+        page = ALIGN_DOWN(badvaddr, PAGE_SIZE);
+
+        pte = page_mapping_find(AS, page, true);
+        if (pte && pte->p) {
                 /*
                  * Read the faulting TLB entry.
@@ -162 +181 @@
                  * The entry is to be updated in TLB.
                  */
-                if ((badvaddr / PAGE_SIZE) % 2 == 0)
+                if (BANK_SELECT_BIT(badvaddr) == 0)
                         cp0_entry_lo0_write(lo.value);
                 else
                         cp0_entry_lo1_write(lo.value);
-                cp0_pagemask_write(TLB_PAGE_MASK_16K);
                 tlbwi();
-        }
+                return;
+        }
+
+        (void) as_page_fault(page, PF_ACCESS_READ, istate);
 }
 
@@ -177 +198 @@
 void tlb_modified(istate_t *istate)
 {
+        entry_lo_t lo;
         tlb_index_t index;
         uintptr_t badvaddr;
-        entry_lo_t lo;
-        entry_hi_t hi;
+        uintptr_t page;
         pte_t *pte;
 
         badvaddr = cp0_badvaddr_read();
+        page = ALIGN_DOWN(badvaddr, PAGE_SIZE);
 
         /*
          * Locate the faulting entry in TLB.
          */
-        hi.value = cp0_entry_hi_read();
-        tlb_prepare_entry_hi(&hi, hi.asid, badvaddr);
-        cp0_entry_hi_write(hi.value);
         tlbp();
         index.value = cp0_index_read();
 
         /*
-         * Fail if the entry is not in TLB.
+         * Emit warning if the entry is not in TLB.
+         *
+         * We do not assert on this because this could be a manifestation of
+         * an emulator bug, such as QEMU Bug #1128935:
+         * https://bugs.launchpad.net/qemu/+bug/1128935  
          */
-        ASSERT(!index.p);
-
-        pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate);
-        if (pte) {
+        if (index.p) {
+                printf("%s: TLBP failed in exception handler (badvaddr=%#"
+                    PRIxn ", ASID=%d).\n", __func__, badvaddr,
+                    AS ? AS->asid : -1);
+                return;
+        }
+
+        pte = page_mapping_find(AS, page, true);
+        if (pte && pte->p && pte->w) {
                 /*
                  * Read the faulting TLB entry.
@@ -218 +246 @@
                  * The entry is to be updated in TLB.
                  */
-                if ((badvaddr / PAGE_SIZE) % 2 == 0)
+                if (BANK_SELECT_BIT(badvaddr) == 0)
                         cp0_entry_lo0_write(lo.value);
                 else
                         cp0_entry_lo1_write(lo.value);
-                cp0_pagemask_write(TLB_PAGE_MASK_16K);
                 tlbwi();
-        }
-}
-
-/** Try to find PTE for faulting address.
- *
- * @param badvaddr      Faulting virtual address.
- * @param access        Access mode that caused the fault.
- * @param istate        Pointer to interrupted state.
- *
- * @return              PTE on success, NULL otherwise.
- */
-pte_t *find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate)
-{
-        entry_hi_t hi;
-        pte_t *pte;
-
-        hi.value = cp0_entry_hi_read();
-
-        ASSERT(hi.asid == AS->asid);
-
-        /*
-         * Check if the mapping exists in page tables.
-         */     
-        pte = page_mapping_find(AS, badvaddr, true);
-        if (pte && pte->p && (pte->w || access != PF_ACCESS_WRITE)) {
-                /*
-                 * Mapping found in page tables.
-                 * Immediately succeed.
-                 */
-                return pte;
-        }
-
-        /*
-         * Mapping not found in page tables.
-         * Resort to higher-level page fault handler.
-         */
-        if (as_page_fault(badvaddr, access, istate) == AS_PF_OK) {
-                pte = page_mapping_find(AS, badvaddr, true);
-                ASSERT(pte && pte->p);
-                ASSERT(pte->w || access != PF_ACCESS_WRITE);
-                return pte;
-        }
-
-        return NULL;
+                return;
+        }
+
+        (void) as_page_fault(page, PF_ACCESS_WRITE, istate);
 }
 
@@ -284 +271 @@
 void tlb_prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr)
 {
-        hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2);
+        hi->value = 0;
+        hi->vpn2 = ADDR2VPN2(ALIGN_DOWN(addr, PAGE_SIZE));
         hi->asid = asid;
 }
@@ -291 +279 @@
 void tlb_print(void)
 {
-        page_mask_t mask;
-        entry_lo_t lo0, lo1;
+        page_mask_t mask, mask_save;
+        entry_lo_t lo0, lo0_save, lo1, lo1_save;
         entry_hi_t hi, hi_save;
         unsigned int i;
 
         hi_save.value = cp0_entry_hi_read();
-        
-        printf("[nr] [asid] [vpn2] [mask] [gvdc] [pfn ]\n");
+        lo0_save.value = cp0_entry_lo0_read();
+        lo1_save.value = cp0_entry_lo1_read();
+        mask_save.value = cp0_pagemask_read();
+        
+        printf("[nr] [asid] [vpn2    ] [mask] [gvdc] [pfn     ]\n");
         
         for (i = 0; i < TLB_ENTRY_COUNT; i++) {
@@ -309 +300 @@
                 lo1.value = cp0_entry_lo1_read();
                 
-                printf("%-4u %-6u %#6x %#6x  %1u%1u%1u%1u  %#6x\n",
-                    i, hi.asid, hi.vpn2, mask.mask,
-                    lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn);
-                printf("                           %1u%1u%1u%1u  %#6x\n",
-                    lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);
+                printf("%-4u %-6u %0#10x %-#6x  %1u%1u%1u%1u  %0#10x\n",
+                    i, hi.asid, VPN22ADDR(hi.vpn2), mask.mask,
+                    lo0.g, lo0.v, lo0.d, lo0.c, PFN2ADDR(lo0.pfn));
+                printf("                               %1u%1u%1u%1u  %0#10x\n",
+                    lo1.g, lo1.v, lo1.d, lo1.c, PFN2ADDR(lo1.pfn));
         }
         
         cp0_entry_hi_write(hi_save.value);
+        cp0_entry_lo0_write(lo0_save.value);
+        cp0_entry_lo1_write(lo1_save.value);
+        cp0_pagemask_write(mask_save.value);
 }
 
@@ -322 +316 @@
 void tlb_invalidate_all(void)
 {
-        ipl_t ipl;
         entry_lo_t lo0, lo1;
         entry_hi_t hi_save;
         int i;
 
+        ASSERT(interrupts_disabled());
+
         hi_save.value = cp0_entry_hi_read();
-        ipl = interrupts_disable();
 
         for (i = TLB_WIRED; i < TLB_ENTRY_COUNT; i++) {
@@ -346 +340 @@
         }
         
-        interrupts_restore(ipl);
         cp0_entry_hi_write(hi_save.value);
 }
@@ -356 +349 @@
 void tlb_invalidate_asid(asid_t asid)
 {
-        ipl_t ipl;
         entry_lo_t lo0, lo1;
         entry_hi_t hi, hi_save;
         int i;
 
+        ASSERT(interrupts_disabled());
         ASSERT(asid != ASID_INVALID);
 
         hi_save.value = cp0_entry_hi_read();
-        ipl = interrupts_disable();
         
         for (i = 0; i < TLB_ENTRY_COUNT; i++) {
@@ -386 +378 @@
         }
         
-        interrupts_restore(ipl);
         cp0_entry_hi_write(hi_save.value);
 }
@@ -400 +391 @@
 {
         unsigned int i;
-        ipl_t ipl;
         entry_lo_t lo0, lo1;
         entry_hi_t hi, hi_save;
         tlb_index_t index;
+
+        ASSERT(interrupts_disabled());
         
         if (asid == ASID_INVALID)
@@ -409 +401 @@
 
         hi_save.value = cp0_entry_hi_read();
-        ipl = interrupts_disable();
 
         for (i = 0; i < cnt + 1; i += 2) {
-                hi.value = 0;
                 tlb_prepare_entry_hi(&hi, asid, page + i * PAGE_SIZE);
                 cp0_entry_hi_write(hi.value);
@@ -439 +429 @@
         }
         
-        interrupts_restore(ipl);
         cp0_entry_hi_write(hi_save.value);
 }

kernel/arch/mips64/src/mips64.c

@@ -46 +46 @@
 #include <arch/debug.h>
 #include <arch/debugger.h>
+#ifdef MACHINE_msim
 #include <arch/drivers/msim.h>
+#endif
 #include <genarch/fb/fb.h>
 #include <genarch/drivers/dsrln/dsrlnin.h>
@@ -125 +127 @@
         interrupt_init();
         
-#ifdef CONFIG_MIPS_PRN
+#ifdef CONFIG_MSIM_PRN
         outdev_t *dsrlndev = dsrlnout_init((ioport8_t *) MSIM_KBD_ADDRESS);
         if (dsrlndev)
@@ -151 +153 @@
             str_size(platform));
         
-#ifdef CONFIG_MIPS_KBD
-        /*
-         * Initialize the msim/GXemul keyboard port. Then initialize the serial line
-         * module and connect it to the msim/GXemul keyboard. Enable keyboard interrupts.
+#ifdef CONFIG_MSIM_KBD
+        /*
+         * Initialize the msim keyboard port. Then initialize the serial line
+         * module and connect it to the msim keyboard. Enable keyboard
+         * interrupts.
          */
         dsrlnin_instance_t *dsrlnin_instance

kernel/arch/mips64/src/mm/frame.c

@@ -40 +40 @@
 #include <mm/asid.h>
 #include <config.h>
+#ifdef MACHINE_msim
 #include <arch/drivers/msim.h>
+#endif
 #include <print.h>
 

kernel/generic/include/mm/tlb.h

@@ -73 +73 @@
 extern void tlb_shootdown_ipi_recv(void);
 #else
-#define tlb_shootdown_start(w, x, y, z) (0)
-#define tlb_shootdown_finalize(i)       ((i) = (i));
+#define tlb_shootdown_start(w, x, y, z) interrupts_disable()    
+#define tlb_shootdown_finalize(i)       (interrupts_restore(i));
 #define tlb_shootdown_ipi_recv()
 #endif /* CONFIG_SMP */