Changeset 96b02eb9 in mainline for kernel/arch
- Timestamp:
- 2010-12-14T12:52:38Z (15 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 6b10dab
- Parents:
- 554debd
- Location:
- kernel/arch
- Files:
-
- 28 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/abs32le/include/types.h
r554debd r96b02eb9 46 46 typedef uint32_t ipl_t; 47 47 48 typedef uint32_t unative_t;48 typedef uint32_t sysarg_t; 49 49 typedef int32_t native_t; 50 50 typedef uint32_t atomic_count_t; … … 57 57 58 58 #define PRIdn PRId32 /**< Format for native_t. */ 59 #define PRIun PRIu32 /**< Format for unative_t. */60 #define PRIxn PRIx32 /**< Format for hexadecimal unative_t. */59 #define PRIun PRIu32 /**< Format for sysarg_t. */ 60 #define PRIxn PRIx32 /**< Format for hexadecimal sysarg_t. */ 61 61 #define PRIua PRIu32 /**< Format for atomic_count_t. */ 62 62 -
kernel/arch/abs32le/src/abs32le.c
r554debd r96b02eb9 86 86 } 87 87 88 unative_t sys_tls_set(unative_t addr)88 sysarg_t sys_tls_set(sysarg_t addr) 89 89 { 90 90 return EOK; -
kernel/arch/amd64/include/asm.h
r554debd r96b02eb9 304 304 } 305 305 306 NO_TRACE static inline unative_t read_msr(uint32_t msr)306 NO_TRACE static inline sysarg_t read_msr(uint32_t msr) 307 307 { 308 308 uint32_t ax, dx; … … 343 343 asm volatile ( 344 344 "invlpg %[addr]\n" 345 :: [addr] "m" (*(( unative_t *) addr))345 :: [addr] "m" (*((sysarg_t *) addr)) 346 346 ); 347 347 } … … 398 398 } 399 399 400 #define GEN_READ_REG(reg) NO_TRACE static inline unative_t read_ ##reg (void) \400 #define GEN_READ_REG(reg) NO_TRACE static inline sysarg_t read_ ##reg (void) \ 401 401 { \ 402 unative_t res; \402 sysarg_t res; \ 403 403 asm volatile ( \ 404 404 "movq %%" #reg ", %[res]" \ … … 408 408 } 409 409 410 #define GEN_WRITE_REG(reg) NO_TRACE static inline void write_ ##reg ( unative_t regn) \410 #define GEN_WRITE_REG(reg) NO_TRACE static inline void write_ ##reg (sysarg_t regn) \ 411 411 { \ 412 412 asm volatile ( \ -
kernel/arch/amd64/include/proc/thread.h
r554debd r96b02eb9 41 41 42 42 typedef struct { 43 unative_t tls;43 sysarg_t tls; 44 44 /** User and kernel RSP for syscalls. */ 45 45 uint64_t syscall_rsp[2]; -
kernel/arch/amd64/include/types.h
r554debd r96b02eb9 43 43 typedef uint64_t ipl_t; 44 44 45 typedef uint64_t unative_t;45 typedef uint64_t sysarg_t; 46 46 typedef int64_t native_t; 47 47 typedef uint64_t atomic_count_t; … … 54 54 55 55 #define PRIdn PRId64 /**< Format for native_t. */ 56 #define PRIun PRIu64 /**< Format for unative_t. */57 #define PRIxn PRIx64 /**< Format for hexadecimal unative_t. */56 #define PRIun PRIu64 /**< Format for sysarg_t. */ 57 #define PRIxn PRIx64 /**< Format for hexadecimal sysarg_t. */ 58 58 #define PRIua PRIu64 /**< Format for atomic_count_t. */ 59 59 -
kernel/arch/amd64/src/amd64.c
r554debd r96b02eb9 256 256 * we need not to go to CPL0 to read it. 257 257 */ 258 unative_t sys_tls_set(unative_t addr)258 sysarg_t sys_tls_set(sysarg_t addr) 259 259 { 260 260 THREAD->arch.tls = addr; -
kernel/arch/amd64/src/debugger.c
r554debd r96b02eb9 125 125 126 126 /* Disable breakpoint in DR7 */ 127 unative_t dr7 = read_dr7();127 sysarg_t dr7 = read_dr7(); 128 128 dr7 &= ~(0x02U << (curidx * 2)); 129 129 … … 152 152 if (!(flags & BKPOINT_INSTR)) { 153 153 #ifdef __32_BITS__ 154 dr7 |= (( unative_t) 0x03U) << (18 + 4 * curidx);154 dr7 |= ((sysarg_t) 0x03U) << (18 + 4 * curidx); 155 155 #endif 156 156 157 157 #ifdef __64_BITS__ 158 dr7 |= (( unative_t) 0x02U) << (18 + 4 * curidx);158 dr7 |= ((sysarg_t) 0x02U) << (18 + 4 * curidx); 159 159 #endif 160 160 161 161 if ((flags & BKPOINT_WRITE)) 162 dr7 |= (( unative_t) 0x01U) << (16 + 4 * curidx);162 dr7 |= ((sysarg_t) 0x01U) << (16 + 4 * curidx); 163 163 else if ((flags & BKPOINT_READ_WRITE)) 164 dr7 |= (( unative_t) 0x03U) << (16 + 4 * curidx);164 dr7 |= ((sysarg_t) 0x03U) << (16 + 4 * curidx); 165 165 } 166 166 … … 227 227 if (!(breakpoints[slot].flags & BKPOINT_INSTR)) { 228 228 if ((breakpoints[slot].flags & BKPOINT_CHECK_ZERO)) { 229 if (*(( unative_t *) breakpoints[slot].address) != 0)229 if (*((sysarg_t *) breakpoints[slot].address) != 0) 230 230 return; 231 231 … … 234 234 } else { 235 235 printf("Data watchpoint - new data: %#" PRIxn "\n", 236 *(( unative_t *) breakpoints[slot].address));236 *((sysarg_t *) breakpoints[slot].address)); 237 237 } 238 238 } … … 279 279 #endif 280 280 281 unative_t dr6 = read_dr6();281 sysarg_t dr6 = read_dr6(); 282 282 283 283 unsigned int i; … … 384 384 int cmd_del_breakpoint(cmd_arg_t *argv) 385 385 { 386 unative_t bpno = argv->intval;386 sysarg_t bpno = argv->intval; 387 387 if (bpno > BKPOINTS_MAX) { 388 388 printf("Invalid breakpoint number.\n"); -
kernel/arch/arm32/include/types.h
r554debd r96b02eb9 50 50 typedef uint32_t ipl_t; 51 51 52 typedef uint32_t unative_t;52 typedef uint32_t sysarg_t; 53 53 typedef int32_t native_t; 54 54 typedef uint32_t atomic_count_t; … … 61 61 62 62 #define PRIdn PRId32 /**< Format for native_t. */ 63 #define PRIun PRIu32 /**< Format for unative_t. */64 #define PRIxn PRIx32 /**< Format for hexadecimal unative_t. */63 #define PRIun PRIu32 /**< Format for sysarg_t. */ 64 #define PRIxn PRIx32 /**< Format for hexadecimal sysarg_t. */ 65 65 #define PRIua PRIu32 /**< Format for atomic_count_t. */ 66 66 -
kernel/arch/arm32/src/mach/testarm/testarm.c
r554debd r96b02eb9 123 123 sysinfo_set_item_val("kbd", NULL, true); 124 124 sysinfo_set_item_val("kbd.inr", NULL, GXEMUL_KBD_IRQ); 125 sysinfo_set_item_val("kbd.address.virtual", NULL, ( unative_t) gxemul_kbd);125 sysinfo_set_item_val("kbd.address.virtual", NULL, (sysarg_t) gxemul_kbd); 126 126 #endif 127 127 } -
kernel/arch/ia32/include/asm.h
r554debd r96b02eb9 64 64 } 65 65 66 #define GEN_READ_REG(reg) NO_TRACE static inline unative_t read_ ##reg (void) \66 #define GEN_READ_REG(reg) NO_TRACE static inline sysarg_t read_ ##reg (void) \ 67 67 { \ 68 unative_t res; \68 sysarg_t res; \ 69 69 asm volatile ( \ 70 70 "movl %%" #reg ", %[res]" \ … … 74 74 } 75 75 76 #define GEN_WRITE_REG(reg) NO_TRACE static inline void write_ ##reg ( unative_t regn) \76 #define GEN_WRITE_REG(reg) NO_TRACE static inline void write_ ##reg (sysarg_t regn) \ 77 77 { \ 78 78 asm volatile ( \ … … 366 366 asm volatile ( 367 367 "invlpg %[addr]\n" 368 :: [addr] "m" (*( unative_t *) addr)368 :: [addr] "m" (*(sysarg_t *) addr) 369 369 ); 370 370 } -
kernel/arch/ia32/include/proc/thread.h
r554debd r96b02eb9 39 39 40 40 typedef struct { 41 unative_t tls;41 sysarg_t tls; 42 42 } thread_arch_t; 43 43 -
kernel/arch/ia32/include/types.h
r554debd r96b02eb9 43 43 typedef uint32_t ipl_t; 44 44 45 typedef uint32_t unative_t;45 typedef uint32_t sysarg_t; 46 46 typedef int32_t native_t; 47 47 typedef uint32_t atomic_count_t; … … 54 54 55 55 #define PRIdn PRId32 /**< Format for native_t. */ 56 #define PRIun PRIu32 /**< Format for unative_t. */57 #define PRIxn PRIx32 /**< Format for hexadecimal unative_t. */56 #define PRIun PRIu32 /**< Format for sysarg_t. */ 57 #define PRIxn PRIx32 /**< Format for hexadecimal sysarg_t. */ 58 58 #define PRIua PRIu32 /**< Format for atomic_count_t. */ 59 59 -
kernel/arch/ia32/src/ia32.c
r554debd r96b02eb9 211 211 * selector, and the descriptor->base is the correct address. 212 212 */ 213 unative_t sys_tls_set(unative_t addr)213 sysarg_t sys_tls_set(sysarg_t addr) 214 214 { 215 215 THREAD->arch.tls = addr; -
kernel/arch/ia64/include/bootinfo.h
r554debd r96b02eb9 62 62 unsigned int memmap_items; 63 63 64 unative_t *sapic;64 sysarg_t *sapic; 65 65 unsigned long sys_freq; 66 66 unsigned long freq_scale; -
kernel/arch/ia64/include/types.h
r554debd r96b02eb9 43 43 typedef uint64_t ipl_t; 44 44 45 typedef uint64_t unative_t;45 typedef uint64_t sysarg_t; 46 46 typedef int64_t native_t; 47 47 typedef uint64_t atomic_count_t; 48 48 49 49 typedef struct { 50 unative_t fnc;51 unative_t gp;50 sysarg_t fnc; 51 sysarg_t gp; 52 52 } __attribute__((may_alias)) fncptr_t; 53 53 … … 56 56 57 57 #define PRIdn PRId64 /**< Format for native_t. */ 58 #define PRIun PRIu64 /**< Format for unative_t. */59 #define PRIxn PRIx64 /**< Format for hexadecimal unative_t. */58 #define PRIun PRIu64 /**< Format for sysarg_t. */ 59 #define PRIxn PRIx64 /**< Format for hexadecimal sysarg_t. */ 60 60 #define PRIua PRIu64 /**< Format for atomic_count_t. */ 61 61 -
kernel/arch/ia64/src/ia64.c
r554debd r96b02eb9 104 104 static void iosapic_init(void) 105 105 { 106 uint64_t IOSAPIC = PA2KA(( unative_t)(iosapic_base)) | FW_OFFSET;106 uint64_t IOSAPIC = PA2KA((sysarg_t)(iosapic_base)) | FW_OFFSET; 107 107 int i; 108 108 … … 251 251 * We use r13 (a.k.a. tp) for this purpose. 252 252 */ 253 unative_t sys_tls_set(unative_t addr)253 sysarg_t sys_tls_set(sysarg_t addr) 254 254 { 255 255 return 0; … … 274 274 void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller) 275 275 { 276 fptr->fnc = ( unative_t) addr;277 fptr->gp = (( unative_t *) caller)[1];276 fptr->fnc = (sysarg_t) addr; 277 fptr->gp = ((sysarg_t *) caller)[1]; 278 278 279 279 return (void *) fptr; -
kernel/arch/mips32/include/debugger.h
r554debd r96b02eb9 58 58 59 59 typedef struct { 60 uintptr_t address; 61 unative_t instruction; /**< Original instruction */62 unative_t nextinstruction; /**< Original instruction following break */63 unsigned int flags; 60 uintptr_t address; /**< Breakpoint address */ 61 sysarg_t instruction; /**< Original instruction */ 62 sysarg_t nextinstruction; /**< Original instruction following break */ 63 unsigned int flags; /**< Flags regarding breakpoint */ 64 64 size_t counter; 65 65 void (*bkfunc)(void *, istate_t *); … … 68 68 extern bpinfo_t breakpoints[BKPOINTS_MAX]; 69 69 70 extern bool is_jump( unative_t);70 extern bool is_jump(sysarg_t); 71 71 72 72 extern void debugger_init(void); -
kernel/arch/mips32/include/fpu_context.h
r554debd r96b02eb9 38 38 #include <typedefs.h> 39 39 40 #define FPU_CONTEXT_ALIGN sizeof( unative_t)40 #define FPU_CONTEXT_ALIGN sizeof(sysarg_t) 41 41 42 42 typedef struct { 43 unative_t dregs[32];44 unative_t cregs[32];43 sysarg_t dregs[32]; 44 sysarg_t cregs[32]; 45 45 } fpu_context_t; 46 46 -
kernel/arch/mips32/include/types.h
r554debd r96b02eb9 43 43 typedef uint32_t ipl_t; 44 44 45 typedef uint32_t unative_t;45 typedef uint32_t sysarg_t; 46 46 typedef int32_t native_t; 47 47 typedef uint32_t atomic_count_t; … … 54 54 55 55 #define PRIdn PRId32 /**< Format for native_t. */ 56 #define PRIun PRIu32 /**< Format for unative_t. */57 #define PRIxn PRIx32 /**< Format for hexadecimal unative_t. */56 #define PRIun PRIu32 /**< Format for sysarg_t. */ 57 #define PRIxn PRIx32 /**< Format for hexadecimal sysarg_t. */ 58 58 #define PRIua PRIu32 /**< Format for atomic_count_t. */ 59 59 -
kernel/arch/mips32/src/debugger.c
r554debd r96b02eb9 134 134 * 135 135 */ 136 bool is_jump( unative_t instr)136 bool is_jump(sysarg_t instr) 137 137 { 138 138 unsigned int i; … … 166 166 return 0; 167 167 } else if ((breakpoints[i].address == (uintptr_t) argv->intval + 168 sizeof( unative_t)) || (breakpoints[i].address ==169 (uintptr_t) argv->intval - sizeof( unative_t))) {168 sizeof(sysarg_t)) || (breakpoints[i].address == 169 (uintptr_t) argv->intval - sizeof(sysarg_t))) { 170 170 printf("Adjacent breakpoints not supported, conflict " 171 171 "with %d.\n", i); … … 194 194 195 195 cur->address = (uintptr_t) argv->intval; 196 cur->instruction = (( unative_t *) cur->address)[0];197 cur->nextinstruction = (( unative_t *) cur->address)[1];196 cur->instruction = ((sysarg_t *) cur->address)[0]; 197 cur->nextinstruction = ((sysarg_t *) cur->address)[1]; 198 198 if (argv == &add_argv) { 199 199 cur->flags = 0; … … 209 209 210 210 /* Set breakpoint */ 211 *(( unative_t *) cur->address) = 0x0d;211 *((sysarg_t *) cur->address) = 0x0d; 212 212 smc_coherence(cur->address); 213 213 … … 341 341 /* Reinst only breakpoint */ 342 342 if ((breakpoints[i].flags & BKPOINT_REINST) && 343 (fireaddr == breakpoints[i].address + sizeof( unative_t))) {343 (fireaddr == breakpoints[i].address + sizeof(sysarg_t))) { 344 344 cur = &breakpoints[i]; 345 345 break; -
kernel/arch/mips32/src/mips32.c
r554debd r96b02eb9 233 233 * possible to have it separately in the future. 234 234 */ 235 unative_t sys_tls_set(unative_t addr)235 sysarg_t sys_tls_set(sysarg_t addr) 236 236 { 237 237 return 0; -
kernel/arch/ppc32/include/exception.h
r554debd r96b02eb9 98 98 } 99 99 100 NO_TRACE static inline unative_t istate_get_pc(istate_t *istate)100 NO_TRACE static inline sysarg_t istate_get_pc(istate_t *istate) 101 101 { 102 102 return istate->pc; 103 103 } 104 104 105 NO_TRACE static inline unative_t istate_get_fp(istate_t *istate)105 NO_TRACE static inline sysarg_t istate_get_fp(istate_t *istate) 106 106 { 107 107 return istate->sp; -
kernel/arch/ppc32/include/types.h
r554debd r96b02eb9 43 43 typedef uint32_t ipl_t; 44 44 45 typedef uint32_t unative_t;45 typedef uint32_t sysarg_t; 46 46 typedef int32_t native_t; 47 47 typedef uint32_t atomic_count_t; … … 54 54 55 55 #define PRIdn PRId32 /**< Format for native_t. */ 56 #define PRIun PRIu32 /**< Format for unative_t. */57 #define PRIxn PRIx32 /**< Format for hexadecimal unative_t. */56 #define PRIun PRIu32 /**< Format for sysarg_t. */ 57 #define PRIxn PRIx32 /**< Format for hexadecimal sysarg_t. */ 58 58 #define PRIua PRIu32 /**< Format for atomic_count_t. */ 59 59 -
kernel/arch/sparc64/include/mm/sun4u/tlb.h
r554debd r96b02eb9 678 678 } 679 679 680 extern void fast_instruction_access_mmu_miss( unative_t, istate_t *);680 extern void fast_instruction_access_mmu_miss(sysarg_t, istate_t *); 681 681 extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t, istate_t *); 682 682 extern void fast_data_access_protection(tlb_tag_access_reg_t , istate_t *); -
kernel/arch/sparc64/include/mm/sun4v/tlb.h
r554debd r96b02eb9 141 141 } 142 142 143 extern void fast_instruction_access_mmu_miss( unative_t, istate_t *);144 extern void fast_data_access_mmu_miss( unative_t, istate_t *);145 extern void fast_data_access_protection( unative_t, istate_t *);143 extern void fast_instruction_access_mmu_miss(sysarg_t, istate_t *); 144 extern void fast_data_access_mmu_miss(sysarg_t, istate_t *); 145 extern void fast_data_access_protection(sysarg_t, istate_t *); 146 146 147 147 extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool); -
kernel/arch/sparc64/include/types.h
r554debd r96b02eb9 43 43 typedef uint64_t ipl_t; 44 44 45 typedef uint64_t unative_t;45 typedef uint64_t sysarg_t; 46 46 typedef int64_t native_t; 47 47 typedef uint64_t atomic_count_t; … … 56 56 57 57 #define PRIdn PRId64 /**< Format for native_t. */ 58 #define PRIun PRIu64 /**< Format for unative_t. */59 #define PRIxn PRIx64 /**< Format for hexadecimal unative_t. */58 #define PRIun PRIu64 /**< Format for sysarg_t. */ 59 #define PRIxn PRIx64 /**< Format for hexadecimal sysarg_t. */ 60 60 #define PRIua PRIu64 /**< Format for atomic_count_t. */ 61 61 -
kernel/arch/sparc64/src/mm/sun4u/tlb.c
r554debd r96b02eb9 200 200 201 201 /** ITLB miss handler. */ 202 void fast_instruction_access_mmu_miss( unative_t unused, istate_t *istate)202 void fast_instruction_access_mmu_miss(sysarg_t unused, istate_t *istate) 203 203 { 204 204 uintptr_t page_16k = ALIGN_DOWN(istate->tpc, PAGE_SIZE); -
kernel/arch/sparc64/src/mm/sun4v/tlb.c
r554debd r96b02eb9 213 213 214 214 /** ITLB miss handler. */ 215 void fast_instruction_access_mmu_miss( unative_t unused, istate_t *istate)215 void fast_instruction_access_mmu_miss(sysarg_t unused, istate_t *istate) 216 216 { 217 217 uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);
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