source: mainline/kernel/arch/amd64/include/asm.h@ 96b02eb9

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 96b02eb9 was 96b02eb9, checked in by Martin Decky <martin@…>, 15 years ago

more unification of basic types

  • use sysarg_t and native_t (unsigned and signed variant) in both kernel and uspace
  • remove ipcarg_t in favour of sysarg_t

(no change in functionality)
  • Property mode set to 100644
File size: 9.5 KB
Line 
1/*
2 * Copyright (c) 2005 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup amd64
30 * @{
31 */
32/** @file
33 */
34
35#ifndef KERN_amd64_ASM_H_
36#define KERN_amd64_ASM_H_
37
38#include <config.h>
39#include <typedefs.h>
40#include <arch/cpu.h>
41#include <trace.h>
42
43/** Return base address of current stack.
44 *
45 * Return the base address of the current stack.
46 * The stack is assumed to be STACK_SIZE bytes long.
47 * The stack must start on page boundary.
48 *
49 */
50NO_TRACE static inline uintptr_t get_stack_base(void)
51{
52 uintptr_t v;
53
54 asm volatile (
55 "andq %%rsp, %[v]\n"
56 : [v] "=r" (v)
57 : "0" (~((uint64_t) STACK_SIZE - 1))
58 );
59
60 return v;
61}
62
63NO_TRACE static inline void cpu_sleep(void)
64{
65 asm volatile (
66 "hlt\n"
67 );
68}
69
70NO_TRACE static inline void __attribute__((noreturn)) cpu_halt(void)
71{
72 while (true) {
73 asm volatile (
74 "hlt\n"
75 );
76 }
77}
78
79/** Byte from port
80 *
81 * Get byte from port
82 *
83 * @param port Port to read from
84 * @return Value read
85 *
86 */
87NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
88{
89 uint8_t val;
90
91 asm volatile (
92 "inb %w[port], %b[val]\n"
93 : [val] "=a" (val)
94 : [port] "d" (port)
95 );
96
97 return val;
98}
99
100/** Word from port
101 *
102 * Get word from port
103 *
104 * @param port Port to read from
105 * @return Value read
106 *
107 */
108NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
109{
110 uint16_t val;
111
112 asm volatile (
113 "inw %w[port], %w[val]\n"
114 : [val] "=a" (val)
115 : [port] "d" (port)
116 );
117
118 return val;
119}
120
121/** Double word from port
122 *
123 * Get double word from port
124 *
125 * @param port Port to read from
126 * @return Value read
127 *
128 */
129NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
130{
131 uint32_t val;
132
133 asm volatile (
134 "inl %w[port], %[val]\n"
135 : [val] "=a" (val)
136 : [port] "d" (port)
137 );
138
139 return val;
140}
141
142/** Byte to port
143 *
144 * Output byte to port
145 *
146 * @param port Port to write to
147 * @param val Value to write
148 *
149 */
150NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t val)
151{
152 asm volatile (
153 "outb %b[val], %w[port]\n"
154 :: [val] "a" (val),
155 [port] "d" (port)
156 );
157}
158
159/** Word to port
160 *
161 * Output word to port
162 *
163 * @param port Port to write to
164 * @param val Value to write
165 *
166 */
167NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t val)
168{
169 asm volatile (
170 "outw %w[val], %w[port]\n"
171 :: [val] "a" (val),
172 [port] "d" (port)
173 );
174}
175
176/** Double word to port
177 *
178 * Output double word to port
179 *
180 * @param port Port to write to
181 * @param val Value to write
182 *
183 */
184NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t val)
185{
186 asm volatile (
187 "outl %[val], %w[port]\n"
188 :: [val] "a" (val),
189 [port] "d" (port)
190 );
191}
192
193/** Swap Hidden part of GS register with visible one */
194NO_TRACE static inline void swapgs(void)
195{
196 asm volatile (
197 "swapgs"
198 );
199}
200
201/** Enable interrupts.
202 *
203 * Enable interrupts and return previous
204 * value of EFLAGS.
205 *
206 * @return Old interrupt priority level.
207 *
208 */
209NO_TRACE static inline ipl_t interrupts_enable(void) {
210 ipl_t v;
211
212 asm volatile (
213 "pushfq\n"
214 "popq %[v]\n"
215 "sti\n"
216 : [v] "=r" (v)
217 );
218
219 return v;
220}
221
222/** Disable interrupts.
223 *
224 * Disable interrupts and return previous
225 * value of EFLAGS.
226 *
227 * @return Old interrupt priority level.
228 *
229 */
230NO_TRACE static inline ipl_t interrupts_disable(void) {
231 ipl_t v;
232
233 asm volatile (
234 "pushfq\n"
235 "popq %[v]\n"
236 "cli\n"
237 : [v] "=r" (v)
238 );
239
240 return v;
241}
242
243/** Restore interrupt priority level.
244 *
245 * Restore EFLAGS.
246 *
247 * @param ipl Saved interrupt priority level.
248 *
249 */
250NO_TRACE static inline void interrupts_restore(ipl_t ipl) {
251 asm volatile (
252 "pushq %[ipl]\n"
253 "popfq\n"
254 :: [ipl] "r" (ipl)
255 );
256}
257
258/** Return interrupt priority level.
259 *
260 * Return EFLAFS.
261 *
262 * @return Current interrupt priority level.
263 *
264 */
265NO_TRACE static inline ipl_t interrupts_read(void) {
266 ipl_t v;
267
268 asm volatile (
269 "pushfq\n"
270 "popq %[v]\n"
271 : [v] "=r" (v)
272 );
273
274 return v;
275}
276
277/** Check interrupts state.
278 *
279 * @return True if interrupts are disabled.
280 *
281 */
282NO_TRACE static inline bool interrupts_disabled(void)
283{
284 ipl_t v;
285
286 asm volatile (
287 "pushfq\n"
288 "popq %[v]\n"
289 : [v] "=r" (v)
290 );
291
292 return ((v & RFLAGS_IF) == 0);
293}
294
295/** Write to MSR */
296NO_TRACE static inline void write_msr(uint32_t msr, uint64_t value)
297{
298 asm volatile (
299 "wrmsr\n"
300 :: "c" (msr),
301 "a" ((uint32_t) (value)),
302 "d" ((uint32_t) (value >> 32))
303 );
304}
305
306NO_TRACE static inline sysarg_t read_msr(uint32_t msr)
307{
308 uint32_t ax, dx;
309
310 asm volatile (
311 "rdmsr\n"
312 : "=a" (ax), "=d" (dx)
313 : "c" (msr)
314 );
315
316 return ((uint64_t) dx << 32) | ax;
317}
318
319/** Enable local APIC
320 *
321 * Enable local APIC in MSR.
322 *
323 */
324NO_TRACE static inline void enable_l_apic_in_msr()
325{
326 asm volatile (
327 "movl $0x1b, %%ecx\n"
328 "rdmsr\n"
329 "orl $(1 << 11),%%eax\n"
330 "orl $(0xfee00000),%%eax\n"
331 "wrmsr\n"
332 ::: "%eax", "%ecx", "%edx"
333 );
334}
335
336/** Invalidate TLB Entry.
337 *
338 * @param addr Address on a page whose TLB entry is to be invalidated.
339 *
340 */
341NO_TRACE static inline void invlpg(uintptr_t addr)
342{
343 asm volatile (
344 "invlpg %[addr]\n"
345 :: [addr] "m" (*((sysarg_t *) addr))
346 );
347}
348
349/** Load GDTR register from memory.
350 *
351 * @param gdtr_reg Address of memory from where to load GDTR.
352 *
353 */
354NO_TRACE static inline void gdtr_load(ptr_16_64_t *gdtr_reg)
355{
356 asm volatile (
357 "lgdtq %[gdtr_reg]\n"
358 :: [gdtr_reg] "m" (*gdtr_reg)
359 );
360}
361
362/** Store GDTR register to memory.
363 *
364 * @param gdtr_reg Address of memory to where to load GDTR.
365 *
366 */
367NO_TRACE static inline void gdtr_store(ptr_16_64_t *gdtr_reg)
368{
369 asm volatile (
370 "sgdtq %[gdtr_reg]\n"
371 :: [gdtr_reg] "m" (*gdtr_reg)
372 );
373}
374
375/** Load IDTR register from memory.
376 *
377 * @param idtr_reg Address of memory from where to load IDTR.
378 *
379 */
380NO_TRACE static inline void idtr_load(ptr_16_64_t *idtr_reg)
381{
382 asm volatile (
383 "lidtq %[idtr_reg]\n"
384 :: [idtr_reg] "m" (*idtr_reg));
385}
386
387/** Load TR from descriptor table.
388 *
389 * @param sel Selector specifying descriptor of TSS segment.
390 *
391 */
392NO_TRACE static inline void tr_load(uint16_t sel)
393{
394 asm volatile (
395 "ltr %[sel]"
396 :: [sel] "r" (sel)
397 );
398}
399
400#define GEN_READ_REG(reg) NO_TRACE static inline sysarg_t read_ ##reg (void) \
401 { \
402 sysarg_t res; \
403 asm volatile ( \
404 "movq %%" #reg ", %[res]" \
405 : [res] "=r" (res) \
406 ); \
407 return res; \
408 }
409
410#define GEN_WRITE_REG(reg) NO_TRACE static inline void write_ ##reg (sysarg_t regn) \
411 { \
412 asm volatile ( \
413 "movq %[regn], %%" #reg \
414 :: [regn] "r" (regn) \
415 ); \
416 }
417
418GEN_READ_REG(cr0)
419GEN_READ_REG(cr2)
420GEN_READ_REG(cr3)
421GEN_WRITE_REG(cr3)
422
423GEN_READ_REG(dr0)
424GEN_READ_REG(dr1)
425GEN_READ_REG(dr2)
426GEN_READ_REG(dr3)
427GEN_READ_REG(dr6)
428GEN_READ_REG(dr7)
429
430GEN_WRITE_REG(dr0)
431GEN_WRITE_REG(dr1)
432GEN_WRITE_REG(dr2)
433GEN_WRITE_REG(dr3)
434GEN_WRITE_REG(dr6)
435GEN_WRITE_REG(dr7)
436
437extern void asm_delay_loop(uint32_t);
438extern void asm_fake_loop(uint32_t);
439
440extern uintptr_t int_0;
441extern uintptr_t int_1;
442extern uintptr_t int_2;
443extern uintptr_t int_3;
444extern uintptr_t int_4;
445extern uintptr_t int_5;
446extern uintptr_t int_6;
447extern uintptr_t int_7;
448extern uintptr_t int_8;
449extern uintptr_t int_9;
450extern uintptr_t int_10;
451extern uintptr_t int_11;
452extern uintptr_t int_12;
453extern uintptr_t int_13;
454extern uintptr_t int_14;
455extern uintptr_t int_15;
456extern uintptr_t int_16;
457extern uintptr_t int_17;
458extern uintptr_t int_18;
459extern uintptr_t int_19;
460extern uintptr_t int_20;
461extern uintptr_t int_21;
462extern uintptr_t int_22;
463extern uintptr_t int_23;
464extern uintptr_t int_24;
465extern uintptr_t int_25;
466extern uintptr_t int_26;
467extern uintptr_t int_27;
468extern uintptr_t int_28;
469extern uintptr_t int_29;
470extern uintptr_t int_30;
471extern uintptr_t int_31;
472extern uintptr_t int_32;
473extern uintptr_t int_33;
474extern uintptr_t int_34;
475extern uintptr_t int_35;
476extern uintptr_t int_36;
477extern uintptr_t int_37;
478extern uintptr_t int_38;
479extern uintptr_t int_39;
480extern uintptr_t int_40;
481extern uintptr_t int_41;
482extern uintptr_t int_42;
483extern uintptr_t int_43;
484extern uintptr_t int_44;
485extern uintptr_t int_45;
486extern uintptr_t int_46;
487extern uintptr_t int_47;
488extern uintptr_t int_48;
489extern uintptr_t int_49;
490extern uintptr_t int_50;
491extern uintptr_t int_51;
492extern uintptr_t int_52;
493extern uintptr_t int_53;
494extern uintptr_t int_54;
495extern uintptr_t int_55;
496extern uintptr_t int_56;
497extern uintptr_t int_57;
498extern uintptr_t int_58;
499extern uintptr_t int_59;
500extern uintptr_t int_60;
501extern uintptr_t int_61;
502extern uintptr_t int_62;
503extern uintptr_t int_63;
504
505#endif
506
507/** @}
508 */
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