source: mainline/kernel/arch/ia32/include/asm.h@ 96b02eb9

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 96b02eb9 was 96b02eb9, checked in by Martin Decky <martin@…>, 15 years ago

more unification of basic types

  • use sysarg_t and native_t (unsigned and signed variant) in both kernel and uspace
  • remove ipcarg_t in favour of sysarg_t

(no change in functionality)
  • Property mode set to 100644
File size: 9.3 KB
Line 
1/*
2 * Copyright (c) 2001-2004 Jakub Jermar
3 * Copyright (c) 2005 Sergey Bondari
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/** @addtogroup ia32
31 * @{
32 */
33/** @file
34 */
35
36#ifndef KERN_ia32_ASM_H_
37#define KERN_ia32_ASM_H_
38
39#include <arch/pm.h>
40#include <arch/cpu.h>
41#include <typedefs.h>
42#include <config.h>
43#include <trace.h>
44
45/** Halt CPU
46 *
47 * Halt the current CPU.
48 *
49 */
50NO_TRACE static inline __attribute__((noreturn)) void cpu_halt(void)
51{
52 while (true) {
53 asm volatile (
54 "hlt\n"
55 );
56 }
57}
58
59NO_TRACE static inline void cpu_sleep(void)
60{
61 asm volatile (
62 "hlt\n"
63 );
64}
65
66#define GEN_READ_REG(reg) NO_TRACE static inline sysarg_t read_ ##reg (void) \
67 { \
68 sysarg_t res; \
69 asm volatile ( \
70 "movl %%" #reg ", %[res]" \
71 : [res] "=r" (res) \
72 ); \
73 return res; \
74 }
75
76#define GEN_WRITE_REG(reg) NO_TRACE static inline void write_ ##reg (sysarg_t regn) \
77 { \
78 asm volatile ( \
79 "movl %[regn], %%" #reg \
80 :: [regn] "r" (regn) \
81 ); \
82 }
83
84GEN_READ_REG(cr0)
85GEN_READ_REG(cr2)
86GEN_READ_REG(cr3)
87GEN_WRITE_REG(cr3)
88
89GEN_READ_REG(dr0)
90GEN_READ_REG(dr1)
91GEN_READ_REG(dr2)
92GEN_READ_REG(dr3)
93GEN_READ_REG(dr6)
94GEN_READ_REG(dr7)
95
96GEN_WRITE_REG(dr0)
97GEN_WRITE_REG(dr1)
98GEN_WRITE_REG(dr2)
99GEN_WRITE_REG(dr3)
100GEN_WRITE_REG(dr6)
101GEN_WRITE_REG(dr7)
102
103/** Byte to port
104 *
105 * Output byte to port
106 *
107 * @param port Port to write to
108 * @param val Value to write
109 *
110 */
111NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t val)
112{
113 asm volatile (
114 "outb %b[val], %w[port]\n"
115 :: [val] "a" (val),
116 [port] "d" (port)
117 );
118}
119
120/** Word to port
121 *
122 * Output word to port
123 *
124 * @param port Port to write to
125 * @param val Value to write
126 *
127 */
128NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t val)
129{
130 asm volatile (
131 "outw %w[val], %w[port]\n"
132 :: [val] "a" (val),
133 [port] "d" (port)
134 );
135}
136
137/** Double word to port
138 *
139 * Output double word to port
140 *
141 * @param port Port to write to
142 * @param val Value to write
143 *
144 */
145NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t val)
146{
147 asm volatile (
148 "outl %[val], %w[port]\n"
149 :: [val] "a" (val),
150 [port] "d" (port)
151 );
152}
153
154/** Byte from port
155 *
156 * Get byte from port
157 *
158 * @param port Port to read from
159 * @return Value read
160 *
161 */
162NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
163{
164 uint8_t val;
165
166 asm volatile (
167 "inb %w[port], %b[val]\n"
168 : [val] "=a" (val)
169 : [port] "d" (port)
170 );
171
172 return val;
173}
174
175/** Word from port
176 *
177 * Get word from port
178 *
179 * @param port Port to read from
180 * @return Value read
181 *
182 */
183NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
184{
185 uint16_t val;
186
187 asm volatile (
188 "inw %w[port], %w[val]\n"
189 : [val] "=a" (val)
190 : [port] "d" (port)
191 );
192
193 return val;
194}
195
196/** Double word from port
197 *
198 * Get double word from port
199 *
200 * @param port Port to read from
201 * @return Value read
202 *
203 */
204NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
205{
206 uint32_t val;
207
208 asm volatile (
209 "inl %w[port], %[val]\n"
210 : [val] "=a" (val)
211 : [port] "d" (port)
212 );
213
214 return val;
215}
216
217/** Enable interrupts.
218 *
219 * Enable interrupts and return previous
220 * value of EFLAGS.
221 *
222 * @return Old interrupt priority level.
223 *
224 */
225NO_TRACE static inline ipl_t interrupts_enable(void)
226{
227 ipl_t v;
228
229 asm volatile (
230 "pushf\n"
231 "popl %[v]\n"
232 "sti\n"
233 : [v] "=r" (v)
234 );
235
236 return v;
237}
238
239/** Disable interrupts.
240 *
241 * Disable interrupts and return previous
242 * value of EFLAGS.
243 *
244 * @return Old interrupt priority level.
245 *
246 */
247NO_TRACE static inline ipl_t interrupts_disable(void)
248{
249 ipl_t v;
250
251 asm volatile (
252 "pushf\n"
253 "popl %[v]\n"
254 "cli\n"
255 : [v] "=r" (v)
256 );
257
258 return v;
259}
260
261/** Restore interrupt priority level.
262 *
263 * Restore EFLAGS.
264 *
265 * @param ipl Saved interrupt priority level.
266 *
267 */
268NO_TRACE static inline void interrupts_restore(ipl_t ipl)
269{
270 asm volatile (
271 "pushl %[ipl]\n"
272 "popf\n"
273 :: [ipl] "r" (ipl)
274 );
275}
276
277/** Return interrupt priority level.
278 *
279 * @return EFLAFS.
280 *
281 */
282NO_TRACE static inline ipl_t interrupts_read(void)
283{
284 ipl_t v;
285
286 asm volatile (
287 "pushf\n"
288 "popl %[v]\n"
289 : [v] "=r" (v)
290 );
291
292 return v;
293}
294
295/** Check interrupts state.
296 *
297 * @return True if interrupts are disabled.
298 *
299 */
300NO_TRACE static inline bool interrupts_disabled(void)
301{
302 ipl_t v;
303
304 asm volatile (
305 "pushf\n"
306 "popl %[v]\n"
307 : [v] "=r" (v)
308 );
309
310 return ((v & EFLAGS_IF) == 0);
311}
312
313/** Write to MSR */
314NO_TRACE static inline void write_msr(uint32_t msr, uint64_t value)
315{
316 asm volatile (
317 "wrmsr"
318 :: "c" (msr),
319 "a" ((uint32_t) (value)),
320 "d" ((uint32_t) (value >> 32))
321 );
322}
323
324NO_TRACE static inline uint64_t read_msr(uint32_t msr)
325{
326 uint32_t ax, dx;
327
328 asm volatile (
329 "rdmsr"
330 : "=a" (ax),
331 "=d" (dx)
332 : "c" (msr)
333 );
334
335 return ((uint64_t) dx << 32) | ax;
336}
337
338
339/** Return base address of current stack
340 *
341 * Return the base address of the current stack.
342 * The stack is assumed to be STACK_SIZE bytes long.
343 * The stack must start on page boundary.
344 *
345 */
346NO_TRACE static inline uintptr_t get_stack_base(void)
347{
348 uintptr_t v;
349
350 asm volatile (
351 "andl %%esp, %[v]\n"
352 : [v] "=r" (v)
353 : "0" (~(STACK_SIZE - 1))
354 );
355
356 return v;
357}
358
359/** Invalidate TLB Entry.
360 *
361 * @param addr Address on a page whose TLB entry is to be invalidated.
362 *
363 */
364NO_TRACE static inline void invlpg(uintptr_t addr)
365{
366 asm volatile (
367 "invlpg %[addr]\n"
368 :: [addr] "m" (*(sysarg_t *) addr)
369 );
370}
371
372/** Load GDTR register from memory.
373 *
374 * @param gdtr_reg Address of memory from where to load GDTR.
375 *
376 */
377NO_TRACE static inline void gdtr_load(ptr_16_32_t *gdtr_reg)
378{
379 asm volatile (
380 "lgdtl %[gdtr_reg]\n"
381 :: [gdtr_reg] "m" (*gdtr_reg)
382 );
383}
384
385/** Store GDTR register to memory.
386 *
387 * @param gdtr_reg Address of memory to where to load GDTR.
388 *
389 */
390NO_TRACE static inline void gdtr_store(ptr_16_32_t *gdtr_reg)
391{
392 asm volatile (
393 "sgdtl %[gdtr_reg]\n"
394 : [gdtr_reg] "=m" (*gdtr_reg)
395 );
396}
397
398/** Load IDTR register from memory.
399 *
400 * @param idtr_reg Address of memory from where to load IDTR.
401 *
402 */
403NO_TRACE static inline void idtr_load(ptr_16_32_t *idtr_reg)
404{
405 asm volatile (
406 "lidtl %[idtr_reg]\n"
407 :: [idtr_reg] "m" (*idtr_reg)
408 );
409}
410
411/** Load TR from descriptor table.
412 *
413 * @param sel Selector specifying descriptor of TSS segment.
414 *
415 */
416NO_TRACE static inline void tr_load(uint16_t sel)
417{
418 asm volatile (
419 "ltr %[sel]"
420 :: [sel] "r" (sel)
421 );
422}
423
424extern void paging_on(void);
425extern void enable_l_apic_in_msr(void);
426
427extern void asm_delay_loop(uint32_t);
428extern void asm_fake_loop(uint32_t);
429
430extern uintptr_t int_syscall;
431
432extern uintptr_t int_0;
433extern uintptr_t int_1;
434extern uintptr_t int_2;
435extern uintptr_t int_3;
436extern uintptr_t int_4;
437extern uintptr_t int_5;
438extern uintptr_t int_6;
439extern uintptr_t int_7;
440extern uintptr_t int_8;
441extern uintptr_t int_9;
442extern uintptr_t int_10;
443extern uintptr_t int_11;
444extern uintptr_t int_12;
445extern uintptr_t int_13;
446extern uintptr_t int_14;
447extern uintptr_t int_15;
448extern uintptr_t int_16;
449extern uintptr_t int_17;
450extern uintptr_t int_18;
451extern uintptr_t int_19;
452extern uintptr_t int_20;
453extern uintptr_t int_21;
454extern uintptr_t int_22;
455extern uintptr_t int_23;
456extern uintptr_t int_24;
457extern uintptr_t int_25;
458extern uintptr_t int_26;
459extern uintptr_t int_27;
460extern uintptr_t int_28;
461extern uintptr_t int_29;
462extern uintptr_t int_30;
463extern uintptr_t int_31;
464extern uintptr_t int_32;
465extern uintptr_t int_33;
466extern uintptr_t int_34;
467extern uintptr_t int_35;
468extern uintptr_t int_36;
469extern uintptr_t int_37;
470extern uintptr_t int_38;
471extern uintptr_t int_39;
472extern uintptr_t int_40;
473extern uintptr_t int_41;
474extern uintptr_t int_42;
475extern uintptr_t int_43;
476extern uintptr_t int_44;
477extern uintptr_t int_45;
478extern uintptr_t int_46;
479extern uintptr_t int_47;
480extern uintptr_t int_48;
481extern uintptr_t int_49;
482extern uintptr_t int_50;
483extern uintptr_t int_51;
484extern uintptr_t int_52;
485extern uintptr_t int_53;
486extern uintptr_t int_54;
487extern uintptr_t int_55;
488extern uintptr_t int_56;
489extern uintptr_t int_57;
490extern uintptr_t int_58;
491extern uintptr_t int_59;
492extern uintptr_t int_60;
493extern uintptr_t int_61;
494extern uintptr_t int_62;
495extern uintptr_t int_63;
496
497#endif
498
499/** @}
500 */
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