Changeset 8c5e6c7 in mainline for arch/mips32/include/mm/tlb.h

Timestamp:

2005-10-07T23:19:56Z (20 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

cad5ce8

Parents:

92e5431

Message:

mips32 memory management work.
TLB exceptions seem to be working on at least simics.
msim handles TLB Refill and TLB Invalid exceptions well,
but seems to skip writes to the mapped addressies in mm
mapping test #1 (the data is not written and exception
is not triggered).

File:

• arch/mips32/include/mm/tlb.h (modified) (1 diff)

arch/mips32/include/mm/tlb.h

@@ -49 +49 @@
                 unsigned c : 3;         /* cache coherency attribute */
                 unsigned pfn : 24;      /* frame number */
-                unsigned zero: 2;       /* zero */
+                unsigned : 2;           /* zero */
         } __attribute__ ((packed));
         __u32 value;