Changeset 7f1c620 in mainline for arch/sparc64/include


Ignore:
Timestamp:
2006-07-04T17:17:56Z (19 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
0ffa3ef5
Parents:
991779c5
Message:

Replace old u?? types with respective C99 variants (e.g. uint32_t, int64_t, uintptr_t etc.).

Location:
arch/sparc64/include
Files:
18 edited

Legend:

Unmodified
Added
Removed

  • arch/sparc64/include/asm.h

    r991779c5 r7f1c620  
    4545 * @return Value of PSTATE register.
    4646 */
    47 static inline __u64 pstate_read(void)
    48 {
    49         __u64 v;
     47static inline uint64_t pstate_read(void)
     48{
     49        uint64_t v;
    5050       
    5151        __asm__ volatile ("rdpr %%pstate, %0\n" : "=r" (v));
    … …  
    5858 * @param v New value of PSTATE register.
    5959 */
    60 static inline void pstate_write(__u64 v)
     60static inline void pstate_write(uint64_t v)
    6161{
    6262        __asm__ volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
    … …  
    6767 * @return Value of TICK_comapre register.
    6868 */
    69 static inline __u64 tick_compare_read(void)
    70 {
    71         __u64 v;
     69static inline uint64_t tick_compare_read(void)
     70{
     71        uint64_t v;
    7272       
    7373        __asm__ volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));
    … …  
    8080 * @param v New value of TICK_comapre register.
    8181 */
    82 static inline void tick_compare_write(__u64 v)
     82static inline void tick_compare_write(uint64_t v)
    8383{
    8484        __asm__ volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));
    … …  
    8989 * @return Value of TICK register.
    9090 */
    91 static inline __u64 tick_read(void)
    92 {
    93         __u64 v;
     91static inline uint64_t tick_read(void)
     92{
     93        uint64_t v;
    9494       
    9595        __asm__ volatile ("rdpr %%tick, %0\n" : "=r" (v));
    … …  
    102102 * @param v New value of TICK register.
    103103 */
    104 static inline void tick_write(__u64 v)
     104static inline void tick_write(uint64_t v)
    105105{
    106106        __asm__ volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));
    … …  
    111111 * @return Value of SOFTINT register.
    112112 */
    113 static inline __u64 softint_read(void)
    114 {
    115         __u64 v;
     113static inline uint64_t softint_read(void)
     114{
     115        uint64_t v;
    116116
    117117        __asm__ volatile ("rd %%softint, %0\n" : "=r" (v));
    … …  
    124124 * @param v New value of SOFTINT register.
    125125 */
    126 static inline void softint_write(__u64 v)
     126static inline void softint_write(uint64_t v)
    127127{
    128128        __asm__ volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));
    … …  
    135135 * @param v New value of CLEAR_SOFTINT register.
    136136 */
    137 static inline void clear_softint_write(__u64 v)
     137static inline void clear_softint_write(uint64_t v)
    138138{
    139139        __asm__ volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));
    … …  
    149149static inline ipl_t interrupts_enable(void) {
    150150        pstate_reg_t pstate;
    151         __u64 value;
     151        uint64_t value;
    152152       
    153153        value = pstate_read();
    … …  
    168168static inline ipl_t interrupts_disable(void) {
    169169        pstate_reg_t pstate;
    170         __u64 value;
     170        uint64_t value;
    171171       
    172172        value = pstate_read();
    … …  
    208208 * The stack must start on page boundary.
    209209 */
    210 static inline __address get_stack_base(void)
    211 {
    212         __address v;
     210static inline uintptr_t get_stack_base(void)
     211{
     212        uintptr_t v;
    213213       
    214214        __asm__ volatile ("and %%sp, %1, %0\n" : "=r" (v) : "r" (~(STACK_SIZE-1)));
    … …  
    221221 * @return Value of VER register.
    222222 */
    223 static inline __u64 ver_read(void)
    224 {
    225         __u64 v;
     223static inline uint64_t ver_read(void)
     224{
     225        uint64_t v;
    226226       
    227227        __asm__ volatile ("rdpr %%ver, %0\n" : "=r" (v));
    … …  
    234234 * @return Current value in TBA.
    235235 */
    236 static inline __u64 tba_read(void)
    237 {
    238         __u64 v;
     236static inline uint64_t tba_read(void)
     237{
     238        uint64_t v;
    239239       
    240240        __asm__ volatile ("rdpr %%tba, %0\n" : "=r" (v));
    … …  
    247247 * @return Current value in TPC.
    248248 */
    249 static inline __u64 tpc_read(void)
    250 {
    251         __u64 v;
     249static inline uint64_t tpc_read(void)
     250{
     251        uint64_t v;
    252252       
    253253        __asm__ volatile ("rdpr %%tpc, %0\n" : "=r" (v));
    … …  
    260260 * @return Current value in TL.
    261261 */
    262 static inline __u64 tl_read(void)
    263 {
    264         __u64 v;
     262static inline uint64_t tl_read(void)
     263{
     264        uint64_t v;
    265265       
    266266        __asm__ volatile ("rdpr %%tl, %0\n" : "=r" (v));
    … …  
    273273 * @param v New value of TBA.
    274274 */
    275 static inline void tba_write(__u64 v)
     275static inline void tba_write(uint64_t v)
    276276{
    277277        __asm__ volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
    278278}
    279279
    280 /** Load __u64 from alternate space.
     280/** Load uint64_t from alternate space.
    281281 *
    282282 * @param asi ASI determining the alternate space.
    … …  
    285285 * @return Value read from the virtual address in the specified address space.
    286286 */
    287 static inline __u64 asi_u64_read(asi_t asi, __address va)
    288 {
    289         __u64 v;
     287static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)
     288{
     289        uint64_t v;
    290290       
    291291        __asm__ volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" (asi));
    … …  
    294294}
    295295
    296 /** Store __u64 to alternate space.
     296/** Store uint64_t to alternate space.
    297297 *
    298298 * @param asi ASI determining the alternate space.
    … …  
    300300 * @param v Value to be written.
    301301 */
    302 static inline void asi_u64_write(asi_t asi, __address va, __u64 v)
     302static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)
    303303{
    304304        __asm__ volatile ("stxa %0, [%1] %2\n" : :  "r" (v), "r" (va), "i" (asi) : "memory");
    … …  
    309309void cpu_halt(void);
    310310void cpu_sleep(void);
    311 void asm_delay_loop(__u32 t);
     311void asm_delay_loop(uint32_t t);
    312312
    313313#endif

  • arch/sparc64/include/atomic.h

    r991779c5 r7f1c620  
    5050static inline long atomic_add(atomic_t *val, int i)
    5151{
    52         __u64 a, b;
    53         volatile __u64 x = (__u64) &val->count;
     52        uint64_t a, b;
     53        volatile uint64_t x = (uint64_t) &val->count;
    5454
    5555        __asm__ volatile (
    … …  
    6161                "bne 0b\n"              /* The operation failed and must be attempted again if a != b. */
    6262                "nop\n"
    63                 : "=m" (*((__u64 *)x)), "=r" (a), "=r" (b)
     63                : "=m" (*((uint64_t *)x)), "=r" (a), "=r" (b)
    6464                : "r" (i)
    6565        );

  • arch/sparc64/include/byteorder.h

    r991779c5 r7f1c620  
    3939#include <byteorder.h>
    4040
    41 static inline __u64 __u64_le2host(__u64 n)
     41static inline uint64_t uint64_t_le2host(uint64_t n)
    4242{
    43         return __u64_byteorder_swap(n);
     43        return uint64_t_byteorder_swap(n);
    4444}
    4545
    46 static inline __native __native_le2host(__native n)
     46static inline unative_t unative_t_le2host(unative_t n)
    4747{
    48         return __u64_byteorder_swap(n);
     48        return uint64_t_byteorder_swap(n);
    4949}
    5050

  • arch/sparc64/include/context.h

    r991779c5 r7f1c620  
    5555
    5656#define context_set(c, _pc, stack, size)                                                                \
    57         (c)->pc = ((__address) _pc) - 8;                                                                \
    58         (c)->sp = ((__address) stack) + ALIGN_UP((size), STACK_ALIGNMENT) - (STACK_BIAS + SP_DELTA);    \
     57        (c)->pc = ((uintptr_t) _pc) - 8;                                                                \
     58        (c)->sp = ((uintptr_t) stack) + ALIGN_UP((size), STACK_ALIGNMENT) - (STACK_BIAS + SP_DELTA);    \
    5959        (c)->fp = -STACK_BIAS;                                                                          \
    6060        (c)->cleanwin = 0
    … …  
    6666 */
    6767struct context {
    68         __address sp;           /* %o6 */
    69         __address pc;           /* %o7 */
    70         __u64 i0;
    71         __u64 i1;
    72         __u64 i2;
    73         __u64 i3;
    74         __u64 i4;
    75         __u64 i5;
    76         __address fp;           /* %i6 */
    77         __address i7;
    78         __u64 l0;
    79         __u64 l1;
    80         __u64 l2;
    81         __u64 l3;
    82         __u64 l4;
    83         __u64 l5;
    84         __u64 l6;
    85         __u64 l7;
     68        uintptr_t sp;           /* %o6 */
     69        uintptr_t pc;           /* %o7 */
     70        uint64_t i0;
     71        uint64_t i1;
     72        uint64_t i2;
     73        uint64_t i3;
     74        uint64_t i4;
     75        uint64_t i5;
     76        uintptr_t fp;           /* %i6 */
     77        uintptr_t i7;
     78        uint64_t l0;
     79        uint64_t l1;
     80        uint64_t l2;
     81        uint64_t l3;
     82        uint64_t l4;
     83        uint64_t l5;
     84        uint64_t l6;
     85        uint64_t l7;
    8686        ipl_t ipl;
    87         __u64 cleanwin;
     87        uint64_t cleanwin;
    8888};
    8989

  • arch/sparc64/include/drivers/i8042.h

    r991779c5 r7f1c620  
    4646#define LAST_REG        DATA_REG
    4747
    48 extern volatile __u8 *kbd_virt_address;
     48extern volatile uint8_t *kbd_virt_address;
    4949
    50 static inline void i8042_data_write(__u8 data)
     50static inline void i8042_data_write(uint8_t data)
    5151{
    5252        kbd_virt_address[DATA_REG] = data;
    5353}
    5454
    55 static inline __u8 i8042_data_read(void)
     55static inline uint8_t i8042_data_read(void)
    5656{
    5757        return kbd_virt_address[DATA_REG];
    5858}
    5959
    60 static inline __u8 i8042_status_read(void)
     60static inline uint8_t i8042_status_read(void)
    6161{
    6262        return kbd_virt_address[STATUS_REG];
    6363}
    6464
    65 static inline void i8042_command_write(__u8 command)
     65static inline void i8042_command_write(uint8_t command)
    6666{
    6767        kbd_virt_address[COMMAND_REG] = command;

  • arch/sparc64/include/faddr.h

    r991779c5 r7f1c620  
    3838#include <arch/types.h>
    3939
    40 #define FADDR(fptr)             ((__address) (fptr))
     40#define FADDR(fptr)             ((uintptr_t) (fptr))
    4141
    4242#endif

  • arch/sparc64/include/interrupt.h

    r991779c5 r7f1c620  
    5555};
    5656
    57 static inline void istate_set_retaddr(istate_t *istate, __address retaddr)
     57static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr)
    5858{
    5959        /* TODO */
    … …  
    6464        return 0;
    6565}
    66 static inline __native istate_get_pc(istate_t *istate)
     66static inline unative_t istate_get_pc(istate_t *istate)
    6767{
    6868        /* TODO */

  • arch/sparc64/include/memstr.h

    r991779c5 r7f1c620  
    3838#define memcpy(dst, src, cnt)  __builtin_memcpy((dst), (src), (cnt))
    3939
    40 extern void memsetw(__address dst, size_t cnt, __u16 x);
    41 extern void memsetb(__address dst, size_t cnt, __u8 x);
     40extern void memsetw(uintptr_t dst, size_t cnt, uint16_t x);
     41extern void memsetb(uintptr_t dst, size_t cnt, uint8_t x);
    4242
    43 extern int memcmp(__address src, __address dst, int cnt);
     43extern int memcmp(uintptr_t src, uintptr_t dst, int cnt);
    4444
    4545#endif

  • arch/sparc64/include/mm/asid.h

    r991779c5 r7f1c620  
    4141 * On SPARC, Context means the same thing as ASID trough out the kernel.
    4242 */
    43 typedef __u16 asid_t;
     43typedef uint16_t asid_t;
    4444
    4545#define ASID_MAX_ARCH           8191    /* 2^13 - 1 */

  • arch/sparc64/include/mm/frame.h

    r991779c5 r7f1c620  
    4545
    4646union frame_address {
    47         __address address;
     47        uintptr_t address;
    4848        struct {
    4949                unsigned : 23;
    50                 __u64 pfn : 28;         /**< Physical Frame Number. */
     50                uint64_t pfn : 28;         /**< Physical Frame Number. */
    5151                unsigned offset : 13;   /**< Offset. */
    5252        } __attribute__ ((packed));

  • arch/sparc64/include/mm/mmu.h

    r991779c5 r7f1c620  
    8383/** LSU Control Register. */
    8484union lsu_cr_reg {
    85         __u64 value;
     85        uint64_t value;
    8686        struct {
    8787                unsigned : 23;

  • arch/sparc64/include/mm/page.h

    r991779c5 r7f1c620  
    4747#include <genarch/mm/page_ht.h>
    4848
    49 #define KA2PA(x)        ((__address) (x))
    50 #define PA2KA(x)        ((__address) (x))
     49#define KA2PA(x)        ((uintptr_t) (x))
     50#define PA2KA(x)        ((uintptr_t) (x))
    5151
    5252union page_address {
    53         __address address;
     53        uintptr_t address;
    5454        struct {
    55                 __u64 vpn : 51;         /**< Virtual Page Number. */
     55                uint64_t vpn : 51;              /**< Virtual Page Number. */
    5656                unsigned offset : 13;   /**< Offset. */
    5757        } __attribute__ ((packed));

  • arch/sparc64/include/mm/tlb.h

    r991779c5 r7f1c620  
    5757
    5858union tlb_context_reg {
    59         __u64 v;
     59        uint64_t v;
    6060        struct {
    6161                unsigned long : 51;
    … …  
    7070/** I-/D-TLB Data Access Address in Alternate Space. */
    7171union tlb_data_access_addr {
    72         __u64 value;
     72        uint64_t value;
    7373        struct {
    74                 __u64 : 55;
     74                uint64_t : 55;
    7575                unsigned tlb_entry : 6;
    7676                unsigned : 3;
    … …  
    8282/** I-/D-TLB Tag Read Register. */
    8383union tlb_tag_read_reg {
    84         __u64 value;
     84        uint64_t value;
    8585        struct {
    86                 __u64 vpn : 51;         /**< Virtual Address bits 63:13. */
     86                uint64_t vpn : 51;              /**< Virtual Address bits 63:13. */
    8787                unsigned context : 13;  /**< Context identifier. */
    8888        } __attribute__ ((packed));
    … …  
    102102/** TLB Demap Operation Address. */
    103103union tlb_demap_addr {
    104         __u64 value;
     104        uint64_t value;
    105105        struct {
    106                 __u64 vpn: 51;          /**< Virtual Address bits 63:13. */
     106                uint64_t vpn: 51;               /**< Virtual Address bits 63:13. */
    107107                unsigned : 6;           /**< Ignored. */
    108108                unsigned type : 1;      /**< The type of demap operation. */
    … …  
    115115/** TLB Synchronous Fault Status Register. */
    116116union tlb_sfsr_reg {
    117         __u64 value;
     117        uint64_t value;
    118118        struct {
    119119                unsigned long : 39;     /**< Implementation dependent. */
    … …  
    137137 * @return Current value of Primary Context Register.
    138138 */
    139 static inline __u64 mmu_primary_context_read(void)
     139static inline uint64_t mmu_primary_context_read(void)
    140140{
    141141        return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);
    … …  
    146146 * @param v New value of Primary Context Register.
    147147 */
    148 static inline void mmu_primary_context_write(__u64 v)
     148static inline void mmu_primary_context_write(uint64_t v)
    149149{
    150150        asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
    … …  
    156156 * @return Current value of Secondary Context Register.
    157157 */
    158 static inline __u64 mmu_secondary_context_read(void)
     158static inline uint64_t mmu_secondary_context_read(void)
    159159{
    160160        return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);
    … …  
    165165 * @param v New value of Primary Context Register.
    166166 */
    167 static inline void mmu_secondary_context_write(__u64 v)
     167static inline void mmu_secondary_context_write(uint64_t v)
    168168{
    169169        asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
    … …  
    177177 * @return Current value of specified IMMU TLB Data Access Register.
    178178 */
    179 static inline __u64 itlb_data_access_read(index_t entry)
     179static inline uint64_t itlb_data_access_read(index_t entry)
    180180{
    181181        tlb_data_access_addr_t reg;
    … …  
    191191 * @param value Value to be written.
    192192 */
    193 static inline void itlb_data_access_write(index_t entry, __u64 value)
     193static inline void itlb_data_access_write(index_t entry, uint64_t value)
    194194{
    195195        tlb_data_access_addr_t reg;
    … …  
    207207 * @return Current value of specified DMMU TLB Data Access Register.
    208208 */
    209 static inline __u64 dtlb_data_access_read(index_t entry)
     209static inline uint64_t dtlb_data_access_read(index_t entry)
    210210{
    211211        tlb_data_access_addr_t reg;
    … …  
    221221 * @param value Value to be written.
    222222 */
    223 static inline void dtlb_data_access_write(index_t entry, __u64 value)
     223static inline void dtlb_data_access_write(index_t entry, uint64_t value)
    224224{
    225225        tlb_data_access_addr_t reg;
    … …  
    237237 * @return Current value of specified IMMU TLB Tag Read Register.
    238238 */
    239 static inline __u64 itlb_tag_read_read(index_t entry)
     239static inline uint64_t itlb_tag_read_read(index_t entry)
    240240{
    241241        tlb_tag_read_addr_t tag;
    … …  
    252252 * @return Current value of specified DMMU TLB Tag Read Register.
    253253 */
    254 static inline __u64 dtlb_tag_read_read(index_t entry)
     254static inline uint64_t dtlb_tag_read_read(index_t entry)
    255255{
    256256        tlb_tag_read_addr_t tag;
    … …  
    265265 * @param v Value to be written.
    266266 */
    267 static inline void itlb_tag_access_write(__u64 v)
     267static inline void itlb_tag_access_write(uint64_t v)
    268268{
    269269        asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
    … …  
    275275 * @return Current value of IMMU TLB Tag Access Register.
    276276 */
    277 static inline __u64 itlb_tag_access_read(void)
     277static inline uint64_t itlb_tag_access_read(void)
    278278{
    279279        return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS);
    … …  
    284284 * @param v Value to be written.
    285285 */
    286 static inline void dtlb_tag_access_write(__u64 v)
     286static inline void dtlb_tag_access_write(uint64_t v)
    287287{
    288288        asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);
    … …  
    294294 * @return Current value of DMMU TLB Tag Access Register.
    295295 */
    296 static inline __u64 dtlb_tag_access_read(void)
     296static inline uint64_t dtlb_tag_access_read(void)
    297297{
    298298        return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS);
    … …  
    304304 * @param v Value to be written.
    305305 */
    306 static inline void itlb_data_in_write(__u64 v)
     306static inline void itlb_data_in_write(uint64_t v)
    307307{
    308308        asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
    … …  
    314314 * @param v Value to be written.
    315315 */
    316 static inline void dtlb_data_in_write(__u64 v)
     316static inline void dtlb_data_in_write(uint64_t v)
    317317{
    318318        asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);
    … …  
    324324 * @return Current content of I-SFSR register.
    325325 */
    326 static inline __u64 itlb_sfsr_read(void)
     326static inline uint64_t itlb_sfsr_read(void)
    327327{
    328328        return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR);
    … …  
    333333 * @param v New value of I-SFSR register.
    334334 */
    335 static inline void itlb_sfsr_write(__u64 v)
     335static inline void itlb_sfsr_write(uint64_t v)
    336336{
    337337        asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
    … …  
    343343 * @return Current content of D-SFSR register.
    344344 */
    345 static inline __u64 dtlb_sfsr_read(void)
     345static inline uint64_t dtlb_sfsr_read(void)
    346346{
    347347        return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR);
    … …  
    352352 * @param v New value of D-SFSR register.
    353353 */
    354 static inline void dtlb_sfsr_write(__u64 v)
     354static inline void dtlb_sfsr_write(uint64_t v)
    355355{
    356356        asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v);
    … …  
    362362 * @return Current content of D-SFAR register.
    363363 */
    364 static inline __u64 dtlb_sfar_read(void)
     364static inline uint64_t dtlb_sfar_read(void)
    365365{
    366366        return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR);
    … …  
    373373 * @param page Address which is on the page to be demapped.
    374374 */
    375 static inline void itlb_demap(int type, int context_encoding, __address page)
     375static inline void itlb_demap(int type, int context_encoding, uintptr_t page)
    376376{
    377377        tlb_demap_addr_t da;
    … …  
    395395 * @param page Address which is on the page to be demapped.
    396396 */
    397 static inline void dtlb_demap(int type, int context_encoding, __address page)
     397static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)
    398398{
    399399        tlb_demap_addr_t da;
    … …  
    415415extern void fast_data_access_protection(void);
    416416
    417 extern void dtlb_insert_mapping(__address page, __address frame, int pagesize, bool locked, bool cacheable);
     417extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable);
    418418
    419419#endif

  • arch/sparc64/include/mm/tte.h

    r991779c5 r7f1c620  
    4040/** Translation Table Entry - Tag. */
    4141union tte_tag {
    42         __u64 value;
     42        uint64_t value;
    4343        struct {
    4444                unsigned g : 1;         /**< Global. */
    … …  
    4646                unsigned context : 13;  /**< Context identifier. */
    4747                unsigned : 6;           /**< Reserved. */
    48                 __u64 va_tag : 42;      /**< Virtual Address Tag, bits 63:22. */
     48                uint64_t va_tag : 42;   /**< Virtual Address Tag, bits 63:22. */
    4949        } __attribute__ ((packed));
    5050};
    … …  
    5454/** Translation Table Entry - Data. */
    5555union tte_data {
    56         __u64 value;
     56        uint64_t value;
    5757        struct {
    5858                unsigned v : 1;         /**< Valid. */

  • arch/sparc64/include/register.h

    r991779c5 r7f1c620  
    4040/** Version Register. */
    4141union ver_reg {
    42         __u64 value;
     42        uint64_t value;
    4343        struct {
    44                 __u16 manuf;    /**< Manufacturer code. */
    45                 __u16 impl;     /**< Implementation code. */
    46                 __u8 mask;      /**< Mask set revision. */
     44                uint16_t manuf; /**< Manufacturer code. */
     45                uint16_t impl;  /**< Implementation code. */
     46                uint8_t mask;   /**< Mask set revision. */
    4747                unsigned : 8;
    48                 __u8 maxtl;
     48                uint8_t maxtl;
    4949                unsigned : 3;
    5050                unsigned maxwin : 5;
    … …  
    5555/** Processor State Register. */
    5656union pstate_reg {
    57         __u64 value;
     57        uint64_t value;
    5858        struct {
    59                 __u64 : 52;
     59                uint64_t : 52;
    6060                unsigned ig : 1;        /**< Interrupt Globals. */
    6161                unsigned mg : 1;        /**< MMU Globals. */
    … …  
    7575/** TICK Register. */
    7676union tick_reg {
    77         __u64 value;
     77        uint64_t value;
    7878        struct {
    7979                unsigned npt : 1;       /**< Non-privileged Trap enable. */
    80                 __u64 counter : 63;     /**< Elapsed CPU clck cycle counter. */
     80                uint64_t counter : 63;  /**< Elapsed CPU clck cycle counter. */
    8181        } __attribute__ ((packed));
    8282};
    … …  
    8585/** TICK_compare Register. */
    8686union tick_compare_reg {
    87         __u64 value;
     87        uint64_t value;
    8888        struct {
    8989                unsigned int_dis : 1;   /**< TICK_INT interrupt disabled flag. */
    90                 __u64 tick_cmpr : 63;   /**< Compare value for TICK interrupts. */
     90                uint64_t tick_cmpr : 63;        /**< Compare value for TICK interrupts. */
    9191        } __attribute__ ((packed));
    9292};
    … …  
    9595/** SOFTINT Register. */
    9696union softint_reg {
    97         __u64 value;
     97        uint64_t value;
    9898        struct {
    99                 __u64 : 47;
     99                uint64_t : 47;
    100100                unsigned stick_int : 1;
    101101                unsigned int_level : 15;

  • arch/sparc64/include/trap/trap.h

    r991779c5 r7f1c620  
    4343{
    4444        /* Point TBA to kernel copy of OFW's trap table. */
    45         tba_write((__u64) trap_table);
     45        tba_write((uint64_t) trap_table);
    4646}
    4747

  • arch/sparc64/include/trap/trap_table.h

    r991779c5 r7f1c620  
    4848#ifndef __ASM__
    4949struct trap_table_entry {
    50         __u8 octets[TRAP_TABLE_ENTRY_SIZE];
     50        uint8_t octets[TRAP_TABLE_ENTRY_SIZE];
    5151} __attribute__ ((packed));
    5252

  • arch/sparc64/include/types.h

    r991779c5 r7f1c620  
    3838#define NULL    0
    3939
    40 typedef signed char __s8;
    41 typedef signed short __s16;
    42 typedef signed int __s32;
    43 typedef signed long __s64;
     40typedef signed char int8_t;
     41typedef signed short int16_t;
     42typedef signed int int32_t;
     43typedef signed long int64_t;
    4444
    45 typedef unsigned char __u8;
    46 typedef unsigned short __u16;
    47 typedef unsigned int __u32;
    48 typedef unsigned long __u64;
     45typedef unsigned char uint8_t;
     46typedef unsigned short uint16_t;
     47typedef unsigned int uint32_t;
     48typedef unsigned long uint64_t;
    4949
    50 typedef __u64 __address;
    51 typedef __u64 pfn_t;
     50typedef uint64_t uintptr_t;
     51typedef uint64_t pfn_t;
    5252
    53 typedef __u64 ipl_t;
     53typedef uint64_t ipl_t;
    5454
    55 typedef __u64 __native;
    56 typedef __s64 __snative;
     55typedef uint64_t unative_t;
     56typedef int64_t native_t;
    5757
    5858typedef struct pte pte_t;
    5959
    60 typedef __u8 asi_t;
     60typedef uint8_t asi_t;
    6161
    6262#endif
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