source: mainline/arch/sparc64/include/mm/mmu.h@ 7f1c620

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 7f1c620 was 7f1c620, checked in by Jakub Jermar <jakub@…>, 19 years ago

Replace old u?? types with respective C99 variants (e.g. uint32_t, int64_t, uintptr_t etc.).
  • Property mode set to 100644
File size: 4.4 KB
Line 
1/*
2 * Copyright (C) 2005 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 /** @addtogroup sparc64mm
30 * @{
31 */
32/** @file
33 */
34
35#ifndef __sparc64_MMU_H__
36#define __sparc64_MMU_H__
37
38#include <arch/asm.h>
39#include <arch/barrier.h>
40#include <arch/types.h>
41#include <typedefs.h>
42
43/** LSU Control Register ASI. */
44#define ASI_LSU_CONTROL_REG 0x45 /**< Load/Store Unit Control Register. */
45
46/** I-MMU ASIs. */
47#define ASI_IMMU 0x50
48#define ASI_IMMU_TSB_8KB_PTR_REG 0x51
49#define ASI_IMMU_TSB_64KB_PTR_REG 0x52
50#define ASI_ITLB_DATA_IN_REG 0x54
51#define ASI_ITLB_DATA_ACCESS_REG 0x55
52#define ASI_ITLB_TAG_READ_REG 0x56
53#define ASI_IMMU_DEMAP 0x57
54
55/** Virtual Addresses within ASI_IMMU. */
56#define VA_IMMU_TAG_TARGET 0x0 /**< IMMU tag target register. */
57#define VA_IMMU_SFSR 0x18 /**< IMMU sync fault status register. */
58#define VA_IMMU_TSB_BASE 0x28 /**< IMMU TSB base register. */
59#define VA_IMMU_TAG_ACCESS 0x30 /**< IMMU TLB tag access register. */
60
61/** D-MMU ASIs. */
62#define ASI_DMMU 0x58
63#define ASI_DMMU_TSB_8KB_PTR_REG 0x59
64#define ASI_DMMU_TSB_64KB_PTR_REG 0x5a
65#define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b
66#define ASI_DTLB_DATA_IN_REG 0x5c
67#define ASI_DTLB_DATA_ACCESS_REG 0x5d
68#define ASI_DTLB_TAG_READ_REG 0x5e
69#define ASI_DMMU_DEMAP 0x5f
70
71/** Virtual Addresses within ASI_DMMU. */
72#define VA_DMMU_TAG_TARGET 0x0 /**< DMMU tag target register. */
73#define VA_PRIMARY_CONTEXT_REG 0x8 /**< DMMU primary context register. */
74#define VA_SECONDARY_CONTEXT_REG 0x10 /**< DMMU secondary context register. */
75#define VA_DMMU_SFSR 0x18 /**< DMMU sync fault status register. */
76#define VA_DMMU_SFAR 0x20 /**< DMMU sync fault address register. */
77#define VA_DMMU_TSB_BASE 0x28 /**< DMMU TSB base register. */
78#define VA_DMMU_TAG_ACCESS 0x30 /**< DMMU TLB tag access register. */
79#define VA_DMMU_VA_WATCHPOINT_REG 0x38 /**< DMMU VA data watchpoint register. */
80#define VA_DMMU_PA_WATCHPOINT_REG 0x40 /**< DMMU PA data watchpoint register. */
81
82
83/** LSU Control Register. */
84union lsu_cr_reg {
85 uint64_t value;
86 struct {
87 unsigned : 23;
88 unsigned pm : 8;
89 unsigned vm : 8;
90 unsigned pr : 1;
91 unsigned pw : 1;
92 unsigned vr : 1;
93 unsigned vw : 1;
94 unsigned : 1;
95 unsigned fm : 16;
96 unsigned dm : 1; /**< D-MMU enable. */
97 unsigned im : 1; /**< I-MMU enable. */
98 unsigned dc : 1; /**< D-Cache enable. */
99 unsigned ic : 1; /**< I-Cache enable. */
100
101 } __attribute__ ((packed));
102};
103typedef union lsu_cr_reg lsu_cr_reg_t;
104
105
106#define immu_enable() immu_set(true)
107#define immu_disable() immu_set(false)
108#define dmmu_enable() dmmu_set(true)
109#define dmmu_disable() dmmu_set(false)
110
111/** Disable or Enable IMMU. */
112static inline void immu_set(bool enable)
113{
114 lsu_cr_reg_t cr;
115
116 cr.value = asi_u64_read(ASI_LSU_CONTROL_REG, 0);
117 cr.im = enable;
118 asi_u64_write(ASI_LSU_CONTROL_REG, 0, cr.value);
119 membar();
120}
121
122/** Disable or Enable DMMU. */
123static inline void dmmu_set(bool enable)
124{
125 lsu_cr_reg_t cr;
126
127 cr.value = asi_u64_read(ASI_LSU_CONTROL_REG, 0);
128 cr.dm = enable;
129 asi_u64_write(ASI_LSU_CONTROL_REG, 0, cr.value);
130 membar();
131}
132
133#endif
134
135 /** @}
136 */
137
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