Changeset 7f1c620 in mainline for arch/sparc64/include/asm.h


Ignore:
Timestamp:
2006-07-04T17:17:56Z (19 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
0ffa3ef5
Parents:
991779c5
Message:

Replace old u?? types with respective C99 variants (e.g. uint32_t, int64_t, uintptr_t etc.).

File:
1 edited

Legend:

Unmodified
Added
Removed

  • arch/sparc64/include/asm.h

    r991779c5 r7f1c620  
    4545 * @return Value of PSTATE register.
    4646 */
    47 static inline __u64 pstate_read(void)
    48 {
    49         __u64 v;
     47static inline uint64_t pstate_read(void)
     48{
     49        uint64_t v;
    5050       
    5151        __asm__ volatile ("rdpr %%pstate, %0\n" : "=r" (v));
    … …  
    5858 * @param v New value of PSTATE register.
    5959 */
    60 static inline void pstate_write(__u64 v)
     60static inline void pstate_write(uint64_t v)
    6161{
    6262        __asm__ volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
    … …  
    6767 * @return Value of TICK_comapre register.
    6868 */
    69 static inline __u64 tick_compare_read(void)
    70 {
    71         __u64 v;
     69static inline uint64_t tick_compare_read(void)
     70{
     71        uint64_t v;
    7272       
    7373        __asm__ volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));
    … …  
    8080 * @param v New value of TICK_comapre register.
    8181 */
    82 static inline void tick_compare_write(__u64 v)
     82static inline void tick_compare_write(uint64_t v)
    8383{
    8484        __asm__ volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));
    … …  
    8989 * @return Value of TICK register.
    9090 */
    91 static inline __u64 tick_read(void)
    92 {
    93         __u64 v;
     91static inline uint64_t tick_read(void)
     92{
     93        uint64_t v;
    9494       
    9595        __asm__ volatile ("rdpr %%tick, %0\n" : "=r" (v));
    … …  
    102102 * @param v New value of TICK register.
    103103 */
    104 static inline void tick_write(__u64 v)
     104static inline void tick_write(uint64_t v)
    105105{
    106106        __asm__ volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));
    … …  
    111111 * @return Value of SOFTINT register.
    112112 */
    113 static inline __u64 softint_read(void)
    114 {
    115         __u64 v;
     113static inline uint64_t softint_read(void)
     114{
     115        uint64_t v;
    116116
    117117        __asm__ volatile ("rd %%softint, %0\n" : "=r" (v));
    … …  
    124124 * @param v New value of SOFTINT register.
    125125 */
    126 static inline void softint_write(__u64 v)
     126static inline void softint_write(uint64_t v)
    127127{
    128128        __asm__ volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));
    … …  
    135135 * @param v New value of CLEAR_SOFTINT register.
    136136 */
    137 static inline void clear_softint_write(__u64 v)
     137static inline void clear_softint_write(uint64_t v)
    138138{
    139139        __asm__ volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));
    … …  
    149149static inline ipl_t interrupts_enable(void) {
    150150        pstate_reg_t pstate;
    151         __u64 value;
     151        uint64_t value;
    152152       
    153153        value = pstate_read();
    … …  
    168168static inline ipl_t interrupts_disable(void) {
    169169        pstate_reg_t pstate;
    170         __u64 value;
     170        uint64_t value;
    171171       
    172172        value = pstate_read();
    … …  
    208208 * The stack must start on page boundary.
    209209 */
    210 static inline __address get_stack_base(void)
    211 {
    212         __address v;
     210static inline uintptr_t get_stack_base(void)
     211{
     212        uintptr_t v;
    213213       
    214214        __asm__ volatile ("and %%sp, %1, %0\n" : "=r" (v) : "r" (~(STACK_SIZE-1)));
    … …  
    221221 * @return Value of VER register.
    222222 */
    223 static inline __u64 ver_read(void)
    224 {
    225         __u64 v;
     223static inline uint64_t ver_read(void)
     224{
     225        uint64_t v;
    226226       
    227227        __asm__ volatile ("rdpr %%ver, %0\n" : "=r" (v));
    … …  
    234234 * @return Current value in TBA.
    235235 */
    236 static inline __u64 tba_read(void)
    237 {
    238         __u64 v;
     236static inline uint64_t tba_read(void)
     237{
     238        uint64_t v;
    239239       
    240240        __asm__ volatile ("rdpr %%tba, %0\n" : "=r" (v));
    … …  
    247247 * @return Current value in TPC.
    248248 */
    249 static inline __u64 tpc_read(void)
    250 {
    251         __u64 v;
     249static inline uint64_t tpc_read(void)
     250{
     251        uint64_t v;
    252252       
    253253        __asm__ volatile ("rdpr %%tpc, %0\n" : "=r" (v));
    … …  
    260260 * @return Current value in TL.
    261261 */
    262 static inline __u64 tl_read(void)
    263 {
    264         __u64 v;
     262static inline uint64_t tl_read(void)
     263{
     264        uint64_t v;
    265265       
    266266        __asm__ volatile ("rdpr %%tl, %0\n" : "=r" (v));
    … …  
    273273 * @param v New value of TBA.
    274274 */
    275 static inline void tba_write(__u64 v)
     275static inline void tba_write(uint64_t v)
    276276{
    277277        __asm__ volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
    278278}
    279279
    280 /** Load __u64 from alternate space.
     280/** Load uint64_t from alternate space.
    281281 *
    282282 * @param asi ASI determining the alternate space.
    … …  
    285285 * @return Value read from the virtual address in the specified address space.
    286286 */
    287 static inline __u64 asi_u64_read(asi_t asi, __address va)
    288 {
    289         __u64 v;
     287static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)
     288{
     289        uint64_t v;
    290290       
    291291        __asm__ volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" (asi));
    … …  
    294294}
    295295
    296 /** Store __u64 to alternate space.
     296/** Store uint64_t to alternate space.
    297297 *
    298298 * @param asi ASI determining the alternate space.
    … …  
    300300 * @param v Value to be written.
    301301 */
    302 static inline void asi_u64_write(asi_t asi, __address va, __u64 v)
     302static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)
    303303{
    304304        __asm__ volatile ("stxa %0, [%1] %2\n" : :  "r" (v), "r" (va), "i" (asi) : "memory");
    … …  
    309309void cpu_halt(void);
    310310void cpu_sleep(void);
    311 void asm_delay_loop(__u32 t);
     311void asm_delay_loop(uint32_t t);
    312312
    313313#endif
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