Changeset 7e752b2 in mainline for kernel/arch
- Timestamp:
- 2010-11-26T01:33:20Z (15 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- bf61d3a
- Parents:
- 202f57b
- Location:
- kernel/arch
- Files:
-
- 26 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/amd64/src/debugger.c
r202f57b r7e752b2 230 230 return; 231 231 232 printf("*** Found ZERO on address % " PRIp "(slot %d) ***\n",233 breakpoints[slot].address, slot);232 printf("*** Found ZERO on address %p (slot %d) ***\n", 233 (void *) breakpoints[slot].address, slot); 234 234 } else { 235 printf("Data watchpoint - new data: % " PRIp"\n",235 printf("Data watchpoint - new data: %#" PRIxn "\n", 236 236 *((unative_t *) breakpoints[slot].address)); 237 237 } 238 238 } 239 239 240 printf("Reached breakpoint %d:% " PRIp " (%s)\n", slot, getip(istate),241 symtab_fmt_name_lookup(getip(istate)));240 printf("Reached breakpoint %d:%p (%s)\n", slot, 241 (void *) getip(istate), symtab_fmt_name_lookup(getip(istate))); 242 242 243 243 #ifdef CONFIG_KCONSOLE … … 363 363 364 364 #ifdef __32_BITS__ 365 printf("%-4u %7 " PRIs "%p %s\n", i,366 breakpoints[i].counter, breakpoints[i].address,365 printf("%-4u %7zu %p %s\n", i, 366 breakpoints[i].counter, (void *) breakpoints[i].address, 367 367 symbol); 368 368 #endif 369 369 370 370 #ifdef __64_BITS__ 371 printf("%-4u %7 " PRIs "%p %s\n", i,372 breakpoints[i].counter, breakpoints[i].address,371 printf("%-4u %7zu %p %s\n", i, 372 breakpoints[i].counter, (void *) breakpoints[i].address, 373 373 symbol); 374 374 #endif … … 405 405 flags = BKPOINT_WRITE; 406 406 407 printf("Adding breakpoint on address: %p\n", argv->intval); 408 409 int id = breakpoint_add((void *)argv->intval, flags, -1); 407 printf("Adding breakpoint on address: %p\n", 408 (void *) argv->intval); 409 410 int id = breakpoint_add((void *) argv->intval, flags, -1); 410 411 if (id < 0) 411 412 printf("Add breakpoint failed.\n"); -
kernel/arch/amd64/src/interrupt.c
r202f57b r7e752b2 65 65 void istate_decode(istate_t *istate) 66 66 { 67 printf("cs =%p\trip=%p\trfl=%p\terr=%p\n", 68 istate->cs, istate->rip, istate->rflags, istate->error_word); 69 67 printf("cs =%#0" PRIx64 "\trip=%p\t" 68 "rfl=%#0" PRIx64 "\terr=%#0" PRIx64 "\n", 69 istate->cs, (void *) istate->rip, 70 istate->rflags, istate->error_word); 71 70 72 if (istate_from_uspace(istate)) 71 printf("ss =%p\n", istate->ss); 72 73 printf("rax=%p\trbx=%p\trcx=%p\trdx=%p\n", 73 printf("ss =%#0" PRIx64 "\n", istate->ss); 74 75 printf("rax=%#0" PRIx64 "\trbx=%#0" PRIx64 "\t" 76 "rcx=%#0" PRIx64 "\trdx=%#0" PRIx64 "\n", 74 77 istate->rax, istate->rbx, istate->rcx, istate->rdx); 78 75 79 printf("rsi=%p\trdi=%p\trbp=%p\trsp=%p\n", 76 istate->rsi, istate->rdi, istate->rbp, 77 istate_from_uspace(istate) ? istate->rsp : (uintptr_t)&istate->rsp); 78 printf("r8 =%p\tr9 =%p\tr10=%p\tr11=%p\n", 80 (void *) istate->rsi, (void *) istate->rdi, 81 (void *) istate->rbp, 82 istate_from_uspace(istate) ? ((void *) istate->rsp) : 83 &istate->rsp); 84 85 printf("r8 =%#0" PRIx64 "\tr9 =%#0" PRIx64 "\t" 86 "r10=%#0" PRIx64 "\tr11=%#0" PRIx64 "\n", 79 87 istate->r8, istate->r9, istate->r10, istate->r11); 80 printf("r12=%p\tr13=%p\tr14=%p\tr15=%p\n", 88 89 printf("r12=%#0" PRIx64 "\tr13=%#0" PRIx64 "\t" 90 "r14=%#0" PRIx64 "\tr15=%#0" PRIx64 "\n", 81 91 istate->r12, istate->r13, istate->r14, istate->r15); 82 92 } -
kernel/arch/amd64/src/mm/page.c
r202f57b r7e752b2 89 89 90 90 if (as_page_fault(page, access, istate) == AS_PF_FAULT) { 91 fault_if_from_uspace(istate, "Page fault: % #x.",page);91 fault_if_from_uspace(istate, "Page fault: %p.", (void *) page); 92 92 panic_memtrap(istate, access, page, NULL); 93 93 } … … 97 97 { 98 98 if (last_frame + ALIGN_UP(size, PAGE_SIZE) > KA2PA(KERNEL_ADDRESS_SPACE_END_ARCH)) 99 panic("Unable to map physical memory %p (% " PRIs " bytes).", physaddr,100 size);99 panic("Unable to map physical memory %p (%zu bytes).", 100 (void *) physaddr, size); 101 101 102 102 uintptr_t virtaddr = PA2KA(last_frame); -
kernel/arch/arm32/src/exception.c
r202f57b r7e752b2 175 175 void istate_decode(istate_t *istate) 176 176 { 177 printf("r0 =%#0.8lx\tr1 =%#0.8lx\tr2 =%#0.8lx\tr3 =%#0.8lx\n", 177 printf("r0 =%#0" PRIx32 "\tr1 =%#0" PRIx32 "\t" 178 "r2 =%#0" PRIx32 "\tr3 =%#0" PRIx32 "\n", 178 179 istate->r0, istate->r1, istate->r2, istate->r3); 179 printf("r4 =%#0.8lx\tr5 =%#0.8lx\tr6 =%#0.8lx\tr7 =%#0.8lx\n", 180 printf("r4 =%#" PRIx32 "\tr5 =%#0" PRIx32 "\t" 181 "r6 =%#0" PRIx32 "\tr7 =%#0" PRIx32 "\n", 180 182 istate->r4, istate->r5, istate->r6, istate->r7); 181 printf("r8 =%#0.8lx\tr9 =%#0.8lx\tr10=%#0.8lx\tfp =%#0.8lx\n", 182 istate->r8, istate->r9, istate->r10, istate->fp); 183 printf("r12=%#0.8lx\tsp =%#0.8lx\tlr =%#0.8lx\tspsr=%#0.8lx\n", 184 istate->r12, istate->sp, istate->lr, istate->spsr); 183 printf("r8 =%#0" PRIx32 "\tr9 =%#0" PRIx32 "\t" 184 "r10=%#0" PRIx32 "\tfp =%p\n", 185 istate->r8, istate->r9, istate->r10, 186 (void *) istate->fp); 187 printf("r12=%#0" PRIx32 "\tsp =%p\tlr =%p\tspsr=%p\n", 188 istate->r12, (void *) istate->sp, 189 (void *) istate->lr, (void *) istate->spsr); 185 190 } 186 191 -
kernel/arch/arm32/src/mm/page.c
r202f57b r7e752b2 93 93 KA2PA(KERNEL_ADDRESS_SPACE_END_ARCH)) { 94 94 panic("Unable to map physical memory %p (%d bytes).", 95 physaddr, size);95 (void *) physaddr, size); 96 96 } 97 97 -
kernel/arch/arm32/src/mm/page_fault.c
r202f57b r7e752b2 141 141 if (instr.condition == 0xf) { 142 142 panic("page_fault - instruction does not access memory " 143 "(instr_code: %x, badvaddr:%x).", instr, badvaddr); 143 "(instr_code: %#0" PRIx32 ", badvaddr:%p).", 144 instr_union.pc, (void *) badvaddr); 144 145 return PF_ACCESS_EXEC; 145 146 } … … 160 161 161 162 panic("page_fault - instruction doesn't access memory " 162 "(instr_code: %x, badvaddr:%x).", instr, badvaddr); 163 "(instr_code: %#0" PRIx32 ", badvaddr:%p).", 164 instr_union.pc, (void *) badvaddr); 163 165 164 166 return PF_ACCESS_EXEC; -
kernel/arch/ia32/src/interrupt.c
r202f57b r7e752b2 65 65 void istate_decode(istate_t *istate) 66 66 { 67 printf("cs =%p\teip=%p\tefl=%p\terr=%p\n", 68 istate->cs, istate->eip, istate->eflags, istate->error_word); 69 70 printf("ds =%p\tes =%p\tfs =%p\tgs =%p\n", 67 printf("cs =%#0" PRIx32 "\teip=%p\t" 68 "efl=%#0" PRIx32 "\terr=%#0" PRIx32 "\n", 69 istate->cs, (void *) istate->eip, 70 istate->eflags, istate->error_word); 71 72 printf("ds =%#0" PRIx32 "\tes =%#0" PRIx32 "\t" 73 "fs =%#0" PRIx32 "\tgs =%#0" PRIx32 "\n", 71 74 istate->ds, istate->es, istate->fs, istate->gs); 75 72 76 if (istate_from_uspace(istate)) 73 printf("ss =%p\n", istate->ss); 74 75 printf("eax=%p\tebx=%p\tecx=%p\tedx=%p\n", 77 printf("ss =%#0" PRIx32 "\n", istate->ss); 78 79 printf("eax=%#0" PRIx32 "\tebx=%#0" PRIx32 "\t" 80 "ecx=%#0" PRIx32 "\tedx=%#0" PRIx32 "\n", 76 81 istate->eax, istate->ebx, istate->ecx, istate->edx); 82 77 83 printf("esi=%p\tedi=%p\tebp=%p\tesp=%p\n", 78 istate->esi, istate->edi, istate->ebp, 79 istate_from_uspace(istate) ? istate->esp : (uintptr_t)&istate->esp); 84 (void *) istate->esi, (void *) istate->edi, 85 (void *) istate->ebp, 86 istate_from_uspace(istate) ? ((void *) istate->esp) : 87 &istate->esp); 80 88 } 81 89 … … 139 147 ); 140 148 141 fault_if_from_uspace(istate, "SIMD FP exception(19), MXCSR=%#0 .8x.",142 (unative_t)mxcsr);143 panic_badtrap(istate, n, "SIMD FP exception , MXCSR=%#0.8x");149 fault_if_from_uspace(istate, "SIMD FP exception(19), MXCSR=%#0" PRIx32 ".", 150 mxcsr); 151 panic_badtrap(istate, n, "SIMD FP exception"); 144 152 } 145 153 -
kernel/arch/ia32/src/mm/page.c
r202f57b r7e752b2 82 82 { 83 83 if (last_frame + ALIGN_UP(size, PAGE_SIZE) > KA2PA(KERNEL_ADDRESS_SPACE_END_ARCH)) 84 panic("Unable to map physical memory %p (%d bytes).", physaddr, size); 84 panic("Unable to map physical memory %p (%zu bytes).", 85 (void *) physaddr, size); 85 86 86 87 uintptr_t virtaddr = PA2KA(last_frame); -
kernel/arch/ia32/src/smp/apic.c
r202f57b r7e752b2 477 477 { 478 478 #ifdef LAPIC_VERBOSE 479 printf("LVT on cpu% " PRIs ", LAPIC ID: %" PRIu8 "\n",479 printf("LVT on cpu%u, LAPIC ID: %" PRIu8 "\n", 480 480 CPU->id, l_apic_id()); 481 481 -
kernel/arch/ia64/src/interrupt.c
r202f57b r7e752b2 135 135 void istate_decode(istate_t *istate) 136 136 { 137 printf("ar.bsp=%p\tar.bspstore=%p\n", istate->ar_bsp, 138 istate->ar_bspstore); 139 printf("ar.rnat=%#018llx\tar.rsc=%#018llx\n", istate->ar_rnat, 140 istate->ar_rsc); 141 printf("ar.ifs=%#018llx\tar.pfs=%#018llx\n", istate->ar_ifs, 142 istate->ar_pfs); 143 printf("cr.isr=%#018llx\tcr.ipsr=%#018llx\t\n", istate->cr_isr.value, 144 istate->cr_ipsr); 145 146 printf("cr.iip=%#018llx, #%d\t(%s)\n", istate->cr_iip, istate->cr_isr.ei, 137 printf("ar.bsp=%p\tar.bspstore=%p\n", 138 (void *) istate->ar_bsp, (void *) istate->ar_bspstore); 139 printf("ar.rnat=%#0" PRIx64 "\tar.rsc=%#0" PRIx64 "\n", 140 istate->ar_rnat, istate->ar_rsc); 141 printf("ar.ifs=%#0" PRIx64 "\tar.pfs=%#0" PRIx64 "\n", 142 istate->ar_ifs, istate->ar_pfs); 143 printf("cr.isr=%#0" PRIx64 "\tcr.ipsr=%#0" PRIx64 "\n", 144 istate->cr_isr.value, istate->cr_ipsr.value); 145 146 printf("cr.iip=%#0" PRIx64 ", #%u\t(%s)\n", 147 istate->cr_iip, istate->cr_isr.ei, 147 148 symtab_fmt_name_lookup(istate->cr_iip)); 148 printf("cr.iipa=%#0 18llx\t(%s)\n", istate->cr_iipa,149 printf("cr.iipa=%#0" PRIx64 "\t(%s)\n", istate->cr_iipa, 149 150 symtab_fmt_name_lookup(istate->cr_iipa)); 150 printf("cr.ifa=%#0 18llx\t(%s)\n", istate->cr_ifa,151 printf("cr.ifa=%#0" PRIx64 "\t(%s)\n", istate->cr_ifa, 151 152 symtab_fmt_name_lookup(istate->cr_ifa)); 152 153 } -
kernel/arch/ia64/src/mm/tlb.c
r202f57b r7e752b2 499 499 page_table_unlock(AS, true); 500 500 if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) { 501 fault_if_from_uspace(istate, "Page fault at %p.", va); 501 fault_if_from_uspace(istate, "Page fault at %p.", 502 (void *) va); 502 503 panic_memtrap(istate, PF_ACCESS_EXEC, va, NULL); 503 504 } … … 556 557 } else { 557 558 fault_if_from_uspace(istate, 558 "IO access fault at %p.", va);559 "IO access fault at %p.", (void *) va); 559 560 } 560 561 } … … 620 621 */ 621 622 if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { 622 fault_if_from_uspace(istate, "Page fault at %p.", va); 623 fault_if_from_uspace(istate, "Page fault at %p.", 624 (void *) va); 623 625 panic_memtrap(istate, PF_ACCESS_UNKNOWN, va, NULL); 624 626 } … … 668 670 } else { 669 671 if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) { 670 fault_if_from_uspace(istate, "Page fault at %p.", va); 672 fault_if_from_uspace(istate, "Page fault at %p.", 673 (void *) va); 671 674 panic_memtrap(istate, PF_ACCESS_WRITE, va, NULL); 672 675 } … … 704 707 } else { 705 708 if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) { 706 fault_if_from_uspace(istate, "Page fault at %p.", va); 709 fault_if_from_uspace(istate, "Page fault at %p.", 710 (void *) va); 707 711 panic_memtrap(istate, PF_ACCESS_EXEC, va, NULL); 708 712 } … … 740 744 } else { 741 745 if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { 742 fault_if_from_uspace(istate, "Page fault at %p.", va); 746 fault_if_from_uspace(istate, "Page fault at %p.", 747 (void *) va); 743 748 panic_memtrap(istate, PF_ACCESS_UNKNOWN, va, NULL); 744 749 } … … 772 777 ASSERT(!t->w); 773 778 if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) { 774 fault_if_from_uspace(istate, "Page fault at %p.", va); 779 fault_if_from_uspace(istate, "Page fault at %p.", 780 (void *) va); 775 781 panic_memtrap(istate, PF_ACCESS_WRITE, va, NULL); 776 782 } … … 812 818 page_table_unlock(AS, true); 813 819 if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { 814 fault_if_from_uspace(istate, "Page fault at %p.", va); 820 fault_if_from_uspace(istate, "Page fault at %p.", 821 (void *) va); 815 822 panic_memtrap(istate, PF_ACCESS_UNKNOWN, va, NULL); 816 823 } -
kernel/arch/mips32/src/cache.c
r202f57b r7e752b2 39 39 void cache_error(istate_t *istate) 40 40 { 41 panic("cache_error exception (epc=%p).", istate->epc);41 panic("cache_error exception (epc=%p).", (void *) istate->epc); 42 42 } 43 43 -
kernel/arch/mips32/src/debugger.c
r202f57b r7e752b2 191 191 } 192 192 193 printf("Adding breakpoint on address %p\n", argv->intval);193 printf("Adding breakpoint on address %p\n", (void *) argv->intval); 194 194 195 195 cur->address = (uintptr_t) argv->intval; … … 267 267 breakpoints[i].address); 268 268 269 printf("%-4u %7 " PRIs "%p %-8s %-9s %-10s %s\n", i,270 breakpoints[i].counter, breakpoints[i].address,269 printf("%-4u %7zu %p %-8s %-9s %-10s %s\n", i, 270 breakpoints[i].counter, (void *) breakpoints[i].address, 271 271 ((breakpoints[i].flags & BKPOINT_INPROG) ? "true" : 272 272 "false"), ((breakpoints[i].flags & BKPOINT_ONESHOT) … … 366 366 367 367 if (!(cur->flags & BKPOINT_FUNCCALL)) { 368 printf("***Breakpoint %u: %p in %s.\n", i, fireaddr, 368 printf("***Breakpoint %u: %p in %s.\n", i, 369 (void *) fireaddr, 369 370 symtab_fmt_name_lookup(fireaddr)); 370 371 } … … 381 382 cur->flags |= BKPOINT_INPROG; 382 383 } else { 383 printf("***Breakpoint %d: %p in %s.\n", i, fireaddr, 384 printf("***Breakpoint %d: %p in %s.\n", i, 385 (void *) fireaddr, 384 386 symtab_fmt_name_lookup(fireaddr)); 385 387 -
kernel/arch/mips32/src/exception.c
r202f57b r7e752b2 74 74 void istate_decode(istate_t *istate) 75 75 { 76 printf("epc=%p\tsta=%p\tlo =%p\thi =%p\n", 77 istate->epc, istate->status, istate->lo, istate->hi); 78 printf("a0 =%p\ta1 =%p\ta2 =%p\ta3 =%p\n", 76 printf("epc=%p\tsta=%#0" PRIx32 "\t" 77 "lo =%#0" PRIx32 "\thi =%#0" PRIx32 "\n", 78 (void *) istate->epc, istate->status, 79 istate->lo, istate->hi); 80 81 printf("a0 =%#0" PRIx32 "\ta1 =%#0" PRIx32 "\t" 82 "a2 =%#0" PRIx32 "\ta3 =%#0" PRIx32 "\n", 79 83 istate->a0, istate->a1, istate->a2, istate->a3); 80 printf("t0 =%p\tt1 =%p\tt2 =%p\tt3 =%p\n", 84 85 printf("t0 =%#0" PRIx32 "\tt1 =%#0" PRIx32 "\t" 86 "t2 =%#0" PRIx32 "\tt3 =%#0" PRIx32 "\n", 81 87 istate->t0, istate->t1, istate->t2, istate->t3); 82 printf("t4 =%p\tt5 =%p\tt6 =%p\tt7 =%p\n", 88 89 printf("t4 =%#0" PRIx32 "\tt5 =%#0" PRIx32 "\t" 90 "t6 =%#0" PRIx32 "\tt7 =%#0" PRIx32 "\n", 83 91 istate->t4, istate->t5, istate->t6, istate->t7); 84 printf("t8 =%p\tt9 =%p\tv0 =%p\tv1 =%p\n", 92 93 printf("t8 =%#0" PRIx32 "\tt9 =%#0" PRIx32 "\t" 94 "v0 =%#0" PRIx32 "\tv1 =%#0" PRIx32 "\n", 85 95 istate->t8, istate->t9, istate->v0, istate->v1); 86 printf("s0 =%p\ts1 =%p\ts2 =%p\ts3 =%p\n", 96 97 printf("s0 =%#0" PRIx32 "\ts1 =%#0" PRIx32 "\t" 98 "s2 =%#0" PRIx32 "\ts3 =%#0" PRIx32 "\n", 87 99 istate->s0, istate->s1, istate->s2, istate->s3); 88 printf("s4 =%p\ts5 =%p\ts6 =%p\ts7 =%p\n", 100 101 printf("s4 =%#0" PRIx32 "\ts5 =%#0" PRIx32 "\t" 102 "s6 =%#0" PRIx32 "\ts7 =%#0" PRIx32 "\n", 89 103 istate->s4, istate->s5, istate->s6, istate->s7); 90 printf("s8 =%p\tat =%p\tkt0=%p\tkt1=%p\n", 104 105 printf("s8 =%#0" PRIx32 "\tat =%#0" PRIx32 "\t" 106 "kt0=%#0" PRIx32 "\tkt1=%#0" PRIx32 "\n", 91 107 istate->s8, istate->at, istate->kt0, istate->kt1); 108 92 109 printf("sp =%p\tra =%p\tgp =%p\n", 93 istate->sp, istate->ra, istate->gp); 110 (void *) istate->sp, (void *) istate->ra, 111 (void *) istate->gp); 94 112 } 95 113 -
kernel/arch/mips32/src/mm/tlb.c
r202f57b r7e752b2 323 323 uintptr_t va = cp0_badvaddr_read(); 324 324 325 fault_if_from_uspace(istate, "TLB Refill Exception on %p.", va); 325 fault_if_from_uspace(istate, "TLB Refill Exception on %p.", 326 (void *) va); 326 327 panic_memtrap(istate, PF_ACCESS_UNKNOWN, va, "TLB Refill Exception."); 327 328 } … … 332 333 uintptr_t va = cp0_badvaddr_read(); 333 334 334 fault_if_from_uspace(istate, "TLB Invalid Exception on %p.", va); 335 fault_if_from_uspace(istate, "TLB Invalid Exception on %p.", 336 (void *) va); 335 337 panic_memtrap(istate, PF_ACCESS_UNKNOWN, va, "TLB Invalid Exception."); 336 338 } … … 340 342 uintptr_t va = cp0_badvaddr_read(); 341 343 342 fault_if_from_uspace(istate, "TLB Modified Exception on %p.", va); 344 fault_if_from_uspace(istate, "TLB Modified Exception on %p.", 345 (void *) va); 343 346 panic_memtrap(istate, PF_ACCESS_WRITE, va, "TLB Modified Exception."); 344 347 } -
kernel/arch/ppc32/src/cpu/cpu.c
r202f57b r7e752b2 68 68 } 69 69 70 printf("cpu% " PRIs ": version=%" PRIu16" (%s), revision=%" PRIu16 "\n", cpu->id,70 printf("cpu%u: version=%" PRIu16" (%s), revision=%" PRIu16 "\n", cpu->id, 71 71 cpu->arch.version, name, cpu->arch.revision); 72 72 } -
kernel/arch/ppc32/src/interrupt.c
r202f57b r7e752b2 54 54 void istate_decode(istate_t *istate) 55 55 { 56 printf("r0 =%p\tr1 =%p\tr2 =%p\n", istate->r0, istate->sp, istate->r2); 57 printf("r3 =%p\tr4 =%p\tr5 =%p\n", istate->r3, istate->r4, istate->r5); 58 printf("r6 =%p\tr7 =%p\tr8 =%p\n", istate->r6, istate->r7, istate->r8); 59 printf("r9 =%p\tr10=%p\tr11=%p\n", 56 printf("r0 =%#0" PRIx32 "\tr1 =%p\tr2 =%#0" PRIx32 "\n", 57 istate->r0, (void *) istate->sp, istate->r2); 58 59 printf("r3 =%#0" PRIx32 "\tr4 =%#0" PRIx32 "\tr5 =%#0" PRIx32 "\n", 60 istate->r3, istate->r4, istate->r5); 61 62 printf("r6 =%#0" PRIx32 "\tr7 =%#0" PRIx32 "\tr8 =%#0" PRIx32 "\n", 63 istate->r6, istate->r7, istate->r8); 64 65 printf("r9 =%#0" PRIx32 "\tr10=%#0" PRIx32 "\tr11=%#0" PRIx32 "\n", 60 66 istate->r9, istate->r10, istate->r11); 61 printf("r12=%p\tr13=%p\tr14=%p\n", 67 68 printf("r12=%#0" PRIx32 "\tr13=%#0" PRIx32 "\tr14=%#0" PRIx32 "\n", 62 69 istate->r12, istate->r13, istate->r14); 63 printf("r15=%p\tr16=%p\tr17=%p\n", 70 71 printf("r15=%#0" PRIx32 "\tr16=%#0" PRIx32 "\tr17=%#0" PRIx32 "\n", 64 72 istate->r15, istate->r16, istate->r17); 65 printf("r18=%p\tr19=%p\tr20=%p\n", 73 74 printf("r18=%#0" PRIx32 "\tr19=%#0" PRIx32 "\tr20=%#0" PRIx32 "\n", 66 75 istate->r18, istate->r19, istate->r20); 67 printf("r21=%p\tr22=%p\tr23=%p\n", 76 77 printf("r21=%#0" PRIx32 "\tr22=%#0" PRIx32 "\tr23=%#0" PRIx32 "\n", 68 78 istate->r21, istate->r22, istate->r23); 69 printf("r24=%p\tr25=%p\tr26=%p\n", 79 80 printf("r24=%#0" PRIx32 "\tr25=%#0" PRIx32 "\tr26=%#0" PRIx32 "\n", 70 81 istate->r24, istate->r25, istate->r26); 71 printf("r27=%p\tr28=%p\tr29=%p\n", 82 83 printf("r27=%#0" PRIx32 "\tr28=%#0" PRIx32 "\tr29=%#0" PRIx32 "\n", 72 84 istate->r27, istate->r28, istate->r29); 73 printf("r30=%p\tr31=%p\n", istate->r30, istate->r31); 74 printf("cr =%p\tpc =%p\tlr =%p\n", istate->cr, istate->pc, istate->lr); 75 printf("ctr=%p\txer=%p\tdar=%p\n", 85 86 printf("r30=%#0" PRIx32 "\tr31=%#0" PRIx32 "\n", 87 istate->r30, istate->r31); 88 89 printf("cr =%#0" PRIx32 "\tpc =%p\tlr =%p\n", 90 istate->cr, (void *) istate->pc, (void *) istate->lr); 91 92 printf("ctr=%#0" PRIx32 "\txer=%#0" PRIx32 "\tdar=%#0" PRIx32 "\n", 76 93 istate->ctr, istate->xer, istate->dar); 77 printf("srr1=%p\n", istate->srr1); 94 95 printf("srr1=%p\n", (void *) istate->srr1); 78 96 } 79 97 … … 111 129 */ 112 130 #ifdef CONFIG_DEBUG 113 printf("cpu% " PRIs ": spurious interrupt (inum=%" PRIu8 ")\n",131 printf("cpu%u: spurious interrupt (inum=%" PRIu8 ")\n", 114 132 CPU->id, inum); 115 133 #endif -
kernel/arch/ppc32/src/mm/frame.c
r202f57b r7e752b2 49 49 size_t i; 50 50 for (i = 0; i < memmap.cnt; i++) { 51 printf("% #10x %#10x\n", memmap.zones[i].start,51 printf("%p %#0zx\n", memmap.zones[i].start, 52 52 memmap.zones[i].size); 53 53 } -
kernel/arch/ppc32/src/mm/page.c
r202f57b r7e752b2 49 49 if (last_frame + ALIGN_UP(size, PAGE_SIZE) > 50 50 KA2PA(KERNEL_ADDRESS_SPACE_END_ARCH)) 51 panic("Unable to map physical memory %p (% " PRIs "bytes).",52 physaddr, size);51 panic("Unable to map physical memory %p (%zu bytes).", 52 (void *) physaddr, size); 53 53 54 54 uintptr_t virtaddr = PA2KA(last_frame); -
kernel/arch/ppc32/src/mm/tlb.c
r202f57b r7e752b2 111 111 static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate) 112 112 { 113 fault_if_from_uspace(istate, "PHT Refill Exception on %p.", badvaddr); 113 fault_if_from_uspace(istate, "PHT Refill Exception on %p.", 114 (void *) badvaddr); 114 115 panic_memtrap(istate, PF_ACCESS_UNKNOWN, badvaddr, 115 116 "PHT Refill Exception."); … … 459 460 length = 0; \ 460 461 \ 461 printf(name ": page=%.*p frame=%.*p length=%d KB (mask=%#x)%s%s\n", \ 462 sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, \ 463 lower & 0xffff0000, length, mask, \ 462 printf(name ": page=%#0" PRIx32 " frame=%#0" PRIx32 \ 463 " length=%#0" PRIx32 " KB (mask=%#0" PRIx32 ")%s%s\n", \ 464 upper & UINT32_C(0xffff0000), lower & UINT32_C(0xffff0000), \ 465 length, mask, \ 464 466 ((upper >> 1) & 1) ? " supervisor" : "", \ 465 467 (upper & 1) ? " user" : ""); 466 468 467 468 469 void tlb_print(void) 469 470 { … … 473 474 uint32_t vsid = sr_get(sr << 28); 474 475 475 printf("sr[%02u]: vsid=%.*p (asid=%u)%s%s\n", sr, 476 sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4, 476 printf("sr[%02" PRIu32 "]: vsid=%#0" PRIx32 " (asid=%" PRIu32 ")" 477 "%s%s\n", sr, vsid & UINT32_C(0x00ffffff), 478 (vsid & UINT32_C(0x00ffffff)) >> 4, 477 479 ((vsid >> 30) & 1) ? " supervisor" : "", 478 480 ((vsid >> 29) & 1) ? " user" : ""); -
kernel/arch/sparc64/src/console.c
r202f57b r7e752b2 70 70 ofw_tree_node_t *screen = ofw_tree_lookup(prop_scr->value); 71 71 if (!screen) 72 panic("Cannot find %s.", prop_scr->value);72 panic("Cannot find %s.", (char *) prop_scr->value); 73 73 74 74 scr_init(screen); … … 83 83 ofw_tree_node_t *keyboard = ofw_tree_lookup(prop_kbd->value); 84 84 if (!keyboard) 85 panic("Cannot find %s.", prop_kbd->value);85 panic("Cannot find %s.", (char *) prop_kbd->value); 86 86 87 87 kbd_init(keyboard); -
kernel/arch/sparc64/src/drivers/pci.c
r202f57b r7e752b2 211 211 * Unsupported model. 212 212 */ 213 printf("Unsupported PCI controller model (%s).\n", prop->value); 213 printf("Unsupported PCI controller model (%s).\n", 214 (char *) prop->value); 214 215 } 215 216 -
kernel/arch/sparc64/src/mm/sun4u/tlb.c
r202f57b r7e752b2 360 360 static void print_tlb_entry(int i, tlb_tag_read_reg_t t, tlb_data_t d) 361 361 { 362 printf("% d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, "363 "ie=% d, soft2=%#x, pfn=%#x, soft=%#x, l=%d, "364 "cp=% d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i,t.vpn,362 printf("%u: vpn=%#" PRIx64 ", context=%u, v=%u, size=%u, nfo=%u, " 363 "ie=%u, soft2=%#x, pfn=%#x, soft=%#x, l=%u, " 364 "cp=%u, cv=%u, e=%u, p=%u, w=%u, g=%u\n", i, (uint64_t) t.vpn, 365 365 t.context, d.v, d.size, d.nfo, d.ie, d.soft2, 366 366 d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); … … 441 441 uintptr_t va, const char *str) 442 442 { 443 fault_if_from_uspace(istate, "%s, Address=%p.", str,va);443 fault_if_from_uspace(istate, "%s, address=%p.", str, (void *) va); 444 444 panic_memtrap(istate, PF_ACCESS_EXEC, va, str); 445 445 } … … 451 451 452 452 va = tag.vpn << MMU_PAGE_WIDTH; 453 fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d).", str, va,454 tag.context);453 fault_if_from_uspace(istate, "%s, page=%p (asid=%u).", str, 454 (void *) va, tag.context); 455 455 panic_memtrap(istate, PF_ACCESS_UNKNOWN, va, str); 456 456 } … … 462 462 463 463 va = tag.vpn << MMU_PAGE_WIDTH; 464 fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d).", str, va,465 tag.context);464 fault_if_from_uspace(istate, "%s, page=%p (asid=%u).", str, 465 (void *) va, tag.context); 466 466 panic_memtrap(istate, PF_ACCESS_WRITE, va, str); 467 467 } … … 484 484 sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, sfsr.ow, sfsr.fv); 485 485 #endif 486 487 printf("DTLB SFAR: address=%p\n", sfar);486 487 printf("DTLB SFAR: address=%p\n", (void *) sfar); 488 488 489 489 dtlb_sfsr_write(0); … … 508 508 #endif 509 509 510 printf("DTLB SFAR: address=%p\n", sfar);510 printf("DTLB SFAR: address=%p\n", (void *) sfar); 511 511 512 512 dtlb_sfsr_write(0); -
kernel/arch/sparc64/src/mm/sun4v/tlb.c
r202f57b r7e752b2 358 358 const char *str) 359 359 { 360 fault_if_from_uspace(istate, "%s, Address=%p.", str, va); 360 fault_if_from_uspace(istate, "%s, address=%p.", str, 361 (void *) va); 361 362 panic_memtrap(istate, PF_ACCESS_EXEC, va, str); 362 363 } … … 365 366 uint64_t page_and_ctx, const char *str) 366 367 { 367 fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d).", str,368 DMISS_ADDRESS(page_and_ctx), DMISS_CONTEXT(page_and_ctx));368 fault_if_from_uspace(istate, "%s, page=%p (asid=%" PRId64 ").", str, 369 (void *) DMISS_ADDRESS(page_and_ctx), DMISS_CONTEXT(page_and_ctx)); 369 370 panic_memtrap(istate, PF_ACCESS_UNKNOWN, DMISS_ADDRESS(page_and_ctx), 370 371 str); … … 374 375 uint64_t page_and_ctx, const char *str) 375 376 { 376 fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d).", str,377 DMISS_ADDRESS(page_and_ctx), DMISS_CONTEXT(page_and_ctx));377 fault_if_from_uspace(istate, "%s, page=%p (asid=%" PRId64 ").", str, 378 (void *) DMISS_ADDRESS(page_and_ctx), DMISS_CONTEXT(page_and_ctx)); 378 379 panic_memtrap(istate, PF_ACCESS_WRITE, DMISS_ADDRESS(page_and_ctx), 379 380 str); … … 399 400 uint64_t errno = __hypercall_fast3(MMU_DEMAP_ALL, 0, 0, 400 401 MMU_FLAG_DTLB | MMU_FLAG_ITLB); 401 if (errno != HV_EOK) { 402 panic("Error code = %d.\n", errno); 403 } 402 if (errno != HV_EOK) 403 panic("Error code = %" PRIu64 ".\n", errno); 404 404 } 405 405 -
kernel/arch/sparc64/src/sun4v/md.c
r202f57b r7e752b2 310 310 retval = retval; 311 311 if (retval != HV_EOK) { 312 printf("Could not retrieve machine description, error = %d.\n",313 retval);312 printf("Could not retrieve machine description, " 313 "error=%" PRIu64 ".\n", retval); 314 314 } 315 315 } -
kernel/arch/sparc64/src/trap/sun4v/interrupt.c
r202f57b r7e752b2 87 87 KA2PA(cpu_mondo_queues[CPU->id]), 88 88 CPU_MONDO_NENTRIES) != HV_EOK) 89 panic("Initializing mondo queue failed on CPU % d.\n",89 panic("Initializing mondo queue failed on CPU %" PRIu64 ".\n", 90 90 CPU->arch.id); 91 91 }
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