Changeset 43114c5 in mainline for arch

Timestamp:

2005-04-09T18:22:53Z (21 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

8262010

Parents:

e6ba9a3f

Message:

Introduce macros CPU, THREAD, TASK and use them to replace the→cpu, the→thread, the→task.
Later on, this will make it possible to reference *current* cpu, thread and/or task without the aid from virtual memory.

Location:

arch

Files:

• ia32/src/cpu/cpu.c (modified) (4 diffs)
• ia32/src/drivers/i8042.c (modified) (1 diff)
• ia32/src/drivers/i8254.c (modified) (2 diffs)
• ia32/src/drivers/i8259.c (modified) (1 diff)
• ia32/src/smp/apic.c (modified) (5 diffs)
• ia32/src/userspace.c (modified) (1 diff)
• mips/src/cpu/cpu.c (modified) (1 diff)
• mips/src/exception.c (modified) (2 diffs)
• mips/src/mm/tlb.c (modified) (1 diff)

arch/ia32/src/cpu/cpu.c

@@ -62 +62 @@
 void cpu_arch_init(void)
 {
-        the->cpu->arch.tss = tss_p;
+        CPU->arch.tss = tss_p;
 }
 
@@ -71 +71 @@
         int i;
 
-        the->cpu->arch.vendor = VendorUnknown;
+        CPU->arch.vendor = VendorUnknown;
         if (has_cpuid()) {
                 cpuid(0, &info);
@@ -82 +82 @@
                     info.cpuid_edx==AMD_CPUID_EDX) {
                         
-                        the->cpu->arch.vendor = VendorAMD;
+                        CPU->arch.vendor = VendorAMD;
                 }
 
@@ -92 +92 @@
                     info.cpuid_edx==INTEL_CPUID_EDX) {
 
-                        the->cpu->arch.vendor = VendorIntel;
+                        CPU->arch.vendor = VendorIntel;
 
                 }
                                 
                 cpuid(1, &info);
-                the->cpu->arch.family = (info.cpuid_eax>>8)&0xf;
-                the->cpu->arch.model = (info.cpuid_eax>>4)&0xf;
-                the->cpu->arch.stepping = (info.cpuid_eax>>0)&0xf;                                              
+                CPU->arch.family = (info.cpuid_eax>>8)&0xf;
+                CPU->arch.model = (info.cpuid_eax>>4)&0xf;
+                CPU->arch.stepping = (info.cpuid_eax>>0)&0xf;                                           
         }
 }

arch/ia32/src/drivers/i8042.c

@@ -55 +55 @@
         trap_virtual_eoi();
         x = inb(0x60);
-        printf("%d", the->cpu->id);;
+        printf("%d", CPU->id);;
 }

arch/ia32/src/drivers/i8254.c

@@ -111 +111 @@
 
 
-        the->cpu->delay_loop_const = ((MAGIC_NUMBER*LOOPS)/1000) / ((t1-t2)-(o1-o2)) + 
+        CPU->delay_loop_const = ((MAGIC_NUMBER*LOOPS)/1000) / ((t1-t2)-(o1-o2)) + 
                                     (((MAGIC_NUMBER*LOOPS)/1000) % ((t1-t2)-(o1-o2)) ? 1 : 0);
         
@@ -119 +119 @@
         clk2 = rdtsc();
         
-        the->cpu->frequency_mhz = (clk2-clk1)>>SHIFT;
+        CPU->frequency_mhz = (clk2-clk1)>>SHIFT;
 
         return;

arch/ia32/src/drivers/i8259.c

@@ -117 +117 @@
 void pic_spurious(__u8 n, __u32 stack[])
 {
-        printf("cpu%d: PIC spurious interrupt\n", the->cpu->id);
+        printf("cpu%d: PIC spurious interrupt\n", CPU->id);
 }

arch/ia32/src/smp/apic.c

@@ -115 +115 @@
 void apic_spurious(__u8 n, __u32 stack[])
 {
-        printf("cpu%d: APIC spurious interrupt\n", the->cpu->id);
+        printf("cpu%d: APIC spurious interrupt\n", CPU->id);
 }
 
@@ -143 +143 @@
 
 /*
- * Send all CPUs excluding the->cpu IPI vector.
+ * Send all CPUs excluding CPU IPI vector.
  */
 int l_apic_broadcast_custom_ipi(__u8 vector)
@@ -233 +233 @@
         l_apic[TPR] &= TPRClear;
 
-        if (the->cpu->arch.family >= 6)
+        if (CPU->arch.family >= 6)
                 enable_l_apic_in_msr();
         
@@ -271 +271 @@
         int i, lint;
 
-        printf("LVT on cpu%d, LAPIC ID: %d\n", the->cpu->id, (l_apic[L_APIC_ID] >> 24)&0xf);
+        printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, (l_apic[L_APIC_ID] >> 24)&0xf);
 
         printf("LVT_Tm: ");
@@ -305 +305 @@
          * This register is supported only on P6 and higher.
          */
-        if (the->cpu->family > 5) {
+        if (CPU->family > 5) {
                 printf("LVT_PCINT: ");
                 if (l_apic[LVT_PCINT] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');

arch/ia32/src/userspace.c

@@ -43 +43 @@
          * Prepare TSS stack selector and pointers for next syscall.
          */
-        the->cpu->arch.tss->esp0 = (__address) &the->thread->kstack[THREAD_STACK_SIZE-8];
-        the->cpu->arch.tss->ss0 = selector(KDATA_DES);
+        CPU->arch.tss->esp0 = (__address) &THREAD->kstack[THREAD_STACK_SIZE-8];
+        CPU->arch.tss->ss0 = selector(KDATA_DES);
         
         __asm__ volatile (""

arch/mips/src/cpu/cpu.c

@@ -84 +84 @@
 void cpu_identify(void)
 {
-        the->cpu->arch.rev_num = cp0_prid_read() & 0xff;
-        the->cpu->arch.imp_num = (cp0_prid_read() >> 8) & 0xff;
+        CPU->arch.rev_num = cp0_prid_read() & 0xff;
+        CPU->arch.imp_num = (cp0_prid_read() >> 8) & 0xff;
 }
 

arch/mips/src/exception.c

@@ -43 +43 @@
         cp0_status_write(cp0_status_read() & ~ cp0_status_exl_exception_bit);
 
-        if (the->thread) {
-                the->thread->saved_pri = pri;
-                the->thread->saved_epc = epc;
+        if (THREAD) {
+                THREAD->saved_pri = pri;
+                THREAD->saved_epc = epc;
         }
         /* decode exception number and process the exception */
@@ -55 +55 @@
         }
         
-        if (the->thread) {
-                pri = the->thread->saved_pri;
-                epc = the->thread->saved_epc;
+        if (THREAD) {
+                pri = THREAD->saved_pri;
+                epc = THREAD->saved_epc;
         }
 

arch/mips/src/mm/tlb.c

@@ -47 +47 @@
 void tlb_invalid(void)
 {
-        panic(PANIC "%X: TLB exception at %X", cp0_badvaddr_read(), the->thread ? the->thread->saved_epc : 0);
+        panic(PANIC "%X: TLB exception at %X", cp0_badvaddr_read(), THREAD ? THREAD->saved_epc : 0);
 }