source: mainline/arch/ia32/src/smp/apic.c@ 397c77f

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 397c77f was 397c77f, checked in by Jakub Jermar <jakub@…>, 20 years ago

Clean up (ia32 vs. i386).
Header files reorganization.
  • Property mode set to 100644
File size: 10.1 KB
Line 
1/*
2 * Copyright (C) 2001-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifdef __SMP__
30
31#include <arch/types.h>
32#include <arch/smp/apic.h>
33#include <arch/smp/ap.h>
34#include <arch/smp/mp.h>
35#include <mm/page.h>
36#include <time/delay.h>
37#include <arch/interrupt.h>
38#include <print.h>
39#include <arch/asm.h>
40#include <arch.h>
41
42/*
43 * This is functional, far-from-general-enough interface to the APIC.
44 * Advanced Programmable Interrupt Controller for MP systems.
45 * Tested on:
46 * Bochs 2.0.2 with 2-8 CPUs
47 * ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
48 */
49
50/*
51 * These variables either stay configured as initilalized, or are changed by
52 * the MP configuration code.
53 *
54 * Pay special attention to the volatile keyword. Without it, gcc -O2 would
55 * optimize the code too much and accesses to l_apic and io_apic, that must
56 * always be 32-bit, would use byte oriented instructions.
57 */
58volatile __u32 *l_apic = (__u32 *) 0xfee00000;
59volatile __u32 *io_apic = (__u32 *) 0xfec00000;
60
61__u32 apic_id_mask = 0;
62
63int apic_poll_errors(void);
64
65void apic_init(void)
66{
67 __u32 tmp, id, i;
68
69 trap_register(VECTOR_APIC_SPUR, apic_spurious);
70
71 enable_irqs_function = io_apic_enable_irqs;
72 disable_irqs_function = io_apic_disable_irqs;
73 eoi_function = l_apic_eoi;
74
75 /*
76 * Configure interrupt routing.
77 * IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
78 * Other interrupts will be forwarded to the lowest priority CPU.
79 */
80 io_apic_disable_irqs(0xffff);
81 trap_register(VECTOR_CLK, l_apic_timer_interrupt);
82 for (i=1; i<16; i++) {
83 int pin;
84
85 if ((pin = mp_irq_to_pin(i)) != -1)
86 io_apic_change_ioredtbl(pin,0xf,IVT_IRQBASE+i,LOPRI);
87 }
88
89
90 /*
91 * Ensure that io_apic has unique ID.
92 */
93 tmp = io_apic_read(IOAPICID);
94 id = (tmp >> 24) & 0xf;
95 if ((1<<id) & apic_id_mask) {
96 int i;
97
98 for (i=0; i<15; i++) {
99 if (!((1<<i) & apic_id_mask)) {
100 io_apic_write(IOAPICID, (tmp & (~(0xf<<24))) | (i<<24));
101 break;
102 }
103 }
104 }
105
106
107
108 /*
109 * Configure the BSP's lapic.
110 */
111 l_apic_init();
112 l_apic_debug();
113}
114
115void apic_spurious(__u8 n, __u32 stack[])
116{
117 printf("cpu%d: APIC spurious interrupt\n", the->cpu->id);
118}
119
120int apic_poll_errors(void)
121{
122 __u32 esr;
123
124 esr = l_apic[ESR] & ~ESRClear;
125
126 if ((esr>>0) & 1)
127 printf("Send CS Error\n");
128 if ((esr>>1) & 1)
129 printf("Receive CS Error\n");
130 if ((esr>>2) & 1)
131 printf("Send Accept Error\n");
132 if ((esr>>3) & 1)
133 printf("Receive Accept Error\n");
134 if ((esr>>5) & 1)
135 printf("Send Illegal Vector\n");
136 if ((esr>>6) & 1)
137 printf("Received Illegal Vector\n");
138 if ((esr>>7) & 1)
139 printf("Illegal Register Address\n");
140
141 return !esr;
142}
143
144/*
145 * Send all CPUs excluding the->cpu IPI vector.
146 */
147int l_apic_broadcast_custom_ipi(__u8 vector)
148{
149 __u32 lo;
150
151 /*
152 * Read the ICR register in and zero all non-reserved fields.
153 */
154 lo = l_apic[ICRlo] & ICRloClear;
155
156 lo |= DLVRMODE_FIXED | DESTMODE_LOGIC | LEVEL_ASSERT | SHORTHAND_EXCL | TRGRMODE_LEVEL | vector;
157
158 l_apic[ICRlo] = lo;
159
160 lo = l_apic[ICRlo] & ICRloClear;
161 if (lo & SEND_PENDING)
162 printf("IPI is pending.\n");
163
164 return apic_poll_errors();
165}
166
167/*
168 * Universal Start-up Algorithm for bringing up the AP processors.
169 */
170int l_apic_send_init_ipi(__u8 apicid)
171{
172 __u32 lo, hi;
173 int i;
174
175 /*
176 * Read the ICR register in and zero all non-reserved fields.
177 */
178 lo = l_apic[ICRlo] & ICRloClear;
179 hi = l_apic[ICRhi] & ICRhiClear;
180
181 lo |= DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_ASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL;
182 hi |= apicid << 24;
183
184 l_apic[ICRhi] = hi;
185 l_apic[ICRlo] = lo;
186
187 /*
188 * According to MP Specification, 20us should be enough to
189 * deliver the IPI.
190 */
191 delay(20);
192
193 if (!apic_poll_errors()) return 0;
194
195 lo = l_apic[ICRlo] & ICRloClear;
196 if (lo & SEND_PENDING)
197 printf("IPI is pending.\n");
198
199 l_apic[ICRlo] = lo | DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_DEASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL;
200
201 /*
202 * Wait 10ms as MP Specification specifies.
203 */
204 delay(10000);
205
206 /*
207 * MP specification says this should not be done for 82489DX-based
208 * l_apic's. However, everything is ok as long as STARTUP IPI is ignored
209 * by 8249DX.
210 */
211 for (i = 0; i < 2; i++) {
212 lo = l_apic[ICRlo] & ICRloClear;
213 lo |= ((__address) ap_boot) / 4096; /* calculate the reset vector */
214 l_apic[ICRlo] = lo | DLVRMODE_STUP | DESTMODE_PHYS | LEVEL_ASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL;
215 delay(200);
216 }
217
218 return apic_poll_errors();
219}
220
221void l_apic_init(void)
222{
223 __u32 tmp, t1, t2;
224
225
226 l_apic[LVT_Err] |= (1<<16);
227 l_apic[LVT_LINT0] |= (1<<16);
228 l_apic[LVT_LINT1] |= (1<<16);
229
230 tmp = l_apic[SVR] & SVRClear;
231 l_apic[SVR] = tmp | (1<<8) | (VECTOR_APIC_SPUR);
232
233 l_apic[TPR] &= TPRClear;
234
235 if (the->cpu->arch.family >= 6)
236 enable_l_apic_in_msr();
237
238 tmp = l_apic[ICRlo] & ICRloClear;
239 l_apic[ICRlo] = tmp | DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_DEASSERT | SHORTHAND_INCL | TRGRMODE_LEVEL;
240
241 /*
242 * Program the timer for periodic mode and respective vector.
243 */
244
245 l_apic[TDCR] &= TDCRClear;
246 l_apic[TDCR] |= 0xb;
247 tmp = l_apic[LVT_Tm] | (1<<17) | (VECTOR_CLK);
248 l_apic[LVT_Tm] = tmp & ~(1<<16);
249
250 t1 = l_apic[CCRT];
251 l_apic[ICRT] = 0xffffffff;
252
253 while (l_apic[CCRT] == t1)
254 ;
255
256 t1 = l_apic[CCRT];
257 delay(1000);
258 t2 = l_apic[CCRT];
259
260 l_apic[ICRT] = t1-t2;
261}
262
263void l_apic_eoi(void)
264{
265 l_apic[EOI] = 0;
266}
267
268void l_apic_debug(void)
269{
270#ifdef LAPIC_VERBOSE
271 int i, lint;
272
273 printf("LVT on cpu%d, LAPIC ID: %d\n", the->cpu->id, (l_apic[L_APIC_ID] >> 24)&0xf);
274
275 printf("LVT_Tm: ");
276 if (l_apic[LVT_Tm] & (1<<17)) printf("periodic"); else printf("one-shot"); putchar(',');
277 if (l_apic[LVT_Tm] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
278 if (l_apic[LVT_Tm] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
279 printf("%B\n", l_apic[LVT_Tm] & 0xff);
280
281 for (i=0; i<2; i++) {
282 lint = i ? LVT_LINT1 : LVT_LINT0;
283 printf("LVT_LINT%d: ", i);
284 if (l_apic[lint] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
285 if (l_apic[lint] & (1<<15)) printf("level"); else printf("edge"); putchar(',');
286 printf("%d", l_apic[lint] & (1<<14)); putchar(',');
287 printf("%d", l_apic[lint] & (1<<13)); putchar(',');
288 if (l_apic[lint] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
289
290 switch ((l_apic[lint]>>8)&7) {
291 case 0: printf("fixed"); break;
292 case 4: printf("NMI"); break;
293 case 7: printf("ExtINT"); break;
294 }
295 putchar(',');
296 printf("%B\n", l_apic[lint] & 0xff);
297 }
298
299 printf("LVT_Err: ");
300 if (l_apic[LVT_Err] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
301 if (l_apic[LVT_Err] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
302 printf("%B\n", l_apic[LVT_Err] & 0xff);
303
304 /*
305 * This register is supported only on P6 and higher.
306 */
307 if (the->cpu->family > 5) {
308 printf("LVT_PCINT: ");
309 if (l_apic[LVT_PCINT] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
310 if (l_apic[LVT_PCINT] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
311 switch ((l_apic[LVT_PCINT] >> 8)&7) {
312 case 0: printf("fixed"); break;
313 case 4: printf("NMI"); break;
314 case 7: printf("ExtINT"); break;
315 }
316 putchar(',');
317 printf("%B\n", l_apic[LVT_PCINT] & 0xff);
318 }
319#endif
320}
321
322void l_apic_timer_interrupt(__u8 n, __u32 stack[])
323{
324 l_apic_eoi();
325 clock();
326}
327
328__u32 io_apic_read(__u8 address)
329{
330 __u32 tmp;
331
332 tmp = io_apic[IOREGSEL] & ~0xf;
333 io_apic[IOREGSEL] = tmp | address;
334 return io_apic[IOWIN];
335}
336
337void io_apic_write(__u8 address, __u32 x)
338{
339 __u32 tmp;
340
341 tmp = io_apic[IOREGSEL] & ~0xf;
342 io_apic[IOREGSEL] = tmp | address;
343 io_apic[IOWIN] = x;
344}
345
346void io_apic_change_ioredtbl(int signal, int dest, __u8 v, int flags)
347{
348 __u32 reglo, reghi;
349 int dlvr = 0;
350
351 if (flags & LOPRI)
352 dlvr = 1;
353
354 reglo = io_apic_read(IOREDTBL + signal*2);
355 reghi = io_apic_read(IOREDTBL + signal*2 + 1);
356
357 reghi &= ~0x0f000000;
358 reghi |= (dest<<24);
359
360 reglo &= (~0x1ffff) | (1<<16); /* don't touch the mask */
361 reglo |= (0<<15) | (0<<13) | (0<<11) | (dlvr<<8) | v;
362
363 io_apic_write(IOREDTBL + signal*2, reglo);
364 io_apic_write(IOREDTBL + signal*2 + 1, reghi);
365}
366
367void io_apic_disable_irqs(__u16 irqmask)
368{
369 int i,pin;
370 __u32 reglo;
371
372 for (i=0;i<16;i++) {
373 if ((irqmask>>i) & 1) {
374 /*
375 * Mask the signal input in IO APIC if there is a
376 * mapping for the respective IRQ number.
377 */
378 pin = mp_irq_to_pin(i);
379 if (pin != -1) {
380 reglo = io_apic_read(IOREDTBL + pin*2);
381 reglo |= (1<<16);
382 io_apic_write(IOREDTBL + pin*2,reglo);
383 }
384
385 }
386 }
387}
388
389void io_apic_enable_irqs(__u16 irqmask)
390{
391 int i,pin;
392 __u32 reglo;
393
394 for (i=0;i<16;i++) {
395 if ((irqmask>>i) & 1) {
396 /*
397 * Unmask the signal input in IO APIC if there is a
398 * mapping for the respective IRQ number.
399 */
400 pin = mp_irq_to_pin(i);
401 if (pin != -1) {
402 reglo = io_apic_read(IOREDTBL + pin*2);
403 reglo &= ~(1<<16);
404 io_apic_write(IOREDTBL + pin*2,reglo);
405 }
406
407 }
408 }
409
410}
411
412#endif /* __SMP__ */
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