Changeset 387416b in mainline for uspace/lib/libc/arch


Ignore:
Timestamp:
2009-12-12T10:11:35Z (16 years ago)
Author:
Pavel Rimsky <pavel@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
99de22b
Parents:
58d5803d (diff), 1e4cada (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Synchronizing with head.

Location:
uspace/lib/libc/arch
Files:
10 edited

Legend:

Unmodified
Added
Removed

  • uspace/lib/libc/arch/amd64/include/atomic.h

    r58d5803d r387416b  
    3737#ifndef LIBC_amd64_ATOMIC_H_
    3838#define LIBC_amd64_ATOMIC_H_
     39
     40#define LIBC_ARCH_ATOMIC_H_
     41
     42#include <atomicdflt.h>
    3943
    4044static inline void atomic_inc(atomic_t *val) {

  • uspace/lib/libc/arch/arm32/include/atomic.h

    r58d5803d r387416b  
    3737#define LIBC_arm32_ATOMIC_H_
    3838
     39#define LIBC_ARCH_ATOMIC_H_
     40#define CAS
     41
     42#include <atomicdflt.h>
     43#include <bool.h>
     44#include <sys/types.h>
     45
     46extern uintptr_t *ras_page;
     47
     48static inline bool cas(atomic_t *val, long ov, long nv)
     49{
     50        long ret = 0;
     51
     52        /*
     53         * The following instructions between labels 1 and 2 constitute a
     54         * Restartable Atomic Seqeunce. Should the sequence be non-atomic,
     55         * the kernel will restart it.
     56         */
     57        asm volatile (
     58                "1:\n"
     59                "       adr %[ret], 1b\n"
     60                "       str %[ret], %[rp0]\n"
     61                "       adr %[ret], 2f\n"
     62                "       str %[ret], %[rp1]\n"
     63                "       ldr %[ret], %[addr]\n"
     64                "       cmp %[ret], %[ov]\n"
     65                "       streq %[nv], %[addr]\n"
     66                "2:\n"
     67                "       moveq %[ret], #1\n"
     68                "       movne %[ret], #0\n"
     69                : [ret] "+&r" (ret),
     70                  [rp0] "=m" (ras_page[0]),
     71                  [rp1] "=m" (ras_page[1]),
     72                  [addr] "+m" (val->count)
     73                : [ov] "r" (ov),
     74                  [nv] "r" (nv)
     75                : "memory"
     76        );
     77
     78        ras_page[0] = 0;
     79        asm volatile ("" ::: "memory");
     80        ras_page[1] = 0xffffffff;
     81
     82        return (bool) ret;
     83}
     84
    3985/** Atomic addition.
    4086 *
    … …  
    4692static inline long atomic_add(atomic_t *val, int i)
    4793{
    48         int ret;
    49         volatile long * mem = &(val->count);
     94        long ret = 0;
    5095
     96        /*
     97         * The following instructions between labels 1 and 2 constitute a
     98         * Restartable Atomic Seqeunce. Should the sequence be non-atomic,
     99         * the kernel will restart it.
     100         */
    51101        asm volatile (
    52         "1:\n"
    53                 "ldr r2, [%1]\n"
    54                 "add r3, r2, %2\n"
    55                 "str r3, %0\n"
    56                 "swp r3, r3, [%1]\n"
    57                 "cmp r3, r2\n"
    58                 "bne 1b\n"
     102                "1:\n"
     103                "       adr %[ret], 1b\n"
     104                "       str %[ret], %[rp0]\n"
     105                "       adr %[ret], 2f\n"
     106                "       str %[ret], %[rp1]\n"
     107                "       ldr %[ret], %[addr]\n"
     108                "       add %[ret], %[ret], %[imm]\n"
     109                "       str %[ret], %[addr]\n"
     110                "2:\n"
     111                : [ret] "+&r" (ret),
     112                  [rp0] "=m" (ras_page[0]),
     113                  [rp1] "=m" (ras_page[1]),
     114                  [addr] "+m" (val->count)
     115                : [imm] "r" (i)
     116        );
    59117
    60                 : "=m" (ret)
    61                 : "r" (mem), "r" (i)
    62                 : "r3", "r2"
    63         );
     118        ras_page[0] = 0;
     119        asm volatile ("" ::: "memory");
     120        ras_page[1] = 0xffffffff;
    64121
    65122        return ret;

  • uspace/lib/libc/arch/arm32/src/entry.s

    r58d5803d r387416b  
    3636#
    3737# r1 contains the PCB pointer
     38# r2 contains the RAS page address
    3839#
    3940__entry:
     41        # Store the RAS page address into the ras_page variable
     42        ldr r0, =ras_page
     43        str r2, [r0]
     44
    4045        # Pass pcb_ptr to __main as the first argument (in r0)
    4146        mov r0, r1
    … …  
    4348
    4449        bl __exit
     50
     51.data
     52
     53.global ras_page
     54ras_page:
     55        .long 0
     56

  • uspace/lib/libc/arch/arm32/src/syscall.c

    r58d5803d r387416b  
    6060        register sysarg_t __arm_reg_r5 asm("r5") = p6;
    6161        register sysarg_t __arm_reg_r6 asm("r6") = id;
    62 
    63         asm volatile ( "swi"
     62       
     63        asm volatile (
     64                "swi 0"
    6465                : "=r" (__arm_reg_r0)
    6566                : "r" (__arm_reg_r0),
    … …  
    7172                  "r" (__arm_reg_r6)
    7273        );
    73 
     74       
    7475        return __arm_reg_r0;
    7576}

  • uspace/lib/libc/arch/ia32/Makefile.inc

    r58d5803d r387416b  
    3939        arch/$(UARCH)/src/setjmp.S
    4040
     41GCC_CFLAGS += -march=pentium
    4142LFLAGS += -N
    4243

  • uspace/lib/libc/arch/ia32/include/atomic.h

    r58d5803d r387416b  
    3535#ifndef LIBC_ia32_ATOMIC_H_
    3636#define LIBC_ia32_ATOMIC_H_
     37
     38#define LIBC_ARCH_ATOMIC_H_
     39
     40#include <atomicdflt.h>
    3741
    3842static inline void atomic_inc(atomic_t *val) {

  • uspace/lib/libc/arch/ia64/include/atomic.h

    r58d5803d r387416b  
    3535#ifndef LIBC_ia64_ATOMIC_H_
    3636#define LIBC_ia64_ATOMIC_H_
     37
     38#define LIBC_ARCH_ATOMIC_H_
     39
     40#include <atomicdflt.h>
    3741
    3842static inline void atomic_inc(atomic_t *val)

  • uspace/lib/libc/arch/mips32/include/atomic.h

    r58d5803d r387416b  
    3636#ifndef LIBC_mips32_ATOMIC_H_
    3737#define LIBC_mips32_ATOMIC_H_
     38
     39#define LIBC_ARCH_ATOMIC_H_
     40
     41#include <atomicdflt.h>
    3842
    3943#define atomic_inc(x)   ((void) atomic_add(x, 1))

  • uspace/lib/libc/arch/ppc32/include/atomic.h

    r58d5803d r387416b  
    3535#ifndef LIBC_ppc32_ATOMIC_H_
    3636#define LIBC_ppc32_ATOMIC_H_
     37
     38#define LIBC_ARCH_ATOMIC_H_
     39
     40#include <atomicdflt.h>
    3741
    3842static inline void atomic_inc(atomic_t *val)

  • uspace/lib/libc/arch/sparc64/include/atomic.h

    r58d5803d r387416b  
    3636#define LIBC_sparc64_ATOMIC_H_
    3737
     38#define LIBC_ARCH_ATOMIC_H_
     39
     40#include <atomicdflt.h>
    3841#include <sys/types.h>
    3942
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