source: mainline/uspace/lib/libc/arch/arm32/src/syscall.c@ 9cc0d7c

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 9cc0d7c was 9cc0d7c, checked in by Jakub Jermar <jakub@…>, 18 years ago

Support for six syscall arguments for arm32.

  • Property mode set to 100644
File size: 2.6 KB
Line 
1/*
2 * Copyright (c) 2007 Pavel Jancik
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup libcarm32
30 * @{
31 */
32/** @file
33 * @brief Syscall routine.
34 */
35
36#include <libc.h>
37
38
39/** Syscall routine.
40 *
41 * Stores p1-p4, id to r0-r4 registers and calls <code>swi</code>
42 * instruction. Returned value is read from r0 register.
43 *
44 * @param p1 Parameter 1.
45 * @param p2 Parameter 2.
46 * @param p3 Parameter 3.
47 * @param p4 Parameter 4.
48 * @param id Number of syscall.
49 *
50 * @return Syscall return value.
51 */
52sysarg_t __syscall(const sysarg_t p1, const sysarg_t p2, const sysarg_t p3,
53 const sysarg_t p4, const sysarg_t p5, const sysarg_t p6, const syscall_t id)
54{
55 register sysarg_t __arm_reg_r0 asm("r0") = p1;
56 register sysarg_t __arm_reg_r1 asm("r1") = p2;
57 register sysarg_t __arm_reg_r2 asm("r2") = p3;
58 register sysarg_t __arm_reg_r3 asm("r3") = p4;
59 register sysarg_t __arm_reg_r4 asm("r4") = p5;
60 register sysarg_t __arm_reg_r5 asm("r5") = p6;
61 register sysarg_t __arm_reg_r6 asm("r6") = id;
62
63 asm volatile ( "swi"
64 : "=r" (__arm_reg_r0)
65 : "r" (__arm_reg_r0),
66 "r" (__arm_reg_r1),
67 "r" (__arm_reg_r2),
68 "r" (__arm_reg_r3),
69 "r" (__arm_reg_r4),
70 "r" (__arm_reg_r5),
71 "r" (__arm_reg_r6)
72 );
73
74 return __arm_reg_r0;
75}
76
77/** @}
78 */
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