- Timestamp:
- 2016-05-02T20:58:16Z (9 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 7c4b26c
- Parents:
- 6adb775f (diff), 5035ba05 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the(diff)
links above to see all the changes relative to each parent. - Location:
- kernel
- Files:
-
- 7 added
- 67 edited
- 4 moved
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/abs32le/src/abs32le.c
r6adb775f r32573ff 85 85 } 86 86 87 sysarg_t sys_tls_set(uintptr_t addr)88 {89 return EOK;90 }91 92 87 /** Construct function pointer 93 88 * -
kernel/arch/amd64/Makefile.inc
r6adb775f r32573ff 57 57 arch/$(KARCH)/src/debug/stacktrace_asm.S \ 58 58 arch/$(KARCH)/src/pm.c \ 59 arch/$(KARCH)/src/vreg.c \ 60 arch/$(KARCH)/src/kseg.c \ 59 61 arch/$(KARCH)/src/context.S \ 60 62 arch/$(KARCH)/src/ddi/ddi.c \ … … 90 92 ARCH_AUTOGENS_AG = \ 91 93 arch/$(KARCH)/include/arch/istate_struct.ag \ 92 arch/$(KARCH)/include/arch/context_struct.ag 94 arch/$(KARCH)/include/arch/context_struct.ag \ 95 arch/$(KARCH)/include/arch/kseg_struct.ag -
kernel/arch/amd64/include/arch/asm.h
r6adb775f r32573ff 206 206 } else 207 207 *port = val; 208 }209 210 /** Swap Hidden part of GS register with visible one */211 NO_TRACE static inline void swapgs(void)212 {213 asm volatile (214 "swapgs"215 );216 208 } 217 209 -
kernel/arch/amd64/include/arch/context_struct.ag
r6adb775f r32573ff 75 75 type : uint64_t 76 76 }, 77 { 78 name : tp, 79 type : uint64_t 80 }, 77 81 78 82 { -
kernel/arch/amd64/include/arch/cpu.h
r6adb775f r32573ff 56 56 57 57 /* MSR registers */ 58 #define AMD_MSR_STAR 0xc0000081 59 #define AMD_MSR_LSTAR 0xc0000082 60 #define AMD_MSR_SFMASK 0xc0000084 61 #define AMD_MSR_FS 0xc0000100 62 #define AMD_MSR_GS 0xc0000101 58 #define AMD_MSR_STAR 0xc0000081 59 #define AMD_MSR_LSTAR 0xc0000082 60 #define AMD_MSR_SFMASK 0xc0000084 61 #define AMD_MSR_FS 0xc0000100 62 #define AMD_MSR_GS 0xc0000101 63 #define AMD_MSR_GS_KERNEL 0xc0000102 63 64 64 65 #ifndef __ASM__ -
kernel/arch/amd64/include/arch/proc/thread.h
r6adb775f r32573ff 36 36 #define KERN_amd64_THREAD_H_ 37 37 38 /* CAUTION: keep these in sync with low level assembly code in syscall_entry */ 39 #define SYSCALL_USTACK_RSP 0 40 #define SYSCALL_KSTACK_RSP 1 38 #include <typedefs.h> 41 39 42 40 typedef struct { 43 sysarg_t tls; 44 /** User and kernel RSP for syscalls. */ 45 uint64_t syscall_rsp[2]; 41 uint64_t kstack_rsp; 46 42 } thread_arch_t; 47 43 -
kernel/arch/amd64/src/amd64.c
r6adb775f r32573ff 56 56 #include <genarch/multiboot/multiboot.h> 57 57 #include <genarch/multiboot/multiboot2.h> 58 #include <arch/pm.h> 59 #include <arch/vreg.h> 60 #include <arch/kseg.h> 58 61 59 62 #ifdef CONFIG_SMP … … 139 142 void arch_post_mm_init(void) 140 143 { 144 vreg_init(); 145 kseg_init(); 146 141 147 if (config.cpu_active == 1) { 142 148 /* Initialize IRQ routing */ … … 262 268 } 263 269 264 /** Set thread-local-storage pointer265 *266 * TLS pointer is set in FS register. Unfortunately the 64-bit267 * part can be set only in CPL0 mode.268 *269 * The specs say, that on %fs:0 there is stored contents of %fs register,270 * we need not to go to CPL0 to read it.271 */272 sysarg_t sys_tls_set(uintptr_t addr)273 {274 THREAD->arch.tls = addr;275 write_msr(AMD_MSR_FS, addr);276 277 return EOK;278 }279 280 270 /** Construct function pointer 281 271 * -
kernel/arch/amd64/src/asm.S
r6adb775f r32573ff 31 31 #include <arch/mm/page.h> 32 32 #include <arch/istate_struct.h> 33 #include <arch/kseg_struct.h> 34 #include <arch/cpu.h> 33 35 34 36 .text … … 178 180 subq $(ISTATE_SOFT_SIZE + 8), %rsp 179 181 .endif 180 182 181 183 /* 182 184 * Save the general purpose registers. … … 199 201 200 202 /* 203 * Is this trap from the kernel? 204 */ 205 cmpq $(GDT_SELECTOR(KTEXT_DES)), ISTATE_OFFSET_CS(%rsp) 206 jz 0f 207 208 /* 209 * Switch to kernel FS base. 210 */ 211 swapgs 212 movl $AMD_MSR_FS, %ecx 213 movl %gs:KSEG_OFFSET_FSBASE, %eax 214 movl %gs:KSEG_OFFSET_FSBASE+4, %edx 215 wrmsr 216 swapgs 217 218 /* 201 219 * Imitate a regular stack frame linkage. 202 220 * Stop stack traces here if we came from userspace. 203 221 */ 204 xorl %edx, %edx 205 cmpq $(GDT_SELECTOR(KTEXT_DES)), ISTATE_OFFSET_CS(%rsp) 222 0: movl $0x0, %edx 206 223 cmovnzq %rdx, %rbp 207 224 … … 272 289 swapgs 273 290 274 /* 275 * %gs:0 Scratch space for this thread's user RSP 276 * %gs:8 Address to be used as this thread's kernel RSP 277 */ 278 279 movq %rsp, %gs:0 /* save this thread's user RSP */ 280 movq %gs:8, %rsp /* set this thread's kernel RSP */ 281 291 movq %rsp, %gs:KSEG_OFFSET_USTACK_RSP /* save this thread's user RSP */ 292 movq %gs:KSEG_OFFSET_KSTACK_RSP, %rsp /* set this thread's kernel RSP */ 293 282 294 /* 283 295 * Note that the space needed for the imitated istate structure has been … … 308 320 309 321 /* 322 * Switch to kernel FS base. 323 */ 324 movl $AMD_MSR_FS, %ecx 325 movl %gs:KSEG_OFFSET_FSBASE, %eax 326 movl %gs:KSEG_OFFSET_FSBASE+4, %edx 327 wrmsr 328 movq ISTATE_OFFSET_RDX(%rsp), %rdx /* restore 3rd argument */ 329 330 /* 310 331 * Save the return address and the userspace stack on locations that 311 332 * would normally be taken by them. 312 333 */ 313 movq %gs: 0, %rax334 movq %gs:KSEG_OFFSET_USTACK_RSP, %rax 314 335 movq %rax, ISTATE_OFFSET_RSP(%rsp) 315 336 movq %rcx, ISTATE_OFFSET_RIP(%rsp) … … 325 346 swapgs 326 347 sti 327 348 328 349 /* Copy the 4th argument where it is expected */ 329 350 movq %r10, %rcx -
kernel/arch/amd64/src/context.S
r6adb775f r32573ff 29 29 #include <abi/asmtool.h> 30 30 #include <arch/context_struct.h> 31 #include <arch/vreg.h> 31 32 32 33 .text … … 50 51 movq %r14, CONTEXT_OFFSET_R14(%rdi) 51 52 movq %r15, CONTEXT_OFFSET_R15(%rdi) 53 54 movq vreg_ptr, %rsi 55 movq %fs:VREG_TP(%rsi), %rsi 56 movq %rsi, CONTEXT_OFFSET_TP(%rdi) 52 57 53 58 xorl %eax, %eax # context_save returns 1 … … 72 77 movq CONTEXT_OFFSET_SP(%rdi), %rsp # ctx->sp -> %rsp 73 78 74 movq CONTEXT_OFFSET_PC(%rdi), %rdx 75 79 movq CONTEXT_OFFSET_PC(%rdi), %rdx 76 80 movq %rdx, (%rsp) 81 82 movq CONTEXT_OFFSET_TP(%rdi), %rcx 83 movq vreg_ptr, %rsi 84 movq %rcx, %fs:VREG_TP(%rsi) 77 85 78 86 xorl %eax, %eax # context_restore returns 0 -
kernel/arch/amd64/src/proc/scheduler.c
r6adb775f r32573ff 42 42 #include <arch/pm.h> 43 43 #include <arch/ddi/ddi.h> 44 #include <arch/kseg_struct.h> 44 45 45 46 /** Perform amd64 specific tasks needed before the new task is run. … … 55 56 void before_thread_runs_arch(void) 56 57 { 57 CPU->arch.tss->rsp0 = 58 (uintptr_t) &THREAD->kstack[STACK_SIZE]; 59 60 /* 61 * Syscall support. 62 */ 63 swapgs(); 64 write_msr(AMD_MSR_GS, (uintptr_t) THREAD->arch.syscall_rsp); 65 swapgs(); 66 67 /* TLS support - set FS to thread local storage */ 68 write_msr(AMD_MSR_FS, THREAD->arch.tls); 58 CPU->arch.tss->rsp0 = (uintptr_t) &THREAD->kstack[STACK_SIZE]; 59 60 kseg_t *kseg = (kseg_t *) read_msr(AMD_MSR_GS_KERNEL); 61 kseg->kstack_rsp = THREAD->arch.kstack_rsp; 69 62 } 70 63 -
kernel/arch/amd64/src/proc/thread.c
r6adb775f r32573ff 35 35 #include <proc/thread.h> 36 36 #include <arch/interrupt.h> 37 #include <arch/kseg_struct.h> 37 38 38 39 /** Perform amd64 specific thread initialization. … … 43 44 void thread_create_arch(thread_t *thread) 44 45 { 45 thread->arch.tls = 0;46 thread->arch.syscall_rsp[SYSCALL_USTACK_RSP] = 0;47 48 46 /* 49 47 * Kernel RSP can be precalculated at thread creation time. 50 48 */ 51 thread->arch. syscall_rsp[SYSCALL_KSTACK_RSP]=49 thread->arch.kstack_rsp = 52 50 (uintptr_t) &thread->kstack[PAGE_SIZE - sizeof(istate_t)]; 53 51 } -
kernel/arch/arm32/Makefile.inc
r6adb775f r32573ff 33 33 ATSIGN = % 34 34 35 GCC_CFLAGS += -fno-omit-frame-pointer -mapcs-frame -march=$(subst _,-,$(PROCESSOR_ARCH)) -mno-unaligned-access 35 GCC_CFLAGS += -fno-omit-frame-pointer -mapcs-frame -march=$(subst _,-,$(PROCESSOR_ARCH)) -mno-unaligned-access -mfpu=vfpv3 36 36 37 37 ifeq ($(CONFIG_FPU),y) … … 70 70 ifeq ($(CONFIG_FPU),y) 71 71 ARCH_SOURCES += arch/$(KARCH)/src/fpu_context.c 72 ARCH_SOURCES += arch/$(KARCH)/src/fpu. s72 ARCH_SOURCES += arch/$(KARCH)/src/fpu.S 73 73 endif 74 74 -
kernel/arch/arm32/src/asm.S
r6adb775f r32573ff 27 27 */ 28 28 29 #include <abi/asmtool.h> 30 29 31 .text 30 32 31 .global memcpy_from_uspace 32 .global memcpy_to_uspace 33 .global memcpy_from_uspace_failover_address 34 .global memcpy_to_uspace_failover_address 35 .global early_putchar 36 37 memcpy_from_uspace: 38 memcpy_to_uspace: 33 FUNCTION_BEGIN(memcpy_from_uspace) 34 FUNCTION_BEGIN(memcpy_to_uspace) 39 35 add r3, r1, #3 40 36 bic r3, r3, #3 … … 94 90 bne 7b 95 91 b 3b 92 FUNCTION_END(memcpy_from_uspace) 93 FUNCTION_END(memcpy_to_uspace) 96 94 97 memcpy_from_uspace_failover_address: 98 memcpy_to_uspace_failover_address: 95 SYMBOL(memcpy_from_uspace_failover_address) 96 SYMBOL(memcpy_to_uspace_failover_address) 99 97 mov r0, #0 100 98 ldmia sp!, {r4, r5, pc} 101 99 102 early_putchar: 100 FUNCTION_BEGIN(early_putchar) 103 101 mov pc, lr 102 FUNCTION_END(early_putchar) 103 -
kernel/arch/arm32/src/context.S
r6adb775f r32573ff 27 27 # 28 28 29 #include <abi/asmtool.h> 30 29 31 .text 30 32 31 .global context_save_arch 32 .global context_restore_arch 33 34 context_save_arch: 33 FUNCTION_BEGIN(context_save_arch) 35 34 stmfd sp!, {r1} 36 35 mrs r1, cpsr … … 44 43 mov r0, #1 45 44 mov pc, lr 45 FUNCTION_END(context_save_arch) 46 46 47 48 context_restore_arch: 47 FUNCTION_BEGIN(context_restore_arch) 49 48 ldmia r0!, {r4} 50 49 mrs r5, cpsr … … 58 57 mov r0, #0 59 58 mov pc, lr 59 FUNCTION_END(context_restore_arch) 60 -
kernel/arch/arm32/src/debug/stacktrace_asm.S
r6adb775f r32573ff 27 27 # 28 28 29 #include <abi/asmtool.h> 30 29 31 .text 30 32 31 .global frame_pointer_get 32 .global program_counter_get 33 34 frame_pointer_get: 33 FUNCTION_BEGIN(frame_pointer_get) 35 34 mov r0, fp 36 35 mov pc, lr 36 FUNCTION_END(frame_pointer_get) 37 37 38 program_counter_get: 38 FUNCTION_BEGIN(program_counter_get) 39 39 mov r0, lr 40 40 mov pc, lr 41 FUNCTION_END(program_counter_get) 42 -
kernel/arch/arm32/src/dummy.S
r6adb775f r32573ff 27 27 # 28 28 29 #include <abi/asmtool.h> 30 29 31 .text 30 32 31 .global calibrate_delay_loop 32 .global asm_delay_loop 33 FUNCTION_BEGIN(calibrate_delay_loop) 34 mov pc, lr 35 FUNCTION_END(calibrate_delay_loop) 33 36 34 .global sys_tls_set 35 .global dummy 36 37 calibrate_delay_loop: 37 FUNCTION_BEGIN(asm_delay_loop) 38 38 mov pc, lr 39 40 asm_delay_loop: 41 mov pc, lr 42 43 # not used on ARM 44 sys_tls_set: 45 46 dummy: 47 mov pc, lr 39 FUNCTION_END(asm_delay_loop) -
kernel/arch/arm32/src/eabi.S
r6adb775f r32573ff 27 27 # 28 28 29 #include <abi/asmtool.h> 30 29 31 .text 30 32 31 .global __aeabi_idiv 32 .global __aeabi_uidiv 33 34 .global __aeabi_idivmod 35 .global __aeabi_uidivmod 36 37 .global __aeabi_ldivmod 38 .global __aeabi_uldivmod 39 40 __aeabi_idiv: 33 FUNCTION_BEGIN(__aeabi_idiv) 41 34 push {lr} 42 35 bl __divsi3 43 36 pop {lr} 44 37 mov pc, lr 38 FUNCTION_END(__aeabi_idiv) 45 39 46 __aeabi_uidiv: 40 FUNCTION_BEGIN(__aeabi_uidiv) 47 41 push {lr} 48 42 bl __udivsi3 49 43 pop {lr} 50 44 mov pc, lr 45 FUNCTION_END(__aeabi_uidiv) 51 46 52 __aeabi_idivmod: 47 FUNCTION_BEGIN(__aeabi_idivmod) 53 48 push {lr} 54 49 sub sp, sp, #12 … … 59 54 pop {lr} 60 55 mov pc, lr 56 FUNCTION_END(__aeabi_idivmod) 61 57 62 __aeabi_uidivmod: 58 FUNCTION_BEGIN(__aeabi_uidivmod) 63 59 push {lr} 64 60 sub sp, sp, #12 … … 69 65 pop {lr} 70 66 mov pc, lr 67 FUNCTION_END(__aeabi_uidivmod) 71 68 72 __aeabi_ldivmod: 69 FUNCTION_BEGIN(__aeabi_ldivmod) 73 70 push {lr} 74 71 sub sp, sp, #24 … … 80 77 pop {lr} 81 78 mov pc, lr 79 FUNCTION_END(__aeabi_ldivmod) 82 80 83 __aeabi_uldivmod: 81 FUNCTION_BEGIN(__aeabi_uldivmod) 84 82 push {lr} 85 83 sub sp, sp, #24 … … 91 89 pop {lr} 92 90 mov pc, lr 91 FUNCTION_END(__aeabi_uldivmod) 92 -
kernel/arch/arm32/src/exc_handler.S
r6adb775f r32573ff 27 27 # 28 28 29 #include <abi/asmtool.h> 30 29 31 .text 30 31 .global irq_exception_entry32 .global fiq_exception_entry33 .global data_abort_exception_entry34 .global prefetch_abort_exception_entry35 .global undef_instr_exception_entry36 .global swi_exception_entry37 .global reset_exception_entry38 39 32 40 33 # Switches to kernel stack and saves all registers there. … … 156 149 .endm 157 150 158 reset_exception_entry: 151 SYMBOL(reset_exception_entry) 159 152 SAVE_REGS_TO_STACK 160 153 mov r0, #0 … … 163 156 LOAD_REGS_FROM_STACK 164 157 165 irq_exception_entry: 158 SYMBOL(irq_exception_entry) 166 159 sub lr, lr, #4 167 160 SAVE_REGS_TO_STACK … … 171 164 LOAD_REGS_FROM_STACK 172 165 173 fiq_exception_entry: 166 SYMBOL(fiq_exception_entry) 174 167 sub lr, lr, #4 175 168 SAVE_REGS_TO_STACK … … 179 172 LOAD_REGS_FROM_STACK 180 173 181 undef_instr_exception_entry: 174 SYMBOL(undef_instr_exception_entry) 182 175 SAVE_REGS_TO_STACK 183 176 mov r0, #1 … … 186 179 LOAD_REGS_FROM_STACK 187 180 188 prefetch_abort_exception_entry: 181 SYMBOL(prefetch_abort_exception_entry) 189 182 sub lr, lr, #4 190 183 SAVE_REGS_TO_STACK … … 194 187 LOAD_REGS_FROM_STACK 195 188 196 data_abort_exception_entry: 189 SYMBOL(data_abort_exception_entry) 197 190 sub lr, lr, #8 198 191 SAVE_REGS_TO_STACK … … 202 195 LOAD_REGS_FROM_STACK 203 196 204 swi_exception_entry: 197 SYMBOL(swi_exception_entry) 205 198 ldr r13, =exc_stack 206 199 SAVE_REGS_TO_STACK -
kernel/arch/arm32/src/fpu.S
r6adb775f r32573ff 27 27 */ 28 28 29 #include <abi/asmtool.h> 30 29 31 .text 30 32 31 .global fpsid_read 32 .global mvfr0_read 33 .global fpscr_read 34 .global fpscr_write 35 .global fpexc_read 36 .global fpexc_write 37 38 .global fpu_context_save_s32 39 .global fpu_context_restore_s32 40 .global fpu_context_save_d16 41 .global fpu_context_restore_d16 42 .global fpu_context_save_d32 43 .global fpu_context_restore_d32 44 45 fpsid_read: 33 FUNCTION_BEGIN(fpsid_read) 46 34 vmrs r0, fpsid 47 35 mov pc, lr 36 FUNCTION_END(fpsid_read) 48 37 49 mvfr0_read: 38 FUNCTION_BEGIN(mvfr0_read) 50 39 vmrs r0, mvfr0 51 40 mov pc, lr 41 FUNCTION_END(mvfr0_read) 52 42 53 fpscr_read: 43 FUNCTION_BEGIN(fpscr_read) 54 44 vmrs r0, fpscr 55 45 mov pc, lr 46 FUNCTION_END(fpscr_read) 56 47 57 fpscr_write: 48 FUNCTION_BEGIN(fpscr_write) 58 49 vmsr fpscr, r0 59 50 mov pc, lr 51 FUNCTION_END(fpscr_write) 60 52 61 fpexc_read: 53 FUNCTION_BEGIN(fpexc_read) 62 54 vmrs r0, fpexc 63 55 mov pc, lr 56 FUNCTION_END(fpexc_read) 64 57 65 fpexc_write: 58 FUNCTION_BEGIN(fpexc_write) 66 59 vmsr fpexc, r0 67 60 mov pc, lr 61 FUNCTION_END(fpexc_write) 68 62 69 fpu_context_save_s32: 63 FUNCTION_BEGIN(fpu_context_save_s32) 70 64 vmrs r1, fpexc 71 65 vmrs r2, fpscr … … 73 67 vstmia r0!, {s0-s31} 74 68 mov pc, lr 69 FUNCTION_END(fpu_context_save_s32) 75 70 76 fpu_context_restore_s32: 71 FUNCTION_BEGIN(fpu_context_restore_s32) 77 72 ldmia r0!, {r1, r2} 78 73 vmsr fpexc, r1 … … 80 75 vldmia r0!, {s0-s31} 81 76 mov pc, lr 77 FUNCTION_END(fpu_context_restore_s32) 82 78 83 fpu_context_save_d16: 79 FUNCTION_BEGIN(fpu_context_save_d16) 84 80 vmrs r1, fpexc 85 81 vmrs r2, fpscr … … 87 83 vstmia r0!, {d0-d15} 88 84 mov pc, lr 85 FUNCTION_END(fpu_context_save_d16) 89 86 90 fpu_context_restore_d16: 87 FUNCTION_BEGIN(fpu_context_restore_d16) 91 88 ldmia r0!, {r1, r2} 92 89 vmsr fpexc, r1 … … 94 91 vldmia r0!, {d0-d15} 95 92 mov pc, lr 93 FUNCTION_END(fpu_context_restore_d16) 96 94 97 fpu_context_save_d32: 95 FUNCTION_BEGIN(fpu_context_save_d32) 98 96 vmrs r1, fpexc 99 97 stmia r0!, {r1} … … 103 101 vstmia r0!, {d16-d31} 104 102 mov pc, lr 103 FUNCTION_END(fpu_context_save_d32) 105 104 106 fpu_context_restore_d32: 105 FUNCTION_BEGIN(fpu_context_restore_d32) 107 106 ldmia r0!, {r1, r2} 108 107 vmsr fpexc, r1 … … 111 110 vldmia r0!, {d16-d31} 112 111 mov pc, lr 112 FUNCTION_END(fpu_context_restore_d32) 113 113 114 115 -
kernel/arch/arm32/src/start.S
r6adb775f r32573ff 27 27 # 28 28 29 #include <abi/asmtool.h> 29 30 #include <arch/asm/boot.h> 30 31 31 32 .text 32 33 33 .global kernel_image_start 34 .global exc_stack 35 .global supervisor_sp 36 37 kernel_image_start: 38 34 SYMBOL(kernel_image_start) 39 35 # initialize Stack pointer for exception modes 40 36 mrs r4, cpsr … … 83 79 84 80 .space 1024 85 exc_stack: 81 SYMBOL(exc_stack) 86 82 87 supervisor_sp: 83 SYMBOL(supervisor_sp) 88 84 .space 4 -
kernel/arch/ia32/Makefile.inc
r6adb775f r32573ff 89 89 arch/$(KARCH)/src/smp/ipi.c \ 90 90 arch/$(KARCH)/src/ia32.c \ 91 arch/$(KARCH)/src/vreg.c \ 91 92 arch/$(KARCH)/src/interrupt.c \ 92 93 arch/$(KARCH)/src/pm.c \ -
kernel/arch/ia32/include/arch/asm.h
r6adb775f r32573ff 439 439 asm volatile ( 440 440 "ltr %[sel]" 441 :: [sel] "r" (sel) 442 ); 443 } 444 445 /** Load GS from descriptor table. 446 * 447 * @param sel Selector specifying descriptor of the GS segment. 448 * 449 */ 450 NO_TRACE static inline void gs_load(uint16_t sel) 451 { 452 asm volatile ( 453 "mov %[sel], %%gs" 441 454 :: [sel] "r" (sel) 442 455 ); -
kernel/arch/ia32/include/arch/context_struct.ag
r6adb775f r32573ff 66 66 }, 67 67 { 68 name : tp, 69 type : uint32_t 70 }, 71 72 { 68 73 name : ipl, 69 74 type : ipl_t -
kernel/arch/ia32/include/arch/pm.h
r6adb775f r32573ff 45 45 #define UDATA_DES 4 46 46 #define TSS_DES 5 47 #define TLS_DES 6 /* Pointer to Thread-Local-Storage data*/47 #define VREG_DES 6 /* Virtual registers */ 48 48 49 49 #ifdef CONFIG_FB … … 169 169 170 170 extern void tss_initialize(tss_t *t); 171 extern void set_tls_desc(uintptr_t tls);172 171 173 172 #endif /* __ASM__ */ -
kernel/arch/ia32/include/arch/proc/thread.h
r6adb775f r32573ff 39 39 40 40 typedef struct { 41 sysarg_t tls;42 41 } thread_arch_t; 43 42 -
kernel/arch/ia32/src/asm.S
r6adb775f r32573ff 183 183 184 184 /* 185 * Save TLS.186 */187 movl %gs, %edx188 movl %edx, ISTATE_OFFSET_GS(%esp)189 190 /*191 185 * Switch to kernel selectors. 192 186 */ 193 movw $(GDT_SELECTOR(KDATA_DES)), %ax 194 movw %ax, %ds 195 movw %ax, %es 187 movl $(GDT_SELECTOR(KDATA_DES)), %eax 188 movl %eax, %ds 189 movl %eax, %es 190 movl $(GDT_SELECTOR(VREG_DES)), %eax 191 movl %eax, %gs 196 192 197 193 /* … … 213 209 214 210 /* 215 * Restore TLS.216 */217 movl ISTATE_OFFSET_GS(%esp), %edx218 movl %edx, %gs219 220 /*221 211 * Prepare return address and userspace stack for SYSEXIT. 222 212 */ … … 252 242 253 243 /* 254 * Save the se lectorregisters.244 * Save the segment registers. 255 245 */ 256 246 movl %gs, %ecx … … 272 262 movl %eax, %ds 273 263 movl %eax, %es 264 movl $(GDT_SELECTOR(VREG_DES)), %eax 265 movl %eax, %gs 274 266 275 267 movl $0, ISTATE_OFFSET_EBP_FRAME(%esp) … … 284 276 285 277 /* 286 * Restore the se lectorregisters.278 * Restore the segment registers. 287 279 */ 288 280 movl ISTATE_OFFSET_GS(%esp), %ecx … … 354 346 355 347 /* 356 * Save the se lectorregisters.348 * Save the segment registers. 357 349 */ 358 350 movl %gs, %ecx … … 374 366 movl %eax, %ds 375 367 movl %eax, %es 368 movl $(GDT_SELECTOR(VREG_DES)), %eax 369 movl %eax, %gs 376 370 377 371 /* -
kernel/arch/ia32/src/context.S
r6adb775f r32573ff 29 29 #include <abi/asmtool.h> 30 30 #include <arch/context_struct.h> 31 #include <arch/vreg.h> 31 32 32 33 .text … … 48 49 movl %edi, CONTEXT_OFFSET_EDI(%edx) # %edi -> ctx->edi 49 50 movl %ebp, CONTEXT_OFFSET_EBP(%edx) # %ebp -> ctx->ebp 51 52 mov vreg_ptr, %ecx 53 movl %gs:VREG_TP(%ecx), %ecx 54 movl %ecx, CONTEXT_OFFSET_TP(%edx) 50 55 51 56 xorl %eax, %eax # context_save returns 1 … … 72 77 73 78 movl %edx, 0(%esp) # put saved pc on stack 79 80 mov vreg_ptr, %ecx 81 movl CONTEXT_OFFSET_TP(%eax), %edx 82 movl %edx, %gs:VREG_TP(%ecx) 83 74 84 xorl %eax, %eax # context_restore returns 0 75 85 ret 76 FUNCTION_END(context_restore_arch) -
kernel/arch/ia32/src/ia32.c
r6adb775f r32573ff 57 57 #include <genarch/multiboot/multiboot.h> 58 58 #include <genarch/multiboot/multiboot2.h> 59 #include <arch/pm.h> 60 #include <arch/vreg.h> 59 61 60 62 #ifdef CONFIG_SMP … … 96 98 void arch_post_mm_init(void) 97 99 { 100 vreg_init(); 101 98 102 if (config.cpu_active == 1) { 99 103 /* Initialize IRQ routing */ … … 122 126 zone_merge_all(); 123 127 } 128 124 129 } 125 130 … … 216 221 } 217 222 218 /** Set thread-local-storage pointer219 *220 * TLS pointer is set in GS register. That means, the GS contains221 * selector, and the descriptor->base is the correct address.222 */223 sysarg_t sys_tls_set(uintptr_t addr)224 {225 THREAD->arch.tls = addr;226 set_tls_desc(addr);227 228 return EOK;229 }230 231 223 /** Construct function pointer 232 224 * -
kernel/arch/ia32/src/pm.c
r6adb775f r32573ff 41 41 #include <panic.h> 42 42 #include <arch/mm/page.h> 43 #include <mm/km.h> 44 #include <mm/frame.h> 43 45 #include <mm/slab.h> 44 46 #include <memstr.h> … … 51 53 52 54 /* 53 * We have no use for segmentation so we set up flat mode. In this54 * mode, we use, for each privilege level, two segments spanning the55 * We don't have much use for segmentation so we set up flat mode. 56 * In this mode, we use, for each privilege level, two segments spanning the 55 57 * whole memory. One is for code and one is for data. 56 58 * 57 * One is for GS register which holds pointer to the TLS thread58 * structure in it's base.59 * One special segment apart of that is for the GS register which holds 60 * a pointer to the VREG page in its base. 59 61 */ 60 62 descriptor_t gdt[GDT_ITEMS] = { … … 71 73 /* TSS descriptor - set up will be completed later */ 72 74 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 73 /* TLS descriptor */74 { 0xffff, 0 , 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },75 /* VREG descriptor - segment used for virtual registers, will be reinitialized later */ 76 { 0xffff, 0 , 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 }, 75 77 /* VESA Init descriptor */ 76 78 #ifdef CONFIG_FB … … 82 84 static idescriptor_t idt[IDT_ITEMS]; 83 85 84 static tss_t tss ;86 static tss_t tss0; 85 87 86 88 tss_t *tss_p = NULL; … … 95 97 { 96 98 d->base_0_15 = base & 0xffff; 97 d->base_16_23 = ( (base)>> 16) & 0xff;98 d->base_24_31 = ( (base)>> 24) & 0xff;99 d->base_16_23 = (base >> 16) & 0xff; 100 d->base_24_31 = (base >> 24) & 0xff; 99 101 } 100 102 … … 265 267 * the heap hasn't been initialized so far. 266 268 */ 267 tss_p = &tss; 268 } 269 else { 269 tss_p = &tss0; 270 } else { 270 271 tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC); 271 272 if (!tss_p) … … 292 293 } 293 294 294 void set_tls_desc(uintptr_t tls)295 {296 ptr_16_32_t cpugdtr;297 descriptor_t *gdt_p;298 299 gdtr_store(&cpugdtr);300 gdt_p = (descriptor_t *) cpugdtr.base;301 gdt_setbase(&gdt_p[TLS_DES], tls);302 /* Reload gdt register to update GS in CPU */303 gdtr_load(&cpugdtr);304 }305 306 295 /** @} 307 296 */ -
kernel/arch/ia32/src/proc/scheduler.c
r6adb775f r32573ff 70 70 CPU->arch.tss->esp0 = kstk; 71 71 CPU->arch.tss->ss0 = GDT_SELECTOR(KDATA_DES); 72 73 /* Set up TLS in GS register */74 set_tls_desc(THREAD->arch.tls);75 72 } 76 73 -
kernel/arch/ia32/src/proc/thread.c
r6adb775f r32573ff 41 41 void thread_create_arch(thread_t *t) 42 42 { 43 t->arch.tls = 0;44 43 } 45 44 -
kernel/arch/ia32/src/userspace.c
r6adb775f r32573ff 59 59 "popfl\n" 60 60 61 /* Set up GS register ( TLS) */62 "movl %[ tls_des], %%gs\n"61 /* Set up GS register (virtual register segment) */ 62 "movl %[vreg_des], %%gs\n" 63 63 64 64 "pushl %[udata_des]\n" … … 81 81 [entry] "r" (kernel_uarg->uspace_entry), 82 82 [uarg] "r" (kernel_uarg->uspace_uarg), 83 [ tls_des] "r" (GDT_SELECTOR(TLS_DES))83 [vreg_des] "r" (GDT_SELECTOR(VREG_DES)) 84 84 : "eax"); 85 85 -
kernel/arch/ia64/Makefile.inc
r6adb775f r32573ff 43 43 arch/$(KARCH)/src/start.S \ 44 44 arch/$(KARCH)/src/asm.S \ 45 arch/$(KARCH)/src/dummy. s\45 arch/$(KARCH)/src/dummy.S \ 46 46 arch/$(KARCH)/src/ia64.c \ 47 47 arch/$(KARCH)/src/fpu_context.c \ -
kernel/arch/ia64/src/asm.S
r6adb775f r32573ff 27 27 */ 28 28 29 #include <abi/asmtool.h> 29 30 #include <arch/register.h> 30 31 31 32 .text 32 .global memcpy_from_uspace33 .global memcpy_to_uspace34 .global memcpy_from_uspace_failover_address35 .global memcpy_to_uspace_failover_address36 33 37 34 /** Copy memory from/to userspace. … … 46 43 * 47 44 */ 48 memcpy_from_uspace: 49 memcpy_to_uspace: 45 FUNCTION_BEGIN(memcpy_from_uspace) 46 FUNCTION_BEGIN(memcpy_to_uspace) 50 47 alloc loc0 = ar.pfs, 3, 1, 0, 0 51 48 … … 132 129 mov ar.pfs = loc0 133 130 br.ret.sptk.many rp 131 FUNCTION_END(memcpy_from_uspace) 132 FUNCTION_END(memcpy_to_uspace) 134 133 135 memcpy_from_uspace_failover_address: 136 memcpy_to_uspace_failover_address: 134 SYMBOL(memcpy_from_uspace_failover_address) 135 SYMBOL(memcpy_to_uspace_failover_address) 137 136 /* Return 0 on failure */ 138 137 mov r8 = r0 … … 140 139 br.ret.sptk.many rp 141 140 142 .global cpu_halt 143 cpu_halt: 141 FUNCTION_BEGIN(cpu_halt) 144 142 br cpu_halt 143 FUNCTION_END(cpu_halt) 145 144 146 145 /** Switch to userspace - low level code. … … 154 153 * 155 154 */ 156 .global switch_to_userspace 157 switch_to_userspace: 155 FUNCTION_BEGIN(switch_to_userspace) 158 156 alloc loc0 = ar.pfs, 6, 3, 0, 0 159 157 … … 191 189 192 190 rfi ;; 191 FUNCTION_END(switch_to_userspace) 193 192 194 .global early_putchar 195 early_putchar: 193 FUNCTION_BEGIN(early_putchar) 196 194 br.ret.sptk.many b0 195 FUNCTION_END(early_putchar) -
kernel/arch/ia64/src/context.S
r6adb775f r32573ff 27 27 # 28 28 29 #include <abi/asmtool.h> 29 30 #include <arch/context_struct.h> 30 31 31 32 .text 32 33 33 .global context_save_arch 34 .global context_restore_arch 35 36 context_save_arch: 34 FUNCTION_BEGIN(context_save_arch) 37 35 alloc loc0 = ar.pfs, 1, 49, 0, 0 38 36 mov loc1 = ar.unat ;; … … 182 180 add r8 = r0, r0, 1 /* context_save returns 1 */ 183 181 br.ret.sptk.many b0 184 185 context_restore_arch: 182 FUNCTION_END(context_save_arch) 183 184 FUNCTION_BEGIN(context_restore_arch) 186 185 alloc loc0 = ar.pfs, 1, 50, 0, 0 ;; 187 186 … … 338 337 mov r8 = r0 /* context_restore returns 0 */ 339 338 br.ret.sptk.many b0 340 339 FUNCTION_END(context_restore_arch) 340 -
kernel/arch/ia64/src/debug/stacktrace_asm.S
r6adb775f r32573ff 27 27 # 28 28 29 #include <abi/asmtool.h> 30 29 31 .text 30 32 31 .global frame_pointer_get 32 .global program_counter_get 33 34 frame_pointer_get: 33 FUNCTION_BEGIN(frame_pointer_get) 35 34 mov r8 = r0 36 35 br.ret.sptk.many b0 36 FUNCTION_END(frame_pointer_get) 37 37 38 program_counter_get: 38 FUNCTION_BEGIN(program_counter_get) 39 39 mov r8 = r0 40 40 br.ret.sptk.many b0 41 FUNCTION_END(program_counter_get) 42 -
kernel/arch/ia64/src/dummy.S
r6adb775f r32573ff 27 27 # 28 28 29 #include <abi/asmtool.h> 30 29 31 .text 30 32 31 .global cpu_sleep 32 .global sys_tls_set 33 FUNCTION_BEGIN(calibrate_delay_loop) 34 FUNCTION_BEGIN(asm_delay_loop) 35 FUNCTION_BEGIN(cpu_sleep) 36 br.ret.sptk.many b0 37 FUNCTION_END(calibrate_delay_loop) 38 FUNCTION_END(asm_delay_loop) 39 FUNCTION_END(cpu_sleep) 33 40 34 .global dummy35 36 cpu_sleep: ! not supported by architecture37 sys_tls_set: ! not needed on architecture38 39 dummy:40 retl41 nop42 43 .global cpu_halt44 cpu_halt:45 ba %xcc, cpu_halt46 nop -
kernel/arch/ia64/src/ia64.c
r6adb775f r32573ff 250 250 } 251 251 252 /** Set thread-local-storage pointer.253 *254 * We use r13 (a.k.a. tp) for this purpose.255 */256 sysarg_t sys_tls_set(uintptr_t addr)257 {258 return EOK;259 }260 261 252 void arch_reboot(void) 262 253 { -
kernel/arch/ia64/src/ivt.S
r6adb775f r32573ff 28 28 # 29 29 30 #include <abi/asmtool.h> 30 31 #include <arch/stack.h> 31 32 #include <arch/register.h> … … 101 102 .endm 102 103 103 .global heavyweight_handler 104 heavyweight_handler: 104 SYMBOL(heavyweight_handler) 105 105 /* 1. copy interrupt registers into bank 0 */ 106 106 … … 297 297 rfi ;; 298 298 299 .global heavyweight_handler_inner 300 heavyweight_handler_inner: 299 FUNCTION_BEGIN(heavyweight_handler_inner) 301 300 /* 302 301 * From this point, the rest of the interrupted context … … 538 537 mov ar.pfs = loc0 539 538 br.ret.sptk.many b0 540 541 .global ivt 539 FUNCTION_END(heavyweight_handler_inner) 540 542 541 .align 32768 543 ivt: 542 SYMBOL(ivt) 544 543 HEAVYWEIGHT_HANDLER 0x00 545 544 HEAVYWEIGHT_HANDLER 0x04 -
kernel/arch/ia64/src/start.S
r6adb775f r32573ff 27 27 # 28 28 29 #include <abi/asmtool.h> 29 30 #include <arch/register.h> 30 31 #include <arch/mm/page.h> … … 41 42 .section K_TEXT_START, "ax" 42 43 43 .global kernel_image_start44 45 44 stack0: 46 45 … … 53 52 # r2 Address of the boot code's bootinfo structure. 54 53 # 55 kernel_image_start: 54 SYMBOL(kernel_image_start) 56 55 .auto 57 56 … … 113 112 rfi ;; 114 113 115 .global paging_start116 114 paging_start: 117 115 -
kernel/arch/mips32/src/asm.S
r6adb775f r32573ff 27 27 */ 28 28 29 #include <abi/asmtool.h> 29 30 #include <arch/asm/regname.h> 30 31 #include <arch/fpu_context_struct.h> … … 48 49 .set nomacro 49 50 50 .global asm_delay_loop 51 asm_delay_loop: 51 FUNCTION_BEGIN(asm_delay_loop) 52 52 j $31 53 53 nop 54 55 .global cpu_halt 56 cpu_halt: 54 FUNCTION_END(asm_delay_loop) 55 56 FUNCTION_BEGIN(cpu_halt) 57 57 j cpu_halt 58 58 nop 59 60 .global memcpy_from_uspace 61 .global memcpy_to_uspace 62 .global memcpy_from_uspace_failover_address 63 .global memcpy_to_uspace_failover_address 64 memcpy_from_uspace: 65 memcpy_to_uspace: 59 FUNCTION_END(cpu_halt) 60 61 FUNCTION_BEGIN(memcpy_from_uspace) 62 FUNCTION_BEGIN(memcpy_to_uspace) 66 63 move $t2, $a0 /* save dst */ 67 64 … … 129 126 jr $ra 130 127 move $v0, $t2 131 132 memcpy_from_uspace_failover_address: 133 memcpy_to_uspace_failover_address: 128 FUNCTION_END(memcpy_from_uspace) 129 FUNCTION_END(memcpy_to_uspace) 130 131 SYMBOL(memcpy_from_uspace_failover_address) 132 SYMBOL(memcpy_to_uspace_failover_address) 134 133 jr $ra 135 134 move $v0, $zero … … 155 154 .endm 156 155 157 .global fpu_context_save 158 fpu_context_save: 156 FUNCTION_BEGIN(fpu_context_save) 159 157 #ifdef CONFIG_FPU 160 158 fpu_gp_save 0, $a0 … … 225 223 j $ra 226 224 nop 227 228 .global fpu_context_restore 229 fpu_context_restore: 225 FUNCTION_END(fpu_context_save) 226 227 FUNCTION_BEGIN(fpu_context_restore) 230 228 #ifdef CONFIG_FPU 231 229 fpu_gp_restore 0, $a0 … … 296 294 j $ra 297 295 nop 298 299 .global early_putchar 300 early_putchar: 296 FUNCTION_END(fpu_context_restore) 297 298 FUNCTION_BEGIN(early_putchar) 301 299 j $ra 302 300 nop 301 FUNCTION_END(early_putchar) -
kernel/arch/mips32/src/context.S
r6adb775f r32573ff 27 27 # 28 28 29 #include <abi/asmtool.h> 29 30 #include <arch/context_struct.h> 30 31 … … 35 36 .set nomacro 36 37 37 .global context_save_arch 38 .global context_restore_arch 39 40 context_save_arch: 38 FUNCTION_BEGIN(context_save_arch) 41 39 sw $s0, CONTEXT_OFFSET_S0($a0) 42 40 sw $s1, CONTEXT_OFFSET_S1($a0) … … 56 54 j $31 57 55 li $2, 1 56 FUNCTION_END(context_save_arch) 58 57 59 context_restore_arch: 58 FUNCTION_BEGIN(context_restore_arch) 60 59 lw $s0, CONTEXT_OFFSET_S0($a0) 61 60 lw $s1, CONTEXT_OFFSET_S1($a0) … … 75 74 j $31 76 75 xor $2, $2 76 FUNCTION_END(context_restore_arch) -
kernel/arch/mips32/src/debug/stacktrace_asm.S
r6adb775f r32573ff 27 27 # 28 28 29 #include <abi/asmtool.h> 30 29 31 .text 30 32 … … 32 34 .set noreorder 33 35 34 .global frame_pointer_get 35 .global program_counter_get 36 37 frame_pointer_get: 36 FUNCTION_BEGIN(frame_pointer_get) 38 37 j $ra 39 38 move $v0, $sp 39 FUNCTION_END(frame_pointer_get) 40 40 41 program_counter_get: 41 FUNCTION_BEGIN(program_counter_get) 42 42 j $ra 43 43 move $v0, $ra 44 FUNCTION_END(program_counter_get) -
kernel/arch/mips32/src/mips32.c
r6adb775f r32573ff 187 187 } 188 188 189 /** Set thread-local-storage pointer190 *191 * We have it currently in K1, it is192 * possible to have it separately in the future.193 */194 sysarg_t sys_tls_set(uintptr_t addr)195 {196 return EOK;197 }198 199 189 void arch_reboot(void) 200 190 { -
kernel/arch/mips32/src/start.S
r6adb775f r32573ff 27 27 # 28 28 29 #include <abi/asmtool.h> 29 30 #include <arch/asm/regname.h> 30 31 #include <arch/mm/page.h> … … 38 39 .set noreorder 39 40 .set nomacro 40 41 .global kernel_image_start42 .global tlb_refill_entry43 .global cache_error_entry44 .global exception_entry45 .global userspace_asm46 41 47 42 /* … … 192 187 193 188 .org 0x0 194 kernel_image_start: 189 SYMBOL(kernel_image_start) 195 190 /* load temporary stack */ 196 191 lui $sp, %hi(end_stack) … … 210 205 end_stack: 211 206 212 tlb_refill_entry: 207 SYMBOL(tlb_refill_entry) 213 208 j tlb_refill_handler 214 209 nop 215 210 216 cache_error_entry: 211 SYMBOL(cache_error_entry) 217 212 j cache_error_handler 218 213 nop 219 214 220 exception_entry: 215 SYMBOL(exception_entry) 221 216 j exception_handler 222 217 nop … … 345 340 eret 346 341 347 userspace_asm: 342 FUNCTION_BEGIN(userspace_asm) 348 343 move $sp, $a0 349 344 move $v0, $a1 … … 352 347 /* set it to 0 */ 353 348 eret 349 FUNCTION_END(userspace_asm) -
kernel/arch/ppc32/Makefile.inc
r6adb775f r32573ff 45 45 arch/$(KARCH)/src/boot/boot.S \ 46 46 arch/$(KARCH)/src/ppc32.c \ 47 arch/$(KARCH)/src/dummy. s\47 arch/$(KARCH)/src/dummy.S \ 48 48 arch/$(KARCH)/src/exception.S \ 49 49 arch/$(KARCH)/src/interrupt.c \ -
kernel/arch/ppc32/src/asm.S
r6adb775f r32573ff 27 27 */ 28 28 29 #include <abi/asmtool.h> 29 30 #include <arch/asm/regname.h> 30 31 #include <arch/msr.h> … … 33 34 .text 34 35 35 .global userspace_asm 36 .global iret 37 .global iret_syscall 38 .global memcpy_from_uspace 39 .global memcpy_to_uspace 40 .global memcpy_from_uspace_failover_address 41 .global memcpy_to_uspace_failover_address 42 .global early_putchar 43 44 userspace_asm: 45 36 FUNCTION_BEGIN(userspace_asm) 46 37 /* 47 38 * r3 = uspace_uarg … … 78 69 79 70 rfi 80 81 iret: 82 71 FUNCTION_END(userspace_asm) 72 73 SYMBOL(iret) 83 74 /* Disable interrupts */ 84 75 … … 142 133 rfi 143 134 144 iret_syscall: 145 135 SYMBOL(iret_syscall) 146 136 /* Disable interrupts */ 147 137 … … 204 194 rfi 205 195 206 memcpy_from_uspace: 207 memcpy_to_uspace: 208 196 FUNCTION_BEGIN(memcpy_from_uspace) 197 FUNCTION_BEGIN(memcpy_to_uspace) 209 198 srwi. r7, r5, 3 210 199 addi r6, r3, -4 … … 267 256 mtctr r7 268 257 b 1b 269 270 memcpy_from_uspace_failover_address: 271 memcpy_to_uspace_failover_address: 258 FUNCTION_END(memcpy_from_uspace) 259 FUNCTION_END(memcpy_to_uspace) 260 261 SYMBOL(memcpy_from_uspace_failover_address) 262 SYMBOL(memcpy_to_uspace_failover_address) 272 263 /* Return zero, failure */ 273 264 xor r3, r3, r3 274 265 blr 275 266 276 early_putchar: 267 FUNCTION_BEGIN(early_putchar) 277 268 blr 269 FUNCTION_END(early_putchar) -
kernel/arch/ppc32/src/boot/boot.S
r6adb775f r32573ff 27 27 # 28 28 29 #include <abi/asmtool.h> 29 30 #include <arch/asm/regname.h> 30 31 #include <config.h> … … 32 33 .section K_TEXT_START, "ax" 33 34 34 .global kernel_image_start 35 kernel_image_start: 36 35 SYMBOL(kernel_image_start) 37 36 # load temporal kernel stack 38 37 -
kernel/arch/ppc32/src/context.S
r6adb775f r32573ff 27 27 # 28 28 29 #include <abi/asmtool.h> 29 30 #include <arch/context_struct.h> 30 31 #include <arch/asm/regname.h> … … 32 33 .text 33 34 34 .global context_save_arch 35 .global context_restore_arch 36 37 context_save_arch: 35 FUNCTION_BEGIN(context_save_arch) 38 36 stw sp, CONTEXT_OFFSET_SP(r3) 39 37 stw r2, CONTEXT_OFFSET_R2(r3) … … 67 65 li r3, 1 68 66 blr 67 FUNCTION_END(context_save_arch) 69 68 70 context_restore_arch: 69 FUNCTION_BEGIN(context_restore_arch) 71 70 lwz sp, CONTEXT_OFFSET_SP(r3) 72 71 lwz r2, CONTEXT_OFFSET_R2(r3) … … 100 99 li r3, 0 101 100 blr 101 FUNCTION_END(context_restore_arch) -
kernel/arch/ppc32/src/debug/stacktrace_asm.S
r6adb775f r32573ff 27 27 # 28 28 29 #include <abi/asmtool.h> 29 30 #include <arch/asm/regname.h> 30 31 31 32 .text 32 33 33 .global frame_pointer_get 34 .global program_counter_get 35 36 frame_pointer_get: 34 FUNCTION_BEGIN(frame_pointer_get) 37 35 mr r3, sp 38 36 blr 37 FUNCTION_END(frame_pointer_get) 39 38 40 program_counter_get: 39 FUNCTION_BEGIN(program_counter_get) 41 40 mflr r3 42 41 blr 42 FUNCTION_END(program_counter_get) -
kernel/arch/ppc32/src/dummy.S
r6adb775f r32573ff 27 27 # 28 28 29 #include <abi/asmtool.h> 30 29 31 .text 30 32 31 .global asm_delay_loop 32 .global sys_tls_set 33 .global cpu_halt 33 FUNCTION_BEGIN(asm_delay_loop) 34 blr 35 FUNCTION_END(asm_delay_loop) 34 36 35 sys_tls_set: 36 b sys_tls_set 37 38 asm_delay_loop: 39 blr 40 41 cpu_halt: 37 FUNCTION_BEGIN(cpu_halt) 42 38 b cpu_halt 39 FUNCTION_END(cpu_halt) -
kernel/arch/ppc32/src/exception.S
r6adb775f r32573ff 27 27 # 28 28 29 #include <abi/asmtool.h> 29 30 #include <arch/asm/regname.h> 30 31 #include <arch/msr.h> … … 126 127 127 128 .org 0x100 128 .global exc_system_reset 129 exc_system_reset: 129 SYMBOL(exc_system_reset) 130 130 CONTEXT_STORE 131 131 … … 134 134 135 135 .org 0x200 136 .global exc_machine_check 137 exc_machine_check: 136 SYMBOL(exc_machine_check) 138 137 CONTEXT_STORE 139 138 … … 142 141 143 142 .org 0x300 144 .global exc_data_storage 145 exc_data_storage: 143 SYMBOL(exc_data_storage) 146 144 CONTEXT_STORE 147 145 … … 150 148 151 149 .org 0x400 152 .global exc_instruction_storage 153 exc_instruction_storage: 150 SYMBOL(exc_instruction_storage) 154 151 CONTEXT_STORE 155 152 … … 158 155 159 156 .org 0x500 160 .global exc_external 161 exc_external: 157 SYMBOL(exc_external) 162 158 CONTEXT_STORE 163 159 … … 166 162 167 163 .org 0x600 168 .global exc_alignment 169 exc_alignment: 164 SYMBOL(exc_alignment) 170 165 CONTEXT_STORE 171 166 … … 174 169 175 170 .org 0x700 176 .global exc_program 177 exc_program: 171 SYMBOL(exc_program) 178 172 CONTEXT_STORE 179 173 … … 182 176 183 177 .org 0x800 184 .global exc_fp_unavailable 185 exc_fp_unavailable: 178 SYMBOL(exc_fp_unavailable) 186 179 CONTEXT_STORE 187 180 … … 190 183 191 184 .org 0x900 192 .global exc_decrementer 193 exc_decrementer: 185 SYMBOL(exc_decrementer) 194 186 CONTEXT_STORE 195 187 … … 198 190 199 191 .org 0xa00 200 .global exc_reserved0 201 exc_reserved0: 192 SYMBOL(exc_reserved0) 202 193 CONTEXT_STORE 203 194 … … 206 197 207 198 .org 0xb00 208 .global exc_reserved1 209 exc_reserved1: 199 SYMBOL(exc_reserved1) 210 200 CONTEXT_STORE 211 201 … … 214 204 215 205 .org 0xc00 216 .global exc_syscall 217 exc_syscall: 206 SYMBOL(exc_syscall) 218 207 CONTEXT_STORE 219 208 … … 221 210 222 211 .org 0xd00 223 .global exc_trace 224 exc_trace: 212 SYMBOL(exc_trace) 225 213 CONTEXT_STORE 226 214 … … 229 217 230 218 .org 0x1000 231 .global exc_itlb_miss 232 exc_itlb_miss: 219 SYMBOL(exc_itlb_miss) 233 220 CONTEXT_STORE 234 221 … … 237 224 238 225 .org 0x1100 239 .global exc_dtlb_miss_load 240 exc_dtlb_miss_load: 226 SYMBOL(exc_dtlb_miss_load) 241 227 CONTEXT_STORE 242 228 … … 245 231 246 232 .org 0x1200 247 .global exc_dtlb_miss_store 248 exc_dtlb_miss_store: 233 SYMBOL(exc_dtlb_miss_store) 249 234 CONTEXT_STORE 250 235 -
kernel/arch/ppc32/src/fpu_context.S
r6adb775f r32573ff 27 27 # 28 28 29 #include <abi/asmtool.h> 29 30 #include <arch/asm/regname.h> 30 31 #include <arch/fpu_context_struct.h> … … 32 33 33 34 .text 34 35 .global fpu_context_save36 .global fpu_context_restore37 .global fpu_init38 .global fpu_enable39 .global fpu_disable40 35 41 36 .macro FPU_CONTEXT_STORE r … … 109 104 .endm 110 105 111 fpu_context_save: 106 FUNCTION_BEGIN(fpu_context_save) 112 107 FPU_CONTEXT_STORE r3 113 108 … … 116 111 117 112 blr 113 FUNCTION_END(fpu_context_save) 118 114 119 fpu_context_restore: 115 FUNCTION_BEGIN(fpu_context_restore) 120 116 lfd fr0, FPU_CONTEXT_OFFSET_FPSCR(r3) 121 117 mtfsf 0xff, fr0 … … 124 120 125 121 blr 122 FUNCTION_END(fpu_context_restore) 126 123 127 fpu_init: 124 FUNCTION_BEGIN(fpu_init) 128 125 mfmsr r0 129 126 ori r0, r0, MSR_FP … … 137 134 138 135 blr 136 FUNCTION_END(fpu_init) 139 137 140 fpu_enable: 138 FUNCTION_BEGIN(fpu_enable) 141 139 mfmsr r0 142 140 ori r0, r0, MSR_FP … … 144 142 isync 145 143 blr 144 FUNCTION_END(fpu_enable) 146 145 147 fpu_disable: 146 FUNCTION_BEGIN(fpu_disable) 148 147 mfmsr r0 149 148 li r3, MSR_FP … … 152 151 isync 153 152 blr 153 FUNCTION_END(fpu_disable) -
kernel/arch/sparc32/src/context.S
r6adb775f r32573ff 28 28 # 29 29 30 #include <abi/asmtool.h> 30 31 #include <arch/context_offset.h> 31 32 #include <arch/arch.h> … … 33 34 .text 34 35 35 .global context_save_arch36 .global context_restore_arch37 38 36 /* 39 37 * context_save_arch() is required not to create its own stack frame. See the 40 38 * generic context.h for explanation. 41 39 */ 42 context_save_arch: 40 FUNCTION_BEGIN(context_save_arch) 43 41 # 44 42 # Force all our active register windows to memory so that we can find … … 62 60 retl 63 61 mov 1, %o0 ! context_save_arch returns 1 62 FUNCTION_END(context_save_arch) 64 63 65 context_restore_arch: 64 FUNCTION_BEGIN(context_restore_arch) 66 65 # 67 66 # Forget all previous windows, they are not going to be needed again. … … 97 96 retl 98 97 xor %o0, %o0, %o0 ! context_restore_arch returns 0 98 FUNCTION_END(context_restore_arch) -
kernel/arch/sparc32/src/sparc32.c
r6adb775f r32573ff 113 113 } 114 114 115 sysarg_t sys_tls_set(uintptr_t addr)116 {117 return EOK;118 }119 120 115 /** Construct function pointer 121 116 * -
kernel/arch/sparc32/src/start.S
r6adb775f r32573ff 27 27 # 28 28 29 #include <abi/asmtool.h> 30 29 31 .text 30 32 31 .global kernel_image_start 32 .global early_putchar 33 .global kernel_sp 34 .global uspace_wbuf 35 36 kernel_image_start: 33 SYMBOL(kernel_image_start) 37 34 # Install trap handlers 38 35 set trap_table, %g1 … … 68 65 nop 69 66 70 early_putchar: 67 FUNCTION_BEGIN(early_putchar) 71 68 set 0x80000100, %l0 72 69 cmp %o0, '\n' … … 80 77 retl 81 78 nop 79 FUNCTION_END(early_putchar) 82 80 83 kernel_sp: 81 SYMBOL(kernel_sp) 84 82 .space 4 85 83 86 uspace_wbuf: 84 SYMBOL(uspace_wbuf) 87 85 .space 4 88 86 -
kernel/arch/sparc32/src/trap_table.S
r6adb775f r32573ff 27 27 # 28 28 29 #include <abi/asmtool.h> 29 30 #include <arch/trap.h> 30 31 #include <arch/regwin.h> 31 32 32 33 .text 33 34 .global trap_table35 .global reset_trap36 .global preemptible_trap37 .global interrupt_trap38 .global syscall_trap39 .global window_overflow_trap40 .global window_underflow_trap41 .global write_to_invalid42 .global read_from_invalid43 .global flush_windows44 34 45 35 .macro get_wim_number reg … … 218 208 .endm 219 209 220 write_to_invalid: 210 FUNCTION_BEGIN(write_to_invalid) 221 211 ! Write value 1 222 212 mov %o0, %g7 … … 236 226 retl 237 227 nop 238 239 read_from_invalid: 228 FUNCTION_END(write_to_invalid) 229 230 FUNCTION_BEGIN(read_from_invalid) 240 231 ! Read value 1 241 232 mov %o0, %g7 … … 255 246 retl 256 247 nop 257 258 reset_trap: 248 FUNCTION_END(read_from_invalid) 249 250 SYMBOL(reset_trap) 259 251 set 0x80000100, %l0 260 252 set 'r', %l1 … … 262 254 rett 263 255 264 window_overflow_trap: 256 SYMBOL(window_overflow_trap) 265 257 mov %g7, %l0 266 258 … … 393 385 rett %l2 394 386 395 window_underflow_trap: 387 SYMBOL(window_underflow_trap) 396 388 mov %g7, %l0 397 389 … … 479 471 rett %l2 480 472 481 flush_windows: 473 FUNCTION_BEGIN(flush_windows) 482 474 mov 7, %g1 483 475 1: … … 494 486 retl 495 487 nop 496 497 preemptible_trap: 488 FUNCTION_END(flush_windows) 489 490 SYMBOL(preemptible_trap) 498 491 /* Save %g7 */ 499 492 mov %g7, %l0 … … 670 663 rett %l2 671 664 672 interrupt_trap: 665 SYMBOL(interrupt_trap) 673 666 /* Save %g7 */ 674 667 mov %g7, %l0 … … 844 837 rett %l2 845 838 846 syscall_trap: 839 SYMBOL(syscall_trap) 847 840 /* Save %g7 */ 848 841 mov %g7, %l0 … … 1051 1044 1052 1045 .align TRAP_TABLE_SIZE 1053 trap_table: 1046 SYMBOL(trap_table) 1054 1047 STRAP(0x0, reset_trap) 1055 1048 TRAP(0x1, instruction_access_exception) -
kernel/arch/sparc64/Makefile.inc
r6adb775f r32573ff 66 66 arch/$(KARCH)/src/context.S \ 67 67 arch/$(KARCH)/src/fpu_context.c \ 68 arch/$(KARCH)/src/dummy. s\68 arch/$(KARCH)/src/dummy.S \ 69 69 arch/$(KARCH)/src/mm/$(USARCH)/km.c \ 70 70 arch/$(KARCH)/src/mm/$(USARCH)/as.c \ -
kernel/arch/sparc64/src/asm.S
r6adb775f r32573ff 27 27 */ 28 28 29 #include <abi/asmtool.h> 29 30 #include <arch/arch.h> 30 31 #include <arch/stack.h> … … 38 39 * Almost the same as memcpy() except the loads are from userspace. 39 40 */ 40 .global memcpy_from_uspace 41 memcpy_from_uspace: 41 FUNCTION_BEGIN(memcpy_from_uspace) 42 42 mov %o0, %o3 /* save dst */ 43 43 add %o1, 7, %g1 … … 108 108 jmp %o7 + 8 /* exit point */ 109 109 mov %o3, %o0 110 FUNCTION_END(memcpy_from_uspace) 110 111 111 112 /* 112 113 * Almost the same as memcpy() except the stores are to userspace. 113 114 */ 114 .global memcpy_to_uspace 115 memcpy_to_uspace: 115 FUNCTION_BEGIN(memcpy_to_uspace) 116 116 mov %o0, %o3 /* save dst */ 117 117 add %o1, 7, %g1 … … 182 182 jmp %o7 + 8 /* exit point */ 183 183 mov %o3, %o0 184 FUNCTION_END(memcpy_to_uspace) 184 185 185 .global memcpy_from_uspace_failover_address 186 .global memcpy_to_uspace_failover_address 187 memcpy_from_uspace_failover_address: 188 memcpy_to_uspace_failover_address: 186 SYMBOL(memcpy_from_uspace_failover_address) 187 SYMBOL(memcpy_to_uspace_failover_address) 189 188 jmp %o7 + 8 /* exit point */ 190 189 mov %g0, %o0 /* return 0 on failure */ 191 190 192 .global early_putchar 193 early_putchar: 191 FUNCTION_BEGIN(early_putchar) 194 192 retl 195 193 nop 194 FUNCTION_END(early_putchar) -
kernel/arch/sparc64/src/context.S
r6adb775f r32573ff 27 27 # 28 28 29 #include <abi/asmtool.h> 29 30 #include <arch/context_struct.h> 30 31 #include <arch/arch.h> … … 33 34 .text 34 35 35 .global context_save_arch36 .global context_restore_arch37 38 36 /* 39 37 * context_save_arch() is required not to create its own stack frame. See the 40 38 * generic context.h for explanation. 41 39 */ 42 context_save_arch: 40 FUNCTION_BEGIN(context_save_arch) 43 41 # 44 42 # Force all our active register windows to memory so that we can find … … 67 65 retl 68 66 mov 1, %o0 ! context_save_arch returns 1 67 FUNCTION_END(context_save_arch) 69 68 70 context_restore_arch: 69 FUNCTION_BEGIN(context_restore_arch) 71 70 # 72 71 # Forget all previous windows, they are not going to be needed again. … … 106 105 retl 107 106 xor %o0, %o0, %o0 ! context_restore_arch returns 0 107 FUNCTION_END(context_restore_arch) -
kernel/arch/sparc64/src/debug/stacktrace_asm.S
r6adb775f r32573ff 27 27 # 28 28 29 #include <abi/asmtool.h> 29 30 #include <arch/stack.h> 30 31 31 32 .text 32 33 33 .global frame_pointer_get 34 .global program_counter_get 35 .global alloc_window_and_flush 36 37 frame_pointer_get: 34 FUNCTION_BEGIN(frame_pointer_get) 38 35 # Add the stack bias to %sp to get the actual address. 39 36 retl 40 37 add %sp, STACK_BIAS, %o0 38 FUNCTION_END(frame_pointer_get) 41 39 42 program_counter_get: 40 FUNCTION_BEGIN(program_counter_get) 43 41 retl 44 42 mov %o7, %o0 43 FUNCTION_END(program_counter_get) 45 44 46 alloc_window_and_flush: 45 FUNCTION_BEGIN(alloc_window_and_flush) 47 46 save %sp, -(STACK_WINDOW_SAVE_AREA_SIZE+STACK_ARG_SAVE_AREA_SIZE), %sp 48 47 # Flush all other windows to memory so that we can read their contents. … … 50 49 ret 51 50 restore 51 FUNCTION_END(alloc_window_and_flush) 52 52 -
kernel/arch/sparc64/src/dummy.S
r6adb775f r32573ff 27 27 # 28 28 29 #include <abi/asmtool.h> 30 29 31 .text 30 32 31 .global calibrate_delay_loop 32 .global asm_delay_loop 33 .global cpu_sleep34 .global dummy 33 FUNCTION_BEGIN(cpu_sleep) 34 retl 35 nop 36 FUNCTION_END(cpu_sleep) 35 37 36 calibrate_delay_loop: 37 asm_delay_loop: 38 cpu_sleep: 38 FUNCTION_BEGIN(cpu_halt) 39 ba %xcc, cpu_halt 40 nop 41 FUNCTION_END(cpu_halt) 39 42 40 dummy:41 br.ret.sptk.many b042 -
kernel/arch/sparc64/src/sun4u/asm.S
r6adb775f r32573ff 27 27 # 28 28 29 #include <abi/asmtool.h> 29 30 #include <arch/arch.h> 30 31 #include <arch/stack.h> … … 55 56 .endm 56 57 57 .global write_to_ag_g6 58 write_to_ag_g6: 58 FUNCTION_BEGIN(write_to_ag_g6) 59 59 WRITE_ALTERNATE_REGISTER %g6, PSTATE_AG_BIT 60 FUNCTION_END(write_to_ag_g6) 60 61 61 .global write_to_ag_g7 62 write_to_ag_g7: 62 FUNCTION_BEGIN(write_to_ag_g7) 63 63 WRITE_ALTERNATE_REGISTER %g7, PSTATE_AG_BIT 64 FUNCTION_END(write_to_ag_g7) 64 65 65 .global write_to_ig_g6 66 write_to_ig_g6: 66 FUNCTION_BEGIN(write_to_ig_g6) 67 67 WRITE_ALTERNATE_REGISTER %g6, PSTATE_IG_BIT 68 FUNCTION_END(write_to_ig_g6) 68 69 69 .global read_from_ag_g6 70 read_from_ag_g6: 70 FUNCTION_BEGIN(read_from_ag_g6) 71 71 READ_ALTERNATE_REGISTER %g6, PSTATE_AG_BIT 72 FUNCTION_END(read_from_ag_g6) 72 73 73 .global read_from_ag_g7 74 read_from_ag_g7: 74 FUNCTION_BEGIN(read_from_ag_g7) 75 75 READ_ALTERNATE_REGISTER %g7, PSTATE_AG_BIT 76 FUNCTION_END(read_from_ag_g7) 76 77 77 78 /** Switch to userspace. … … 81 82 * %o2 Userspace address of uarg structure. 82 83 */ 83 .global switch_to_userspace 84 switch_to_userspace: 84 FUNCTION_BEGIN(switch_to_userspace) 85 85 save %o1, -(STACK_WINDOW_SAVE_AREA_SIZE + STACK_ARG_SAVE_AREA_SIZE), %sp 86 86 flushw … … 119 119 120 120 done ! jump to userspace 121 FUNCTION_END(switch_to_userspace) 121 122 -
kernel/arch/sparc64/src/sun4u/start.S
r6adb775f r32573ff 27 27 # 28 28 29 #include <abi/asmtool.h> 30 29 31 #include <arch/arch.h> 30 32 #include <arch/cpu.h> … … 76 78 */ 77 79 78 .global kernel_image_start 79 kernel_image_start: 80 SYMBOL(kernel_image_start) 80 81 mov BSP_FLAG, %l0 81 82 and %o0, %l0, %l7 ! l7 <= bootstrap processor? … … 396 397 397 398 .align 8 398 .global physmem_base ! copy of the physical memory base address 399 physmem_base: 399 SYMBOL(physmem_base) ! copy of the physical memory base address 400 400 .quad 0 401 401 … … 405 405 * are meant to stay together, aligned on a 32B boundary. 406 406 */ 407 .global fast_data_access_mmu_miss_data_hi408 .global end_of_identity409 .global kernel_8k_tlb_data_template410 .global tlb_tag_access_context_mask411 407 412 408 .align 32 … … 414 410 * This label is used by the fast_data_access_MMU_miss trap handler. 415 411 */ 416 fast_data_access_mmu_miss_data_hi: 412 SYMBOL(fast_data_access_mmu_miss_data_hi) 417 413 /* 418 414 * This variable is used by the fast_data_access_MMU_miss trap handler. … … 420 416 * memory. 421 417 */ 422 end_of_identity: 418 SYMBOL(end_of_identity) 423 419 .quad -1 424 420 /* … … 427 423 * physical memory. 428 424 */ 429 kernel_8k_tlb_data_template: 425 SYMBOL(kernel_8k_tlb_data_template) 430 426 #ifdef CONFIG_VIRT_IDX_DCACHE 431 427 .quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | \ … … 440 436 * It allows us to save one precious instruction slot of this handler. 441 437 */ 442 tlb_tag_access_context_mask: 438 SYMBOL(tlb_tag_access_context_mask) 443 439 .quad TLB_TAG_ACCESS_CONTEXT_MASK 444 440 -
kernel/arch/sparc64/src/sun4v/asm.S
r6adb775f r32573ff 27 27 # 28 28 29 #include <abi/asmtool.h> 29 30 #include <arch/mm/mmu.h> 30 31 #include <arch/regdef.h> … … 39 40 * %o2 Userspace address of uarg structure. 40 41 */ 41 .global switch_to_userspace 42 switch_to_userspace: 42 FUNCTION_BEGIN(switch_to_userspace) 43 43 save %o1, -(STACK_WINDOW_SAVE_AREA_SIZE + STACK_ARG_SAVE_AREA_SIZE), %sp 44 44 flushw … … 75 75 wrpr %g0, WSTATE_OTHER(0) | WSTATE_NORMAL(1), %wstate 76 76 done ! jump to userspace 77 FUNCTION_END(switch_to_userspace) -
kernel/arch/sparc64/src/sun4v/start.S
r6adb775f r32573ff 28 28 # 29 29 30 #include <abi/asmtool.h> 30 31 #include <arch/arch.h> 31 32 #include <arch/stack.h> … … 106 107 * 107 108 */ 108 .global kernel_image_start 109 kernel_image_start: 109 SYMBOL(kernel_image_start) 110 110 mov BSP_FLAG, %l0 111 111 and %o0, %l0, %l7 ! l7 <= bootstrap processor? … … 310 310 311 311 .align 8 312 .global temp_cpu_mondo_handler 313 temp_cpu_mondo_handler: 312 SYMBOL(temp_cpu_mondo_handler) 314 313 315 314 set 0x3c, %o0 … … 341 340 342 341 .align 8 343 .global physmem_base ! copy of the physical memory base address 344 physmem_base: 342 SYMBOL(physmem_base) ! copy of the physical memory base address 345 343 .quad 0 346 344 … … 350 348 * memory. 351 349 */ 352 .global end_of_identity 353 end_of_identity: 350 SYMBOL(end_of_identity) 354 351 .quad -1 355 352 356 .global kernel_8k_tlb_data_template 357 kernel_8k_tlb_data_template: 353 SYMBOL(kernel_8k_tlb_data_template) 358 354 .quad 0 359 355 360 356 /* MMU fault status areas for all CPUs */ 361 357 .align MMU_FSA_ALIGNMENT 362 .global mmu_fsas 363 mmu_fsas: 358 SYMBOL(mmu_fsas) 364 359 .space (MMU_FSA_SIZE * MAX_NUM_STRANDS) -
kernel/arch/sparc64/src/trap/sun4u/trap_table.S
r6adb775f r32573ff 37 37 .text 38 38 39 #include <abi/asmtool.h> 39 40 #include <arch/trap/trap_table.h> 40 41 #include <arch/trap/regwin.h> … … 55 56 */ 56 57 .align TABLE_SIZE 57 .global trap_table 58 trap_table: 58 SYMBOL(trap_table) 59 59 60 60 /* TT = 0x08, TL = 0, instruction_access_exception */ 61 61 .org trap_table + TT_INSTRUCTION_ACCESS_EXCEPTION*ENTRY_SIZE 62 .global instruction_access_exception_tl0 63 instruction_access_exception_tl0: 62 SYMBOL(instruction_access_exception_tl0) 64 63 wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate 65 64 mov TT_INSTRUCTION_ACCESS_EXCEPTION, %g2 … … 69 68 /* TT = 0x0a, TL = 0, instruction_access_error */ 70 69 .org trap_table + TT_INSTRUCTION_ACCESS_ERROR*ENTRY_SIZE 71 .global instruction_access_error_tl0 72 instruction_access_error_tl0: 70 SYMBOL(instruction_access_error_tl0) 73 71 mov TT_INSTRUCTION_ACCESS_ERROR, %g2 74 72 clr %g5 … … 77 75 /* TT = 0x10, TL = 0, illegal_instruction */ 78 76 .org trap_table + TT_ILLEGAL_INSTRUCTION*ENTRY_SIZE 79 .global illegal_instruction_tl0 80 illegal_instruction_tl0: 77 SYMBOL(illegal_instruction_tl0) 81 78 mov TT_ILLEGAL_INSTRUCTION, %g2 82 79 clr %g5 … … 85 82 /* TT = 0x11, TL = 0, privileged_opcode */ 86 83 .org trap_table + TT_PRIVILEGED_OPCODE*ENTRY_SIZE 87 .global privileged_opcode_tl0 88 privileged_opcode_tl0: 84 SYMBOL(privileged_opcode_tl0) 89 85 mov TT_PRIVILEGED_OPCODE, %g2 90 86 clr %g5 … … 93 89 /* TT = 0x12, TL = 0, unimplemented_LDD */ 94 90 .org trap_table + TT_UNIMPLEMENTED_LDD*ENTRY_SIZE 95 .global unimplemented_LDD_tl0 96 unimplemented_LDD_tl0: 91 SYMBOL(unimplemented_LDD_tl0) 97 92 mov TT_UNIMPLEMENTED_LDD, %g2 98 93 clr %g5 … … 101 96 /* TT = 0x13, TL = 0, unimplemented_STD */ 102 97 .org trap_table + TT_UNIMPLEMENTED_STD*ENTRY_SIZE 103 .global unimplemented_STD_tl0 104 unimplemented_STD_tl0: 98 SYMBOL(unimplemented_STD_tl0) 105 99 mov TT_UNIMPLEMENTED_STD, %g2 106 100 clr %g5 … … 109 103 /* TT = 0x20, TL = 0, fb_disabled handler */ 110 104 .org trap_table + TT_FP_DISABLED*ENTRY_SIZE 111 .global fb_disabled_tl0 112 fp_disabled_tl0: 105 SYMBOL(fp_disabled_tl0) 113 106 mov TT_FP_DISABLED, %g2 114 107 clr %g5 … … 117 110 /* TT = 0x21, TL = 0, fb_exception_ieee_754 handler */ 118 111 .org trap_table + TT_FP_EXCEPTION_IEEE_754*ENTRY_SIZE 119 .global fb_exception_ieee_754_tl0 120 fp_exception_ieee_754_tl0: 112 SYMBOL(fp_exception_ieee_754_tl0) 121 113 mov TT_FP_EXCEPTION_IEEE_754, %g2 122 114 clr %g5 … … 125 117 /* TT = 0x22, TL = 0, fb_exception_other handler */ 126 118 .org trap_table + TT_FP_EXCEPTION_OTHER*ENTRY_SIZE 127 .global fb_exception_other_tl0 128 fp_exception_other_tl0: 119 SYMBOL(fp_exception_other_tl0) 129 120 mov TT_FP_EXCEPTION_OTHER, %g2 130 121 clr %g5 … … 133 124 /* TT = 0x23, TL = 0, tag_overflow */ 134 125 .org trap_table + TT_TAG_OVERFLOW*ENTRY_SIZE 135 .global tag_overflow_tl0 136 tag_overflow_tl0: 126 SYMBOL(tag_overflow_tl0) 137 127 mov TT_TAG_OVERFLOW, %g2 138 128 clr %g5 … … 141 131 /* TT = 0x24, TL = 0, clean_window handler */ 142 132 .org trap_table + TT_CLEAN_WINDOW*ENTRY_SIZE 143 .global clean_window_tl0 144 clean_window_tl0: 133 SYMBOL(clean_window_tl0) 145 134 CLEAN_WINDOW_HANDLER 146 135 147 136 /* TT = 0x28, TL = 0, division_by_zero */ 148 137 .org trap_table + TT_DIVISION_BY_ZERO*ENTRY_SIZE 149 .global division_by_zero_tl0 150 division_by_zero_tl0: 138 SYMBOL(division_by_zero_tl0) 151 139 mov TT_DIVISION_BY_ZERO, %g2 152 140 clr %g5 … … 155 143 /* TT = 0x30, TL = 0, data_access_exception */ 156 144 .org trap_table + TT_DATA_ACCESS_EXCEPTION*ENTRY_SIZE 157 .global data_access_exception_tl0 158 data_access_exception_tl0: 145 SYMBOL(data_access_exception_tl0) 159 146 wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate 160 147 mov TT_DATA_ACCESS_EXCEPTION, %g2 … … 164 151 /* TT = 0x32, TL = 0, data_access_error */ 165 152 .org trap_table + TT_DATA_ACCESS_ERROR*ENTRY_SIZE 166 .global data_access_error_tl0 167 data_access_error_tl0: 153 SYMBOL(data_access_error_tl0) 168 154 mov TT_DATA_ACCESS_ERROR, %g2 169 155 clr %g5 … … 172 158 /* TT = 0x34, TL = 0, mem_address_not_aligned */ 173 159 .org trap_table + TT_MEM_ADDRESS_NOT_ALIGNED*ENTRY_SIZE 174 .global mem_address_not_aligned_tl0 175 mem_address_not_aligned_tl0: 160 SYMBOL(mem_address_not_aligned_tl0) 176 161 mov TT_MEM_ADDRESS_NOT_ALIGNED, %g2 177 162 clr %g5 … … 180 165 /* TT = 0x35, TL = 0, LDDF_mem_address_not_aligned */ 181 166 .org trap_table + TT_LDDF_MEM_ADDRESS_NOT_ALIGNED*ENTRY_SIZE 182 .global LDDF_mem_address_not_aligned_tl0 183 LDDF_mem_address_not_aligned_tl0: 167 SYMBOL(LDDF_mem_address_not_aligned_tl0) 184 168 mov TT_LDDF_MEM_ADDRESS_NOT_ALIGNED, %g2 185 169 clr %g5 … … 188 172 /* TT = 0x36, TL = 0, STDF_mem_address_not_aligned */ 189 173 .org trap_table + TT_STDF_MEM_ADDRESS_NOT_ALIGNED*ENTRY_SIZE 190 .global STDF_mem_address_not_aligned_tl0 191 STDF_mem_address_not_aligned_tl0: 174 SYMBOL(STDF_mem_address_not_aligned_tl0) 192 175 mov TT_STDF_MEM_ADDRESS_NOT_ALIGNED, %g2 193 176 clr %g5 … … 196 179 /* TT = 0x37, TL = 0, privileged_action */ 197 180 .org trap_table + TT_PRIVILEGED_ACTION*ENTRY_SIZE 198 .global privileged_action_tl0 199 privileged_action_tl0: 181 SYMBOL(privileged_action_tl0) 200 182 mov TT_PRIVILEGED_ACTION, %g2 201 183 clr %g5 … … 204 186 /* TT = 0x38, TL = 0, LDQF_mem_address_not_aligned */ 205 187 .org trap_table + TT_LDQF_MEM_ADDRESS_NOT_ALIGNED*ENTRY_SIZE 206 .global LDQF_mem_address_not_aligned_tl0 207 LDQF_mem_address_not_aligned_tl0: 188 SYMBOL(LDQF_mem_address_not_aligned_tl0) 208 189 mov TT_LDQF_MEM_ADDRESS_NOT_ALIGNED, %g2 209 190 clr %g5 … … 212 193 /* TT = 0x39, TL = 0, STQF_mem_address_not_aligned */ 213 194 .org trap_table + TT_STQF_MEM_ADDRESS_NOT_ALIGNED*ENTRY_SIZE 214 .global STQF_mem_address_not_aligned_tl0 215 STQF_mem_address_not_aligned_tl0: 195 SYMBOL(STQF_mem_address_not_aligned_tl0) 216 196 mov TT_STQF_MEM_ADDRESS_NOT_ALIGNED, %g2 217 197 clr %g5 … … 220 200 /* TT = 0x41, TL = 0, interrupt_level_1 handler */ 221 201 .org trap_table + TT_INTERRUPT_LEVEL_1*ENTRY_SIZE 222 .global interrupt_level_1_handler_tl0 223 interrupt_level_1_handler_tl0: 202 SYMBOL(interrupt_level_1_handler_tl0) 224 203 mov TT_INTERRUPT_LEVEL_1, %g2 225 204 clr %g5 … … 228 207 /* TT = 0x42, TL = 0, interrupt_level_2 handler */ 229 208 .org trap_table + TT_INTERRUPT_LEVEL_2*ENTRY_SIZE 230 .global interrupt_level_2_handler_tl0 231 interrupt_level_2_handler_tl0: 209 SYMBOL(interrupt_level_2_handler_tl0) 232 210 mov TT_INTERRUPT_LEVEL_2, %g2 233 211 clr %g5 … … 236 214 /* TT = 0x43, TL = 0, interrupt_level_3 handler */ 237 215 .org trap_table + TT_INTERRUPT_LEVEL_3*ENTRY_SIZE 238 .global interrupt_level_3_handler_tl0 239 interrupt_level_3_handler_tl0: 216 SYMBOL(interrupt_level_3_handler_tl0) 240 217 mov TT_INTERRUPT_LEVEL_3, %g2 241 218 clr %g5 … … 244 221 /* TT = 0x44, TL = 0, interrupt_level_4 handler */ 245 222 .org trap_table + TT_INTERRUPT_LEVEL_4*ENTRY_SIZE 246 .global interrupt_level_4_handler_tl0 247 interrupt_level_4_handler_tl0: 223 SYMBOL(interrupt_level_4_handler_tl0) 248 224 mov TT_INTERRUPT_LEVEL_4, %g2 249 225 clr %g5 … … 252 228 /* TT = 0x45, TL = 0, interrupt_level_5 handler */ 253 229 .org trap_table + TT_INTERRUPT_LEVEL_5*ENTRY_SIZE 254 .global interrupt_level_5_handler_tl0 255 interrupt_level_5_handler_tl0: 230 SYMBOL(interrupt_level_5_handler_tl0) 256 231 mov TT_INTERRUPT_LEVEL_5, %g2 257 232 clr %g5 … … 260 235 /* TT = 0x46, TL = 0, interrupt_level_6 handler */ 261 236 .org trap_table + TT_INTERRUPT_LEVEL_6*ENTRY_SIZE 262 .global interrupt_level_6_handler_tl0 263 interrupt_level_6_handler_tl0: 237 SYMBOL(interrupt_level_6_handler_tl0) 264 238 mov TT_INTERRUPT_LEVEL_6, %g2 265 239 clr %g5 … … 268 242 /* TT = 0x47, TL = 0, interrupt_level_7 handler */ 269 243 .org trap_table + TT_INTERRUPT_LEVEL_7*ENTRY_SIZE 270 .global interrupt_level_7_handler_tl0 271 interrupt_level_7_handler_tl0: 244 SYMBOL(interrupt_level_7_handler_tl0) 272 245 mov TT_INTERRUPT_LEVEL_7, %g2 273 246 clr %g5 … … 276 249 /* TT = 0x48, TL = 0, interrupt_level_8 handler */ 277 250 .org trap_table + TT_INTERRUPT_LEVEL_8*ENTRY_SIZE 278 .global interrupt_level_8_handler_tl0 279 interrupt_level_8_handler_tl0: 251 SYMBOL(interrupt_level_8_handler_tl0) 280 252 mov TT_INTERRUPT_LEVEL_8, %g2 281 253 clr %g5 … … 284 256 /* TT = 0x49, TL = 0, interrupt_level_9 handler */ 285 257 .org trap_table + TT_INTERRUPT_LEVEL_9*ENTRY_SIZE 286 .global interrupt_level_9_handler_tl0 287 interrupt_level_9_handler_tl0: 258 SYMBOL(interrupt_level_9_handler_tl0) 288 259 mov TT_INTERRUPT_LEVEL_9, %g2 289 260 clr %g5 … … 292 263 /* TT = 0x4a, TL = 0, interrupt_level_10 handler */ 293 264 .org trap_table + TT_INTERRUPT_LEVEL_10*ENTRY_SIZE 294 .global interrupt_level_10_handler_tl0 295 interrupt_level_10_handler_tl0: 265 SYMBOL(interrupt_level_10_handler_tl0) 296 266 mov TT_INTERRUPT_LEVEL_10, %g2 297 267 clr %g5 … … 300 270 /* TT = 0x4b, TL = 0, interrupt_level_11 handler */ 301 271 .org trap_table + TT_INTERRUPT_LEVEL_11*ENTRY_SIZE 302 .global interrupt_level_11_handler_tl0 303 interrupt_level_11_handler_tl0: 272 SYMBOL(interrupt_level_11_handler_tl0) 304 273 mov TT_INTERRUPT_LEVEL_11, %g2 305 274 clr %g5 … … 308 277 /* TT = 0x4c, TL = 0, interrupt_level_12 handler */ 309 278 .org trap_table + TT_INTERRUPT_LEVEL_12*ENTRY_SIZE 310 .global interrupt_level_12_handler_tl0 311 interrupt_level_12_handler_tl0: 279 SYMBOL(interrupt_level_12_handler_tl0) 312 280 mov TT_INTERRUPT_LEVEL_12, %g2 313 281 clr %g5 … … 316 284 /* TT = 0x4d, TL = 0, interrupt_level_13 handler */ 317 285 .org trap_table + TT_INTERRUPT_LEVEL_13*ENTRY_SIZE 318 .global interrupt_level_13_handler_tl0 319 interrupt_level_13_handler_tl0: 286 SYMBOL(interrupt_level_13_handler_tl0) 320 287 mov TT_INTERRUPT_LEVEL_13, %g2 321 288 clr %g5 … … 324 291 /* TT = 0x4e, TL = 0, interrupt_level_14 handler */ 325 292 .org trap_table + TT_INTERRUPT_LEVEL_14*ENTRY_SIZE 326 .global interrupt_level_14_handler_tl0 327 interrupt_level_14_handler_tl0: 293 SYMBOL(interrupt_level_14_handler_tl0) 328 294 mov TT_INTERRUPT_LEVEL_14, %g2 329 295 clr %g5 … … 332 298 /* TT = 0x4f, TL = 0, interrupt_level_15 handler */ 333 299 .org trap_table + TT_INTERRUPT_LEVEL_15*ENTRY_SIZE 334 .global interrupt_level_15_handler_tl0 335 interrupt_level_15_handler_tl0: 300 SYMBOL(interrupt_level_15_handler_tl0) 336 301 mov TT_INTERRUPT_LEVEL_15, %g2 337 302 clr %g5 … … 340 305 /* TT = 0x60, TL = 0, interrupt_vector_trap handler */ 341 306 .org trap_table + TT_INTERRUPT_VECTOR_TRAP*ENTRY_SIZE 342 .global interrupt_vector_trap_handler_tl0 343 interrupt_vector_trap_handler_tl0: 307 SYMBOL(interrupt_vector_trap_handler_tl0) 344 308 mov TT_INTERRUPT_VECTOR_TRAP, %g2 345 309 clr %g5 … … 348 312 /* TT = 0x64, TL = 0, fast_instruction_access_MMU_miss */ 349 313 .org trap_table + TT_FAST_INSTRUCTION_ACCESS_MMU_MISS*ENTRY_SIZE 350 .global fast_instruction_access_mmu_miss_handler_tl0 351 fast_instruction_access_mmu_miss_handler_tl0: 314 SYMBOL(fast_instruction_access_mmu_miss_handler_tl0) 352 315 FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER 353 316 354 317 /* TT = 0x68, TL = 0, fast_data_access_MMU_miss */ 355 318 .org trap_table + TT_FAST_DATA_ACCESS_MMU_MISS*ENTRY_SIZE 356 .global fast_data_access_mmu_miss_handler_tl0 357 fast_data_access_mmu_miss_handler_tl0: 319 SYMBOL(fast_data_access_mmu_miss_handler_tl0) 358 320 FAST_DATA_ACCESS_MMU_MISS_HANDLER 0 359 321 360 322 /* TT = 0x6c, TL = 0, fast_data_access_protection */ 361 323 .org trap_table + TT_FAST_DATA_ACCESS_PROTECTION*ENTRY_SIZE 362 .global fast_data_access_protection_handler_tl0 363 fast_data_access_protection_handler_tl0: 324 SYMBOL(fast_data_access_protection_handler_tl0) 364 325 FAST_DATA_ACCESS_PROTECTION_HANDLER 0 365 326 366 327 /* TT = 0x80, TL = 0, spill_0_normal handler */ 367 328 .org trap_table + TT_SPILL_0_NORMAL*ENTRY_SIZE 368 .global spill_0_normal_tl0 369 spill_0_normal_tl0: 329 SYMBOL(spill_0_normal_tl0) 370 330 SPILL_NORMAL_HANDLER_KERNEL 371 331 372 332 /* TT = 0x84, TL = 0, spill_1_normal handler */ 373 333 .org trap_table + TT_SPILL_1_NORMAL*ENTRY_SIZE 374 .global spill_1_normal_tl0 375 spill_1_normal_tl0: 334 SYMBOL(spill_1_normal_tl0) 376 335 SPILL_NORMAL_HANDLER_USERSPACE 377 336 378 337 /* TT = 0x88, TL = 0, spill_2_normal handler */ 379 338 .org trap_table + TT_SPILL_2_NORMAL*ENTRY_SIZE 380 .global spill_2_normal_tl0 381 spill_2_normal_tl0: 339 SYMBOL(spill_2_normal_tl0) 382 340 SPILL_TO_USPACE_WINDOW_BUFFER 383 341 384 342 /* TT = 0xa0, TL = 0, spill_0_other handler */ 385 343 .org trap_table + TT_SPILL_0_OTHER*ENTRY_SIZE 386 .global spill_0_other_tl0 387 spill_0_other_tl0: 344 SYMBOL(spill_0_other_tl0) 388 345 SPILL_TO_USPACE_WINDOW_BUFFER 389 346 390 347 /* TT = 0xc0, TL = 0, fill_0_normal handler */ 391 348 .org trap_table + TT_FILL_0_NORMAL*ENTRY_SIZE 392 .global fill_0_normal_tl0 393 fill_0_normal_tl0: 349 SYMBOL(fill_0_normal_tl0) 394 350 FILL_NORMAL_HANDLER_KERNEL 395 351 396 352 /* TT = 0xc4, TL = 0, fill_1_normal handler */ 397 353 .org trap_table + TT_FILL_1_NORMAL*ENTRY_SIZE 398 .global fill_1_normal_tl0 399 fill_1_normal_tl0: 354 SYMBOL(fill_1_normal_tl0) 400 355 FILL_NORMAL_HANDLER_USERSPACE 401 356 … … 410 365 127 411 366 .org trap_table + (TT_TRAP_INSTRUCTION_0+\cur)*ENTRY_SIZE 412 .global trap_instruction_\cur\()_tl0 413 trap_instruction_\cur\()_tl0: 367 SYMBOL(trap_instruction_\cur\()_tl0) 414 368 mov \cur, %g2 415 369 ba %xcc, trap_instruction_handler … … 423 377 /* TT = 0x08, TL > 0, instruction_access_exception */ 424 378 .org trap_table + (TT_INSTRUCTION_ACCESS_EXCEPTION+512)*ENTRY_SIZE 425 .global instruction_access_exception_tl1 426 instruction_access_exception_tl1: 379 SYMBOL(instruction_access_exception_tl1) 427 380 wrpr %g0, 1, %tl 428 381 wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate … … 433 386 /* TT = 0x0a, TL > 0, instruction_access_error */ 434 387 .org trap_table + (TT_INSTRUCTION_ACCESS_ERROR+512)*ENTRY_SIZE 435 .global instruction_access_error_tl1 436 instruction_access_error_tl1: 388 SYMBOL(instruction_access_error_tl1) 437 389 wrpr %g0, 1, %tl 438 390 mov TT_INSTRUCTION_ACCESS_ERROR, %g2 … … 442 394 /* TT = 0x10, TL > 0, illegal_instruction */ 443 395 .org trap_table + (TT_ILLEGAL_INSTRUCTION+512)*ENTRY_SIZE 444 .global illegal_instruction_tl1 445 illegal_instruction_tl1: 396 SYMBOL(illegal_instruction_tl1) 446 397 wrpr %g0, 1, %tl 447 398 mov TT_ILLEGAL_INSTRUCTION, %g2 … … 451 402 /* TT = 0x24, TL > 0, clean_window handler */ 452 403 .org trap_table + (TT_CLEAN_WINDOW+512)*ENTRY_SIZE 453 .global clean_window_tl1 454 clean_window_tl1: 404 SYMBOL(clean_window_tl1) 455 405 CLEAN_WINDOW_HANDLER 456 406 457 407 /* TT = 0x28, TL > 0, division_by_zero */ 458 408 .org trap_table + (TT_DIVISION_BY_ZERO+512)*ENTRY_SIZE 459 .global division_by_zero_tl1 460 division_by_zero_tl1: 409 SYMBOL(division_by_zero_tl1) 461 410 wrpr %g0, 1, %tl 462 411 mov TT_DIVISION_BY_ZERO, %g2 … … 466 415 /* TT = 0x30, TL > 0, data_access_exception */ 467 416 .org trap_table + (TT_DATA_ACCESS_EXCEPTION+512)*ENTRY_SIZE 468 .global data_access_exception_tl1 469 data_access_exception_tl1: 417 SYMBOL(data_access_exception_tl1) 470 418 wrpr %g0, 1, %tl 471 419 wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate … … 476 424 /* TT = 0x32, TL > 0, data_access_error */ 477 425 .org trap_table + (TT_DATA_ACCESS_ERROR+512)*ENTRY_SIZE 478 .global data_access_error_tl1 479 data_access_error_tl1: 426 SYMBOL(data_access_error_tl1) 480 427 wrpr %g0, 1, %tl 481 428 mov TT_DATA_ACCESS_ERROR, %g2 … … 485 432 /* TT = 0x34, TL > 0, mem_address_not_aligned */ 486 433 .org trap_table + (TT_MEM_ADDRESS_NOT_ALIGNED+512)*ENTRY_SIZE 487 .global mem_address_not_aligned_tl1 488 mem_address_not_aligned_tl1: 434 SYMBOL(mem_address_not_aligned_tl1) 489 435 wrpr %g0, 1, %tl 490 436 mov TT_MEM_ADDRESS_NOT_ALIGNED, %g2 … … 494 440 /* TT = 0x68, TL > 0, fast_data_access_MMU_miss */ 495 441 .org trap_table + (TT_FAST_DATA_ACCESS_MMU_MISS+512)*ENTRY_SIZE 496 .global fast_data_access_mmu_miss_handler_tl1 497 fast_data_access_mmu_miss_handler_tl1: 442 SYMBOL(fast_data_access_mmu_miss_handler_tl1) 498 443 FAST_DATA_ACCESS_MMU_MISS_HANDLER 1 499 444 500 445 /* TT = 0x6c, TL > 0, fast_data_access_protection */ 501 446 .org trap_table + (TT_FAST_DATA_ACCESS_PROTECTION+512)*ENTRY_SIZE 502 .global fast_data_access_protection_handler_tl1 503 fast_data_access_protection_handler_tl1: 447 SYMBOL(fast_data_access_protection_handler_tl1) 504 448 FAST_DATA_ACCESS_PROTECTION_HANDLER 1 505 449 506 450 /* TT = 0x80, TL > 0, spill_0_normal handler */ 507 451 .org trap_table + (TT_SPILL_0_NORMAL+512)*ENTRY_SIZE 508 .global spill_0_normal_tl1 509 spill_0_normal_tl1: 452 SYMBOL(spill_0_normal_tl1) 510 453 SPILL_NORMAL_HANDLER_KERNEL 511 454 512 455 /* TT = 0x88, TL > 0, spill_2_normal handler */ 513 456 .org trap_table + (TT_SPILL_2_NORMAL+512)*ENTRY_SIZE 514 .global spill_2_normal_tl1 515 spill_2_normal_tl1: 457 SYMBOL(spill_2_normal_tl1) 516 458 SPILL_TO_USPACE_WINDOW_BUFFER 517 459 518 460 /* TT = 0xa0, TL > 0, spill_0_other handler */ 519 461 .org trap_table + (TT_SPILL_0_OTHER+512)*ENTRY_SIZE 520 .global spill_0_other_tl1 521 spill_0_other_tl1: 462 SYMBOL(spill_0_other_tl1) 522 463 SPILL_TO_USPACE_WINDOW_BUFFER 523 464 524 465 /* TT = 0xc0, TL > 0, fill_0_normal handler */ 525 466 .org trap_table + (TT_FILL_0_NORMAL+512)*ENTRY_SIZE 526 .global fill_0_normal_tl1 527 fill_0_normal_tl1: 467 SYMBOL(fill_0_normal_tl1) 528 468 FILL_NORMAL_HANDLER_KERNEL 529 469 … … 914 854 .endm 915 855 916 .global preemptible_handler 917 preemptible_handler: 856 SYMBOL(preemptible_handler) 918 857 PREEMPTIBLE_HANDLER_TEMPLATE 0 919 858 920 .global trap_instruction_handler 921 trap_instruction_handler: 859 SYMBOL(trap_instruction_handler) 922 860 PREEMPTIBLE_HANDLER_TEMPLATE 1 -
kernel/arch/sparc64/src/trap/sun4v/mmu.S
r6adb775f r32573ff 37 37 .text 38 38 39 #include <abi/asmtool.h> 39 40 #include <arch/trap/sun4v/mmu.h> 40 41 #include <arch/trap/trap_table.h> … … 48 49 * %g1 virtual address that has caused the miss 49 50 */ 50 .global install_identity_mapping 51 install_identity_mapping: 52 51 SYMBOL(install_identity_mapping) 53 52 /* output registers mustn't be clobbered during the hypercall, SAVE is too risky */ 54 53 mov %o0, %g3 -
kernel/arch/sparc64/src/trap/sun4v/trap_table.S
r6adb775f r32573ff 38 38 .text 39 39 40 #include <abi/asmtool.h> 40 41 #include <arch/trap/trap_table.h> 41 42 #include <arch/trap/regwin.h> … … 58 59 */ 59 60 .align TABLE_SIZE 60 .global trap_table 61 trap_table: 61 SYMBOL(trap_table) 62 62 63 63 /* TT = 0x08, TL = 0, instruction_access_exception */ 64 64 /* TT = 0x08, TL = 0, IAE_privilege_violation on UltraSPARC T2 */ 65 65 .org trap_table + TT_INSTRUCTION_ACCESS_EXCEPTION*ENTRY_SIZE 66 .global instruction_access_exception_tl0 67 instruction_access_exception_tl0: 66 SYMBOL(instruction_access_exception_tl0) 68 67 mov TT_INSTRUCTION_ACCESS_EXCEPTION, %g2 69 68 clr %g5 … … 72 71 /* TT = 0x09, TL = 0, instruction_access_mmu_miss */ 73 72 .org trap_table + TT_INSTRUCTION_ACCESS_MMU_MISS*ENTRY_SIZE 74 .global instruction_access_mmu_miss_handler_tl0 73 SYMBOL(instruction_access_mmu_miss_handler_tl0) 75 74 ba,a %xcc, fast_instruction_access_mmu_miss_handler_tl0 76 75 77 76 /* TT = 0x0a, TL = 0, instruction_access_error */ 78 77 .org trap_table + TT_INSTRUCTION_ACCESS_ERROR*ENTRY_SIZE 79 .global instruction_access_error_tl0 80 instruction_access_error_tl0: 78 SYMBOL(instruction_access_error_tl0) 81 79 mov TT_INSTRUCTION_ACCESS_ERROR, %g2 82 80 clr %g5 … … 85 83 /* TT = 0x0b, TL = 0, IAE_unauth_access */ 86 84 .org trap_table + TT_IAE_UNAUTH_ACCESS*ENTRY_SIZE 87 .global iae_unauth_access_tl0 88 iae_unauth_access_tl0: 85 SYMBOL(iae_unauth_access_tl0) 89 86 mov TT_IAE_UNAUTH_ACCESS, %g2 90 87 clr %g5 … … 93 90 /* TT = 0x0c, TL = 0, IAE_nfo_page */ 94 91 .org trap_table + TT_IAE_NFO_PAGE*ENTRY_SIZE 95 .global iae_nfo_page_tl0 96 iae_nfo_page_tl0: 92 SYMBOL(iae_nfo_page_tl0) 97 93 mov TT_IAE_NFO_PAGE, %g2 98 94 clr %g5 … … 101 97 /* TT = 0x10, TL = 0, illegal_instruction */ 102 98 .org trap_table + TT_ILLEGAL_INSTRUCTION*ENTRY_SIZE 103 .global illegal_instruction_tl0 104 illegal_instruction_tl0: 99 SYMBOL(illegal_instruction_tl0) 105 100 mov TT_ILLEGAL_INSTRUCTION, %g2 106 101 clr %g5 … … 109 104 /* TT = 0x11, TL = 0, privileged_opcode */ 110 105 .org trap_table + TT_PRIVILEGED_OPCODE*ENTRY_SIZE 111 .global privileged_opcode_tl0 112 privileged_opcode_tl0: 106 SYMBOL(privileged_opcode_tl0) 113 107 mov TT_PRIVILEGED_OPCODE, %g2 114 108 clr %g5 … … 117 111 /* TT = 0x12, TL = 0, unimplemented_LDD */ 118 112 .org trap_table + TT_UNIMPLEMENTED_LDD*ENTRY_SIZE 119 .global unimplemented_LDD_tl0 120 unimplemented_LDD_tl0: 113 SYMBOL(unimplemented_LDD_tl0) 121 114 mov TT_UNIMPLEMENTED_LDD, %g2 122 115 clr %g5 … … 125 118 /* TT = 0x13, TL = 0, unimplemented_STD */ 126 119 .org trap_table + TT_UNIMPLEMENTED_STD*ENTRY_SIZE 127 .global unimplemented_STD_tl0 128 unimplemented_STD_tl0: 120 SYMBOL(unimplemented_STD_tl0) 129 121 mov TT_UNIMPLEMENTED_STD, %g2 130 122 clr %g5 … … 133 125 /* TT = 0x14, TL = 0, DAE_invalid_asi */ 134 126 .org trap_table + TT_DAE_INVALID_ASI*ENTRY_SIZE 135 .global dae_invalid_asi_tl0 136 dae_invalid_asi_tl0: 127 SYMBOL(dae_invalid_asi_tl0) 137 128 mov TT_DAE_INVALID_ASI, %g2 138 129 clr %g5 … … 141 132 /* TT = 0x15, TL = 0, DAE_privilege_violation */ 142 133 .org trap_table + TT_DAE_PRIVILEGE_VIOLATION*ENTRY_SIZE 143 .global dae_privilege_violation_tl0 144 dae_privilege_violation_tl0: 134 SYMBOL(dae_privilege_violation_tl0) 145 135 mov TT_DAE_PRIVILEGE_VIOLATION, %g2 146 136 clr %g5 … … 149 139 /* TT = 0x16, TL = 0, DAE_nc_page */ 150 140 .org trap_table + TT_DAE_NC_PAGE*ENTRY_SIZE 151 .global dae_nc_page_tl0 152 dae_nc_page_tl0: 141 SYMBOL(dae_nc_page_tl0) 153 142 mov TT_DAE_NC_PAGE, %g2 154 143 clr %g5 … … 157 146 /* TT = 0x17, TL = 0, DAE_nfo_page */ 158 147 .org trap_table + TT_DAE_NFO_PAGE*ENTRY_SIZE 159 .global dae_nfo_page_tl0 160 dae_nfo_page_tl0: 148 SYMBOL(dae_nfo_page_tl0) 161 149 mov TT_DAE_NFO_PAGE, %g2 162 150 clr %g5 … … 165 153 /* TT = 0x20, TL = 0, fb_disabled handler */ 166 154 .org trap_table + TT_FP_DISABLED*ENTRY_SIZE 167 .global fb_disabled_tl0 168 fp_disabled_tl0: 155 SYMBOL(fp_disabled_tl0) 169 156 mov TT_FP_DISABLED, %g2 170 157 clr %g5 … … 173 160 /* TT = 0x21, TL = 0, fb_exception_ieee_754 handler */ 174 161 .org trap_table + TT_FP_EXCEPTION_IEEE_754*ENTRY_SIZE 175 .global fb_exception_ieee_754_tl0 176 fp_exception_ieee_754_tl0: 162 SYMBOL(fp_exception_ieee_754_tl0) 177 163 mov TT_FP_EXCEPTION_IEEE_754, %g2 178 164 clr %g5 … … 181 167 /* TT = 0x22, TL = 0, fb_exception_other handler */ 182 168 .org trap_table + TT_FP_EXCEPTION_OTHER*ENTRY_SIZE 183 .global fb_exception_other_tl0 184 fp_exception_other_tl0: 169 SYMBOL(fp_exception_other_tl) 185 170 mov TT_FP_EXCEPTION_OTHER, %g2 186 171 clr %g5 … … 189 174 /* TT = 0x23, TL = 0, tag_overflow */ 190 175 .org trap_table + TT_TAG_OVERFLOW*ENTRY_SIZE 191 .global tag_overflow_tl0 192 tag_overflow_tl0: 176 SYMBOL(tag_overflow_tl0) 193 177 mov TT_TAG_OVERFLOW, %g2 194 178 clr %g5 … … 197 181 /* TT = 0x24, TL = 0, clean_window handler */ 198 182 .org trap_table + TT_CLEAN_WINDOW*ENTRY_SIZE 199 .global clean_window_tl0 200 clean_window_tl0: 183 SYMBOL(clean_window_tl0) 201 184 CLEAN_WINDOW_HANDLER 202 185 203 186 /* TT = 0x28, TL = 0, division_by_zero */ 204 187 .org trap_table + TT_DIVISION_BY_ZERO*ENTRY_SIZE 205 .global division_by_zero_tl0 206 division_by_zero_tl0: 188 SYMBOL(division_by_zero_tl0) 207 189 mov TT_DIVISION_BY_ZERO, %g2 208 190 clr %g5 … … 212 194 /* TT = 0x30, TL = 0, DAE_side_effect_page for UltraPSARC T2 */ 213 195 .org trap_table + TT_DATA_ACCESS_EXCEPTION*ENTRY_SIZE 214 .global data_access_exception_tl0 215 data_access_exception_tl0: 196 SYMBOL(data_access_exception_tl0) 216 197 mov TT_DATA_ACCESS_EXCEPTION, %g2 217 198 clr %g5 … … 220 201 /* TT = 0x31, TL = 0, data_access_mmu_miss */ 221 202 .org trap_table + TT_DATA_ACCESS_MMU_MISS*ENTRY_SIZE 222 .global data_access_mmu_miss_tl0 223 data_access_mmu_miss_tl0: 203 SYMBOL(data_access_mmu_miss_tl0) 224 204 ba,a %xcc, fast_data_access_mmu_miss_handler_tl0 225 205 226 206 /* TT = 0x32, TL = 0, data_access_error */ 227 207 .org trap_table + TT_DATA_ACCESS_ERROR*ENTRY_SIZE 228 .global data_access_error_tl0 229 data_access_error_tl0: 208 SYMBOL(data_access_error_tl0) 230 209 mov TT_DATA_ACCESS_ERROR, %g2 231 210 clr %g5 … … 234 213 /* TT = 0x34, TL = 0, mem_address_not_aligned */ 235 214 .org trap_table + TT_MEM_ADDRESS_NOT_ALIGNED*ENTRY_SIZE 236 .global mem_address_not_aligned_tl0 237 mem_address_not_aligned_tl0: 215 SYMBOL(mem_address_not_aligned_tl0) 238 216 mov TT_MEM_ADDRESS_NOT_ALIGNED, %g2 239 217 clr %g5 … … 242 220 /* TT = 0x35, TL = 0, LDDF_mem_address_not_aligned */ 243 221 .org trap_table + TT_LDDF_MEM_ADDRESS_NOT_ALIGNED*ENTRY_SIZE 244 .global LDDF_mem_address_not_aligned_tl0 245 LDDF_mem_address_not_aligned_tl0: 222 SYMBOL(LDDF_mem_address_not_aligned_tl0) 246 223 mov TT_LDDF_MEM_ADDRESS_NOT_ALIGNED, %g2 247 224 clr %g5 … … 250 227 /* TT = 0x36, TL = 0, STDF_mem_address_not_aligned */ 251 228 .org trap_table + TT_STDF_MEM_ADDRESS_NOT_ALIGNED*ENTRY_SIZE 252 .global STDF_mem_address_not_aligned_tl0 253 STDF_mem_address_not_aligned_tl0: 229 SYMBOL(STDF_mem_address_not_aligned_tl0) 254 230 mov TT_STDF_MEM_ADDRESS_NOT_ALIGNED, %g2 255 231 clr %g5 … … 258 234 /* TT = 0x37, TL = 0, privileged_action */ 259 235 .org trap_table + TT_PRIVILEGED_ACTION*ENTRY_SIZE 260 .global privileged_action_tl0 261 privileged_action_tl0: 236 SYMBOL(privileged_action_tl0) 262 237 mov TT_PRIVILEGED_ACTION, %g2 263 238 clr %g5 … … 266 241 /* TT = 0x38, TL = 0, LDQF_mem_address_not_aligned */ 267 242 .org trap_table + TT_LDQF_MEM_ADDRESS_NOT_ALIGNED*ENTRY_SIZE 268 .global LDQF_mem_address_not_aligned_tl0 269 LDQF_mem_address_not_aligned_tl0: 243 SYMBOL(LDQF_mem_address_not_aligned_tl0) 270 244 mov TT_LDQF_MEM_ADDRESS_NOT_ALIGNED, %g2 271 245 clr %g5 … … 274 248 /* TT = 0x39, TL = 0, STQF_mem_address_not_aligned */ 275 249 .org trap_table + TT_STQF_MEM_ADDRESS_NOT_ALIGNED*ENTRY_SIZE 276 .global STQF_mem_address_not_aligned_tl0 277 STQF_mem_address_not_aligned_tl0: 250 SYMBOL(STQF_mem_address_not_aligned_tl0) 278 251 mov TT_STQF_MEM_ADDRESS_NOT_ALIGNED, %g2 279 252 clr %g5 … … 282 255 /* TT = 0x41, TL = 0, interrupt_level_1 handler */ 283 256 .org trap_table + TT_INTERRUPT_LEVEL_1*ENTRY_SIZE 284 .global interrupt_level_1_handler_tl0 285 interrupt_level_1_handler_tl0: 257 SYMBOL(interrupt_level_1_handler_tl0) 286 258 mov TT_INTERRUPT_LEVEL_1, %g2 287 259 clr %g5 … … 290 262 /* TT = 0x42, TL = 0, interrupt_level_2 handler */ 291 263 .org trap_table + TT_INTERRUPT_LEVEL_2*ENTRY_SIZE 292 .global interrupt_level_2_handler_tl0 293 interrupt_level_2_handler_tl0: 264 SYMBOL(interrupt_level_2_handler_tl0) 294 265 mov TT_INTERRUPT_LEVEL_2, %g2 295 266 clr %g5 … … 298 269 /* TT = 0x43, TL = 0, interrupt_level_3 handler */ 299 270 .org trap_table + TT_INTERRUPT_LEVEL_3*ENTRY_SIZE 300 .global interrupt_level_3_handler_tl0 301 interrupt_level_3_handler_tl0: 271 SYMBOL(interrupt_level_3_handler_tl0) 302 272 mov TT_INTERRUPT_LEVEL_3, %g2 303 273 clr %g5 … … 306 276 /* TT = 0x44, TL = 0, interrupt_level_4 handler */ 307 277 .org trap_table + TT_INTERRUPT_LEVEL_4*ENTRY_SIZE 308 .global interrupt_level_4_handler_tl0 309 interrupt_level_4_handler_tl0: 278 SYMBOL(interrupt_level_4_handler_tl0) 310 279 mov TT_INTERRUPT_LEVEL_4, %g2 311 280 clr %g5 … … 314 283 /* TT = 0x45, TL = 0, interrupt_level_5 handler */ 315 284 .org trap_table + TT_INTERRUPT_LEVEL_5*ENTRY_SIZE 316 .global interrupt_level_5_handler_tl0 317 interrupt_level_5_handler_tl0: 285 SYMBOL(interrupt_level_5_handler_tl0) 318 286 mov TT_INTERRUPT_LEVEL_5, %g2 319 287 clr %g5 … … 322 290 /* TT = 0x46, TL = 0, interrupt_level_6 handler */ 323 291 .org trap_table + TT_INTERRUPT_LEVEL_6*ENTRY_SIZE 324 .global interrupt_level_6_handler_tl0 325 interrupt_level_6_handler_tl0: 292 SYMBOL(interrupt_level_6_handler_tl0) 326 293 mov TT_INTERRUPT_LEVEL_6, %g2 327 294 clr %g5 … … 330 297 /* TT = 0x47, TL = 0, interrupt_level_7 handler */ 331 298 .org trap_table + TT_INTERRUPT_LEVEL_7*ENTRY_SIZE 332 .global interrupt_level_7_handler_tl0 333 interrupt_level_7_handler_tl0: 299 SYMBOL(interrupt_level_7_handler_tl0) 334 300 mov TT_INTERRUPT_LEVEL_7, %g2 335 301 clr %g5 … … 338 304 /* TT = 0x48, TL = 0, interrupt_level_8 handler */ 339 305 .org trap_table + TT_INTERRUPT_LEVEL_8*ENTRY_SIZE 340 .global interrupt_level_8_handler_tl0 341 interrupt_level_8_handler_tl0: 306 SYMBOL(interrupt_level_8_handler_tl0) 342 307 mov TT_INTERRUPT_LEVEL_8, %g2 343 308 clr %g5 … … 346 311 /* TT = 0x49, TL = 0, interrupt_level_9 handler */ 347 312 .org trap_table + TT_INTERRUPT_LEVEL_9*ENTRY_SIZE 348 .global interrupt_level_9_handler_tl0 349 interrupt_level_9_handler_tl0: 313 SYMBOL(interrupt_level_9_handler_tl0) 350 314 mov TT_INTERRUPT_LEVEL_9, %g2 351 315 clr %g5 … … 354 318 /* TT = 0x4a, TL = 0, interrupt_level_10 handler */ 355 319 .org trap_table + TT_INTERRUPT_LEVEL_10*ENTRY_SIZE 356 .global interrupt_level_10_handler_tl0 357 interrupt_level_10_handler_tl0: 320 SYMBOL(interrupt_level_10_handler_tl0) 358 321 mov TT_INTERRUPT_LEVEL_10, %g2 359 322 clr %g5 … … 362 325 /* TT = 0x4b, TL = 0, interrupt_level_11 handler */ 363 326 .org trap_table + TT_INTERRUPT_LEVEL_11*ENTRY_SIZE 364 .global interrupt_level_11_handler_tl0 365 interrupt_level_11_handler_tl0: 327 SYMBOL(interrupt_level_11_handler_tl0) 366 328 mov TT_INTERRUPT_LEVEL_11, %g2 367 329 clr %g5 … … 370 332 /* TT = 0x4c, TL = 0, interrupt_level_12 handler */ 371 333 .org trap_table + TT_INTERRUPT_LEVEL_12*ENTRY_SIZE 372 .global interrupt_level_12_handler_tl0 373 interrupt_level_12_handler_tl0: 334 SYMBOL(interrupt_level_12_handler_tl0) 374 335 mov TT_INTERRUPT_LEVEL_12, %g2 375 336 clr %g5 … … 378 339 /* TT = 0x4d, TL = 0, interrupt_level_13 handler */ 379 340 .org trap_table + TT_INTERRUPT_LEVEL_13*ENTRY_SIZE 380 .global interrupt_level_13_handler_tl0 381 interrupt_level_13_handler_tl0: 341 SYMBOL(interrupt_level_13_handler_tl0) 382 342 mov TT_INTERRUPT_LEVEL_13, %g2 383 343 clr %g5 … … 386 346 /* TT = 0x4e, TL = 0, interrupt_level_14 handler */ 387 347 .org trap_table + TT_INTERRUPT_LEVEL_14*ENTRY_SIZE 388 .global interrupt_level_14_handler_tl0 389 interrupt_level_14_handler_tl0: 348 SYMBOL(interrupt_level_14_handler_tl0) 390 349 mov TT_INTERRUPT_LEVEL_14, %g2 391 350 clr %g5 … … 394 353 /* TT = 0x4f, TL = 0, interrupt_level_15 handler */ 395 354 .org trap_table + TT_INTERRUPT_LEVEL_15*ENTRY_SIZE 396 .global interrupt_level_15_handler_tl0 397 interrupt_level_15_handler_tl0: 355 SYMBOL(interrupt_level_15_handler_tl0) 398 356 mov TT_INTERRUPT_LEVEL_15, %g2 399 357 clr %g5 … … 402 360 /* TT = 0x64, TL = 0, fast_instruction_access_MMU_miss */ 403 361 .org trap_table + TT_FAST_INSTRUCTION_ACCESS_MMU_MISS*ENTRY_SIZE 404 .global fast_instruction_access_mmu_miss_handler_tl0 405 fast_instruction_access_mmu_miss_handler_tl0: 362 SYMBOL(fast_instruction_access_mmu_miss_handler_tl0) 406 363 FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER 407 364 408 365 /* TT = 0x68, TL = 0, fast_data_access_MMU_miss */ 409 366 .org trap_table + TT_FAST_DATA_ACCESS_MMU_MISS*ENTRY_SIZE 410 .global fast_data_access_mmu_miss_handler_tl0 411 fast_data_access_mmu_miss_handler_tl0: 367 SYMBOL(fast_data_access_mmu_miss_handler_tl0) 412 368 FAST_DATA_ACCESS_MMU_MISS_HANDLER 0 413 369 414 370 /* TT = 0x6c, TL = 0, fast_data_access_protection */ 415 371 .org trap_table + TT_FAST_DATA_ACCESS_PROTECTION*ENTRY_SIZE 416 .global fast_data_access_protection_handler_tl0 417 fast_data_access_protection_handler_tl0: 372 SYMBOL(fast_data_access_protection_handler_tl0) 418 373 FAST_DATA_ACCESS_PROTECTION_HANDLER 0 419 374 420 375 /* TT = 0x7c, TL = 0, cpu_mondo */ 421 376 .org trap_table + TT_CPU_MONDO*ENTRY_SIZE 422 .global cpu_mondo_handler_tl0 423 cpu_mondo_handler_tl0: 377 SYMBOL(cpu_mondo_handler_tl0) 424 378 mov TT_CPU_MONDO, %g2 425 379 clr %g5 … … 428 382 /* TT = 0x80, TL = 0, spill_0_normal handler */ 429 383 .org trap_table + TT_SPILL_0_NORMAL*ENTRY_SIZE 430 .global spill_0_normal_tl0 431 spill_0_normal_tl0: 384 SYMBOL(spill_0_normal_tl0) 432 385 SPILL_NORMAL_HANDLER_KERNEL 433 386 434 387 /* TT = 0x84, TL = 0, spill_1_normal handler */ 435 388 .org trap_table + TT_SPILL_1_NORMAL*ENTRY_SIZE 436 .global spill_1_normal_tl0 437 spill_1_normal_tl0: 389 SYMBOL(spill_1_normal_tl0) 438 390 SPILL_NORMAL_HANDLER_USERSPACE 439 391 440 392 /* TT = 0x88, TL = 0, spill_2_normal handler */ 441 393 .org trap_table + TT_SPILL_2_NORMAL*ENTRY_SIZE 442 .global spill_2_normal_tl0 443 spill_2_normal_tl0: 394 SYMBOL(spill_2_normal_tl0) 444 395 SPILL_TO_USPACE_WINDOW_BUFFER 445 396 446 397 /* TT = 0xa0, TL = 0, spill_0_other handler */ 447 398 .org trap_table + TT_SPILL_0_OTHER*ENTRY_SIZE 448 .global spill_0_other_tl0 449 spill_0_other_tl0: 399 SYMBOL(spill_0_other_tl0) 450 400 SPILL_TO_USPACE_WINDOW_BUFFER 451 401 452 402 /* TT = 0xc0, TL = 0, fill_0_normal handler */ 453 403 .org trap_table + TT_FILL_0_NORMAL*ENTRY_SIZE 454 .global fill_0_normal_tl0 455 fill_0_normal_tl0: 404 SYMBOL(fill_0_normal_tl0) 456 405 FILL_NORMAL_HANDLER_KERNEL 457 406 458 407 /* TT = 0xc4, TL = 0, fill_1_normal handler */ 459 408 .org trap_table + TT_FILL_1_NORMAL*ENTRY_SIZE 460 .global fill_1_normal_tl0 461 fill_1_normal_tl0: 409 SYMBOL(fill_1_normal_tl0) 462 410 FILL_NORMAL_HANDLER_USERSPACE 463 411 … … 472 420 127 473 421 .org trap_table + (TT_TRAP_INSTRUCTION_0+\cur)*ENTRY_SIZE 474 .global trap_instruction_\cur\()_tl0 475 trap_instruction_\cur\()_tl0: 422 SYMBOL(trap_instruction_\cur\()_tl0) 476 423 mov \cur, %g2 477 424 ba %xcc, trap_instruction_handler … … 486 433 /* TT = 0x08, TL > 0, IAE_privilege_violation on UltraSPARC T2 */ 487 434 .org trap_table + (TT_INSTRUCTION_ACCESS_EXCEPTION+512)*ENTRY_SIZE 488 .global instruction_access_exception_tl1 489 instruction_access_exception_tl1: 435 SYMBOL(instruction_access_exception_tl1) 490 436 wrpr %g0, 1, %tl 491 437 mov TT_INSTRUCTION_ACCESS_EXCEPTION, %g2 … … 495 441 /* TT = 0x09, TL > 0, instruction_access_mmu_miss */ 496 442 .org trap_table + (TT_INSTRUCTION_ACCESS_MMU_MISS+512)*ENTRY_SIZE 497 .global instruction_access_mmu_miss_handler_tl1 443 SYMBOL(instruction_access_mmu_miss_handler_tl1) 498 444 wrpr %g0, 1, %tl 499 445 ba,a %xcc, fast_instruction_access_mmu_miss_handler_tl0 … … 501 447 /* TT = 0x0a, TL > 0, instruction_access_error */ 502 448 .org trap_table + (TT_INSTRUCTION_ACCESS_ERROR+512)*ENTRY_SIZE 503 .global instruction_access_error_tl1 504 instruction_access_error_tl1: 449 SYMBOL(instruction_access_error_tl1) 505 450 wrpr %g0, 1, %tl 506 451 mov TT_INSTRUCTION_ACCESS_ERROR, %g2 … … 510 455 /* TT = 0x0b, TL > 0, IAE_unauth_access */ 511 456 .org trap_table + (TT_IAE_UNAUTH_ACCESS+512)*ENTRY_SIZE 512 .global iae_unauth_access_tl1 513 iae_unauth_access_tl1: 457 SYMBOL(iae_unauth_access_tl1) 514 458 wrpr %g0, 1, %tl 515 459 mov TT_IAE_UNAUTH_ACCESS, %g2 … … 519 463 /* TT = 0x0c, TL > 0, IAE_nfo_page */ 520 464 .org trap_table + (TT_IAE_NFO_PAGE+512)*ENTRY_SIZE 521 .global iae_nfo_page_tl1 522 iae_nfo_page_tl1: 465 SYMBOL(iae_nfo_page_tl1) 523 466 wrpr %g0, 1, %tl 524 467 mov TT_IAE_NFO_PAGE, %g2 … … 528 471 /* TT = 0x10, TL > 0, illegal_instruction */ 529 472 .org trap_table + (TT_ILLEGAL_INSTRUCTION+512)*ENTRY_SIZE 530 .global illegal_instruction_tl1 531 illegal_instruction_tl1: 473 SYMBOL(illegal_instruction_tl1) 532 474 wrpr %g0, 1, %tl 533 475 mov TT_ILLEGAL_INSTRUCTION, %g2 … … 537 479 /* TT = 0x14, TL > 0, DAE_invalid_asi */ 538 480 .org trap_table + (TT_DAE_INVALID_ASI+512)*ENTRY_SIZE 539 .global dae_invalid_asi_tl1 540 dae_invalid_asi_tl1: 481 SYMBOL(dae_invalid_asi_tl1) 541 482 wrpr %g0, 1, %tl 542 483 mov TT_DAE_INVALID_ASI, %g2 … … 546 487 /* TT = 0x15, TL > 0, DAE_privilege_violation */ 547 488 .org trap_table + (TT_DAE_PRIVILEGE_VIOLATION+512)*ENTRY_SIZE 548 .global dae_privilege_violation_tl1 549 dae_privilege_violation_tl1: 489 SYMBOL(dae_privilege_violation_tl1) 550 490 wrpr %g0, 1, %tl 551 491 mov TT_DAE_PRIVILEGE_VIOLATION, %g2 … … 555 495 /* TT = 0x16, TL > 0, DAE_nc_page */ 556 496 .org trap_table + (TT_DAE_NC_PAGE+512)*ENTRY_SIZE 557 .global dae_nc_page_tl1 558 dae_nc_page_tl1: 497 SYMBOL(dae_nc_page_tl1) 559 498 wrpr %g0, 1, %tl 560 499 mov TT_DAE_NC_PAGE, %g2 … … 564 503 /* TT = 0x17, TL > 0, DAE_nfo_page */ 565 504 .org trap_table + (TT_DAE_NFO_PAGE+512)*ENTRY_SIZE 566 .global dae_nfo_page_tl1 567 dae_nfo_page_tl1: 505 SYMBOL(dae_nfo_page_tl1) 568 506 wrpr %g0, 1, %tl 569 507 mov TT_DAE_NFO_PAGE, %g2 … … 573 511 /* TT = 0x24, TL > 0, clean_window handler */ 574 512 .org trap_table + (TT_CLEAN_WINDOW+512)*ENTRY_SIZE 575 .global clean_window_tl1 576 clean_window_tl1: 513 SYMBOL(clean_window_tl1) 577 514 CLEAN_WINDOW_HANDLER 578 515 579 516 /* TT = 0x28, TL > 0, division_by_zero */ 580 517 .org trap_table + (TT_DIVISION_BY_ZERO+512)*ENTRY_SIZE 581 .global division_by_zero_tl1 582 division_by_zero_tl1: 518 SYMBOL(division_by_zero_tl1) 583 519 wrpr %g0, 1, %tl 584 520 mov TT_DIVISION_BY_ZERO, %g2 … … 588 524 /* TT = 0x30, TL > 0, data_access_exception */ 589 525 .org trap_table + (TT_DATA_ACCESS_EXCEPTION+512)*ENTRY_SIZE 590 .global data_access_exception_tl1 591 data_access_exception_tl1: 526 SYMBOL(data_access_exception_tl1) 592 527 wrpr %g0, 1, %tl 593 528 mov TT_DATA_ACCESS_EXCEPTION, %g2 … … 597 532 /* TT = 0x31, TL > 0, data_access_mmu_miss */ 598 533 .org trap_table + (TT_DATA_ACCESS_MMU_MISS+512)*ENTRY_SIZE 599 .global data_access_mmu_miss_tl1 600 data_access_mmu_miss_tl1: 534 SYMBOL(data_access_mmu_miss_tl1) 601 535 ba,a %xcc, fast_data_access_mmu_miss_handler_tl1 602 536 603 537 /* TT = 0x32, TL > 0, data_access_error */ 604 538 .org trap_table + (TT_DATA_ACCESS_ERROR+512)*ENTRY_SIZE 605 .global data_access_error_tl1 606 data_access_error_tl1: 539 SYMBOL(data_access_error_tl1) 607 540 wrpr %g0, 1, %tl 608 541 mov TT_DATA_ACCESS_ERROR, %g2 … … 612 545 /* TT = 0x34, TL > 0, mem_address_not_aligned */ 613 546 .org trap_table + (TT_MEM_ADDRESS_NOT_ALIGNED+512)*ENTRY_SIZE 614 .global mem_address_not_aligned_tl1 615 mem_address_not_aligned_tl1: 547 SYMBOL(mem_address_not_aligned_tl1) 616 548 wrpr %g0, 1, %tl 617 549 mov TT_MEM_ADDRESS_NOT_ALIGNED, %g2 … … 621 553 /* TT = 0x68, TL > 0, fast_data_access_MMU_miss */ 622 554 .org trap_table + (TT_FAST_DATA_ACCESS_MMU_MISS+512)*ENTRY_SIZE 623 .global fast_data_access_mmu_miss_handler_tl1 624 fast_data_access_mmu_miss_handler_tl1: 555 SYMBOL(fast_data_access_mmu_miss_handler_tl1) 625 556 FAST_DATA_ACCESS_MMU_MISS_HANDLER 1 626 557 627 558 /* TT = 0x6c, TL > 0, fast_data_access_protection */ 628 559 .org trap_table + (TT_FAST_DATA_ACCESS_PROTECTION+512)*ENTRY_SIZE 629 .global fast_data_access_protection_handler_tl1 630 fast_data_access_protection_handler_tl1: 560 SYMBOL(fast_data_access_protection_handler_tl1) 631 561 FAST_DATA_ACCESS_PROTECTION_HANDLER 1 632 562 633 563 /* TT = 0x7c, TL > 0, cpu_mondo */ 634 564 .org trap_table + (TT_CPU_MONDO+512)*ENTRY_SIZE 635 .global cpu_mondo_handler_tl1 636 cpu_mondo_handler_tl1: 565 SYMBOL(cpu_mondo_handler_tl1) 637 566 wrpr %g0, %tl 638 567 mov TT_CPU_MONDO, %g2 … … 642 571 /* TT = 0x80, TL > 0, spill_0_normal handler */ 643 572 .org trap_table + (TT_SPILL_0_NORMAL+512)*ENTRY_SIZE 644 .global spill_0_normal_tl1 645 spill_0_normal_tl1: 573 SYMBOL(spill_0_normal_tl1) 646 574 SPILL_NORMAL_HANDLER_KERNEL 647 575 648 576 /* TT = 0x88, TL > 0, spill_2_normal handler */ 649 577 .org trap_table + (TT_SPILL_2_NORMAL+512)*ENTRY_SIZE 650 .global spill_2_normal_tl1 651 spill_2_normal_tl1: 578 SYMBOL(spill_2_normal_tl1) 652 579 SPILL_TO_USPACE_WINDOW_BUFFER 653 580 654 581 /* TT = 0xa0, TL > 0, spill_0_other handler */ 655 582 .org trap_table + (TT_SPILL_0_OTHER+512)*ENTRY_SIZE 656 .global spill_0_other_tl1 657 spill_0_other_tl1: 583 SYMBOL(spill_0_other_tl1) 658 584 SPILL_TO_USPACE_WINDOW_BUFFER 659 585 660 586 /* TT = 0xc0, TL > 0, fill_0_normal handler */ 661 587 .org trap_table + (TT_FILL_0_NORMAL+512)*ENTRY_SIZE 662 .global fill_0_normal_tl1 663 fill_0_normal_tl1: 588 SYMBOL(fill_0_normal_tl1) 664 589 FILL_NORMAL_HANDLER_KERNEL 665 590 … … 1178 1103 .endm 1179 1104 1180 .global preemptible_handler 1181 preemptible_handler: 1105 SYMBOL(preemptible_handler) 1182 1106 PREEMPTIBLE_HANDLER_TEMPLATE 0 1183 1107 1184 .global trap_instruction_handler 1185 trap_instruction_handler: 1108 SYMBOL(trap_instruction_handler) 1186 1109 PREEMPTIBLE_HANDLER_TEMPLATE 1 -
kernel/generic/include/syscall/syscall.h
r6adb775f r32573ff 45 45 extern sysarg_t syscall_handler(sysarg_t, sysarg_t, sysarg_t, sysarg_t, 46 46 sysarg_t, sysarg_t, sysarg_t); 47 extern sysarg_t sys_tls_set(uintptr_t);48 47 49 48 #endif -
kernel/generic/src/syscall/syscall.c
r6adb775f r32573ff 124 124 /* System management syscalls. */ 125 125 (syshandler_t) sys_kio, 126 (syshandler_t) sys_tls_set,127 126 128 127 /* Thread and task related syscalls. */
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