source: mainline/kernel/arch/ia64/src/start.S@ 22f0561

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 22f0561 was 22f0561, checked in by Jakub Jermar <jakub@…>, 14 years ago

Get rid of kernel static non-identity mappings on ia64.

  • IO_OFFSET is replaced by legacyio_virt_base and LEGACYIO_USER_BASE.
  • VIO_OFFSET and FW_OFFSET are removed entirely.
  • Legacy I/O and IO SAPIC are mapped via hw_map().
  • Remove corresponding locked translation records.
  • Cleanup ia64 kernel pio_read/write_8|16|32().
  • Property mode set to 100644
File size: 3.9 KB
Line 
1#
2# Copyright (c) 2005 Jakub Jermar
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions
7# are met:
8#
9# - Redistributions of source code must retain the above copyright
10# notice, this list of conditions and the following disclaimer.
11# - Redistributions in binary form must reproduce the above copyright
12# notice, this list of conditions and the following disclaimer in the
13# documentation and/or other materials provided with the distribution.
14# - The name of the author may not be used to endorse or promote products
15# derived from this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28
29#include <arch/register.h>
30#include <arch/mm/page.h>
31#include <arch/mm/asid.h>
32#include <mm/asid.h>
33
34#define RR_MASK (0xFFFFFFFF00000002)
35#define RID_SHIFT 8
36#define PS_SHIFT 2
37
38#define KERNEL_TRANSLATION_I 0x0010000000000661
39#define KERNEL_TRANSLATION_D 0x0010000000000661
40
41.section K_TEXT_START, "ax"
42
43.global kernel_image_start
44
45stack0:
46
47#
48# Kernel entry point.
49#
50# This is where we are passed control from the boot code.
51# Register contents:
52#
53# r2 Address of the boot code's bootinfo structure.
54#
55kernel_image_start:
56 .auto
57
58 mov psr.l = r0
59 srlz.i
60 srlz.d
61
62 # Fill TR.i and TR.d using Region Register #VRN_KERNEL
63
64 movl r8 = (VRN_KERNEL << VRN_SHIFT)
65 mov r9 = rr[r8]
66
67 movl r10 = (RR_MASK)
68 and r9 = r10, r9
69 movl r10 = (((RID_KERNEL7) << RID_SHIFT) | (KERNEL_PAGE_WIDTH << PS_SHIFT))
70 or r9 = r10, r9
71
72 mov rr[r8] = r9
73
74 movl r8 = (VRN_KERNEL << VRN_SHIFT)
75 mov cr.ifa = r8
76
77 mov r11 = cr.itir
78 movl r10 = (KERNEL_PAGE_WIDTH << PS_SHIFT)
79 or r10 = r10, r11
80 mov cr.itir = r10
81
82 movl r10 = (KERNEL_TRANSLATION_I)
83 itr.i itr[r0] = r10
84 movl r10 = (KERNEL_TRANSLATION_D)
85 itr.d dtr[r0] = r10
86
87 # Initialize DCR
88
89 movl r10 = (DCR_DP_MASK | DCR_DK_MASK | DCR_DX_MASK | DCR_DR_MASK | DCR_DA_MASK | DCR_DD_MASK | DCR_LC_MASK)
90 mov r9 = cr.dcr
91 or r10 = r10, r9
92 mov cr.dcr = r10
93
94 # Initialize PSR
95
96 movl r10 = (PSR_DT_MASK | PSR_RT_MASK | PSR_IT_MASK | PSR_IC_MASK) /* Enable paging */
97 mov r9 = psr
98
99 or r10 = r10, r9
100 mov cr.ipsr = r10
101 mov cr.ifs = r0
102 movl r8 = paging_start
103 mov cr.iip = r8
104 srlz.d
105 srlz.i
106
107 .explicit
108
109 /*
110 * Return From Interrupt is the only way to
111 * fill the upper half word of PSR.
112 */
113 rfi ;;
114
115.global paging_start
116paging_start:
117
118 /*
119 * Now we are paging.
120 */
121
122 #
123 # Set Interruption Vector Address
124 # (i.e. location of interruption vector table)
125 #
126 movl r8 = ivt ;;
127 mov cr.iva = r8
128 srlz.d ;;
129
130
131 # Switch to register bank 1
132 bsw.1
133
134 # Initialize register stack
135 mov ar.rsc = r0
136 movl r8 = (VRN_KERNEL << VRN_SHIFT) ;;
137 mov ar.bspstore = r8
138 loadrs
139
140 #
141 # Initialize memory stack to some sane value and allocate a scratch area
142 # on it.
143 #
144 movl sp = stack0 ;;
145 add sp = -16, sp
146
147 # Initialize gp (Global Pointer) register
148 movl gp = __gp
149
150 #
151 # Initialize bootinfo on BSP.
152 #
153 movl r20 = (VRN_KERNEL << VRN_SHIFT) ;;
154 or r20 = r20, r2 ;;
155 addl r21 = @gprel(bootinfo), gp ;;
156 st8 [r21] = r20
157
158 ssm (1 << 19) ;; /* Disable f32 - f127 */
159 srlz.i
160 srlz.d ;;
161
162 br.call.sptk.many b0 = arch_pre_main
1630:
164 br.call.sptk.many b0 = main_bsp
1650:
166 br 0b
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