Changeset 235d31d in mainline for kernel/arch


Ignore:
Timestamp:
2014-12-22T17:47:40Z (11 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
8c7d5ad
Parents:
eae91e0 (diff), 759ea0d (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge the CHT pre-integration branch

This branch contains:

  • the merge of lp:~adam-hraska+lp/helenos/rcu, which brings:
  • a new preemptible kernel RCU variant called A-RCU,
  • a preemptible variant of Podzimek's non-preemptible kernel RCU and
  • a new variant of usersace RCU,
  • a new concurrent hash table (CHT) implementation based on RCU,
  • a deployment of CHT in kernel futex handling,
  • a deployment of the userspace RCU in the implementation of upgradable futexes,

all described in Adam Hraska's master thesis named Read-Copy-Update
for HelenOS, defended in 2013 at MFF UK; furthemore, the branch
fixes two synchronization bugs in condvars and waitq, respectively:

  • revid:adam.hraska+hos@gmail.com-20121116144921-3to9u1tn1sg07rg7
  • revid:adam.hraska+hos@gmail.com-20121116173623-km7gwtqixwudpe66
  • build fixes required to pass make check
  • overhaul of ia64 and sparc64 trap handling, to allow exc_dispatch() to be used now when the kernel is more picky about CPU state accounting
  • an important fix of the sparc64/sun4v preemptible trap handler
  • various other fixes of issues discovered on non-x86 architectures
Location:
kernel/arch
Files:
8 added
62 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/abs32le/Makefile.inc

    reae91e0 r235d31d  
    5151        arch/$(KARCH)/src/cpu/cpu.c \
    5252        arch/$(KARCH)/src/smp/smp.c \
     53        arch/$(KARCH)/src/smp/smp_call.c \
    5354        arch/$(KARCH)/src/smp/ipi.c \
    5455        arch/$(KARCH)/src/mm/km.c \

  • kernel/arch/abs32le/src/cpu/cpu.c

    reae91e0 r235d31d  
    3434
    3535#include <arch/cpu.h>
     36#include <cpu.h>
    3637#include <arch.h>
    3738#include <typedefs.h>

  • kernel/arch/amd64/Makefile.inc

    reae91e0 r235d31d  
    8484                arch/$(KARCH)/src/smp/ipi.c \
    8585                arch/$(KARCH)/src/smp/mps.c \
     86                arch/$(KARCH)/src/smp/smp_call.c \
    8687                arch/$(KARCH)/src/smp/smp.c
    8788endif

  • kernel/arch/amd64/include/arch/atomic.h

    reae91e0 r235d31d  
    11/*
    22 * Copyright (c) 2001-2004 Jakub Jermar
     3 * Copyright (c) 2012      Adam Hraska
    34 * All rights reserved.
    45 *
    … …  
    140141}
    141142
     143
     144#define _atomic_cas_impl(pptr, exp_val, new_val, old_val, prefix) \
     145({ \
     146        switch (sizeof(typeof(*(pptr)))) { \
     147        case 1: \
     148                asm volatile ( \
     149                        prefix " cmpxchgb %[newval], %[ptr]\n" \
     150                        : /* Output operands. */ \
     151                        /* Old/current value is returned in eax. */ \
     152                        [oldval] "=a" (old_val), \
     153                        /* (*ptr) will be read and written to, hence "+" */ \
     154                        [ptr] "+m" (*pptr) \
     155                        : /* Input operands. */ \
     156                        /* Expected value must be in eax. */ \
     157                        [expval] "a" (exp_val), \
     158                        /* The new value may be in any register. */ \
     159                        [newval] "r" (new_val) \
     160                        : "memory" \
     161                ); \
     162                break; \
     163        case 2: \
     164                asm volatile ( \
     165                        prefix " cmpxchgw %[newval], %[ptr]\n" \
     166                        : /* Output operands. */ \
     167                        /* Old/current value is returned in eax. */ \
     168                        [oldval] "=a" (old_val), \
     169                        /* (*ptr) will be read and written to, hence "+" */ \
     170                        [ptr] "+m" (*pptr) \
     171                        : /* Input operands. */ \
     172                        /* Expected value must be in eax. */ \
     173                        [expval] "a" (exp_val), \
     174                        /* The new value may be in any register. */ \
     175                        [newval] "r" (new_val) \
     176                        : "memory" \
     177                ); \
     178                break; \
     179        case 4: \
     180                asm volatile ( \
     181                        prefix " cmpxchgl %[newval], %[ptr]\n" \
     182                        : /* Output operands. */ \
     183                        /* Old/current value is returned in eax. */ \
     184                        [oldval] "=a" (old_val), \
     185                        /* (*ptr) will be read and written to, hence "+" */ \
     186                        [ptr] "+m" (*pptr) \
     187                        : /* Input operands. */ \
     188                        /* Expected value must be in eax. */ \
     189                        [expval] "a" (exp_val), \
     190                        /* The new value may be in any register. */ \
     191                        [newval] "r" (new_val) \
     192                        : "memory" \
     193                ); \
     194                break; \
     195        case 8: \
     196                asm volatile ( \
     197                        prefix " cmpxchgq %[newval], %[ptr]\n" \
     198                        : /* Output operands. */ \
     199                        /* Old/current value is returned in eax. */ \
     200                        [oldval] "=a" (old_val), \
     201                        /* (*ptr) will be read and written to, hence "+" */ \
     202                        [ptr] "+m" (*pptr) \
     203                        : /* Input operands. */ \
     204                        /* Expected value must be in eax. */ \
     205                        [expval] "a" (exp_val), \
     206                        /* The new value may be in any register. */ \
     207                        [newval] "r" (new_val) \
     208                        : "memory" \
     209                ); \
     210                break; \
     211        } \
     212})
     213
     214
     215#ifndef local_atomic_cas
     216
     217#define local_atomic_cas(pptr, exp_val, new_val) \
     218({ \
     219        /* Use proper types and avoid name clashes */ \
     220        typeof(*(pptr)) _old_val_cas; \
     221        typeof(*(pptr)) _exp_val_cas = exp_val; \
     222        typeof(*(pptr)) _new_val_cas = new_val; \
     223        _atomic_cas_impl(pptr, _exp_val_cas, _new_val_cas, _old_val_cas, ""); \
     224        \
     225        _old_val_cas; \
     226})
     227
     228#else
     229/* Check if arch/atomic.h does not accidentally include /atomic.h .*/
     230#error Architecture specific cpu local atomics already defined! Check your includes.
    142231#endif
    143232
     233
     234#ifndef local_atomic_exchange
     235/*
     236 * Issuing a xchg instruction always implies lock prefix semantics.
     237 * Therefore, it is cheaper to use a cmpxchg without a lock prefix
     238 * in a loop.
     239 */
     240#define local_atomic_exchange(pptr, new_val) \
     241({ \
     242        /* Use proper types and avoid name clashes */ \
     243        typeof(*(pptr)) _exp_val_x; \
     244        typeof(*(pptr)) _old_val_x; \
     245        typeof(*(pptr)) _new_val_x = new_val; \
     246        \
     247        do { \
     248                _exp_val_x = *pptr; \
     249                _old_val_x = local_atomic_cas(pptr, _exp_val_x, _new_val_x); \
     250        } while (_old_val_x != _exp_val_x); \
     251        \
     252        _old_val_x; \
     253})
     254
     255#else
     256/* Check if arch/atomic.h does not accidentally include /atomic.h .*/
     257#error Architecture specific cpu local atomics already defined! Check your includes.
     258#endif
     259
     260
     261#endif
     262
    144263/** @}
    145264 */

  • kernel/arch/amd64/include/arch/cpu.h

    reae91e0 r235d31d  
    7373        tss_t *tss;
    7474       
     75        unsigned int id; /** CPU's local, ie physical, APIC ID. */
     76       
    7577        size_t iomapver_copy;  /** Copy of TASK's I/O Permission bitmap generation count. */
    7678} cpu_arch_t;

  • kernel/arch/amd64/include/arch/interrupt.h

    reae91e0 r235d31d  
    7171#define VECTOR_TLB_SHOOTDOWN_IPI  (IVT_FREEBASE + 1)
    7272#define VECTOR_DEBUG_IPI          (IVT_FREEBASE + 2)
     73#define VECTOR_SMP_CALL_IPI       (IVT_FREEBASE + 3)
    7374
    7475extern void (* disable_irqs_function)(uint16_t);

  • kernel/arch/amd64/src/amd64.c

    reae91e0 r235d31d  
    170170}
    171171
    172 void arch_post_cpu_init()
     172void arch_post_cpu_init(void)
    173173{
    174174#ifdef CONFIG_SMP

  • kernel/arch/amd64/src/cpu/cpu.c

    reae91e0 r235d31d  
    158158void cpu_print_report(cpu_t* m)
    159159{
    160         printf("cpu%d: (%s family=%d model=%d stepping=%d) %dMHz\n",
     160        printf("cpu%d: (%s family=%d model=%d stepping=%d apicid=%u) %dMHz\n",
    161161            m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model,
    162             m->arch.stepping, m->frequency_mhz);
     162            m->arch.stepping, m->arch.id, m->frequency_mhz);
    163163}
    164164

  • kernel/arch/amd64/src/interrupt.c

    reae91e0 r235d31d  
    5555#include <symtab.h>
    5656#include <stacktrace.h>
     57#include <smp/smp_call.h>
    5758
    5859/*
    … …  
    161162        trap_virtual_eoi();
    162163        tlb_shootdown_ipi_recv();
     164}
     165
     166static void arch_smp_call_ipi_recv(unsigned int n, istate_t *istate)
     167{
     168        trap_virtual_eoi();
     169        smp_call_ipi_recv();
    163170}
    164171#endif
    … …  
    224231        exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown", true,
    225232            (iroutine_t) tlb_shootdown_ipi);
     233        exc_register(VECTOR_SMP_CALL_IPI, "smp_call", true,
     234                (iroutine_t) arch_smp_call_ipi_recv);
    226235#endif
    227236}

  • kernel/arch/arm32/Makefile.inc

    reae91e0 r235d31d  
    6565        arch/$(KARCH)/src/mm/tlb.c \
    6666        arch/$(KARCH)/src/mm/page_fault.c \
     67        arch/$(KARCH)/src/atomic.c \
    6768        arch/$(KARCH)/src/ras.c
    6869

  • kernel/arch/arm32/include/arch/cp15.h

    reae91e0 r235d31d  
    3737#define KERN_arm32_CP15_H_
    3838
     39#if defined(KERNEL) || defined(BOOT)
     40#include <typedefs.h>
     41#else
     42#include <sys/types.h>
     43#endif
    3944
    4045/** See ARM Architecture reference manual ch. B3.17.1 page B3-1456

  • kernel/arch/arm32/src/cpu/cpu.c

    reae91e0 r235d31d  
    4141#include <print.h>
    4242
     43#ifdef CONFIG_FPU
     44#include <arch/fpu_context.h>
     45#endif
     46
    4347static inline unsigned log2(unsigned val)
    4448{
    … …  
    6064static const char * implementer(unsigned id)
    6165{
    62         switch (id)
    63         {
     66        switch (id) {
    6467        case 0x41: return "ARM Limited";
    6568        case 0x44: return "Digital Equipment Corporation";

  • kernel/arch/arm32/src/exception.c

    reae91e0 r235d31d  
    8888static void swi_exception(unsigned int exc_no, istate_t *istate)
    8989{
     90        interrupts_enable();
    9091        istate->r0 = syscall_handler(istate->r0, istate->r1, istate->r2,
    9192            istate->r3, istate->r4, istate->r5, istate->r6);
     93        interrupts_disable();
    9294}
    9395

  • kernel/arch/ia32/Makefile.inc

    reae91e0 r235d31d  
    8585        arch/$(KARCH)/src/smp/mps.c \
    8686        arch/$(KARCH)/src/smp/smp.c \
     87        arch/$(KARCH)/src/smp/smp_call.c \
    8788        arch/$(KARCH)/src/atomic.S \
    8889        arch/$(KARCH)/src/smp/ipi.c \

  • kernel/arch/ia32/include/arch/atomic.h

    reae91e0 r235d31d  
    11/*
    22 * Copyright (c) 2001-2004 Jakub Jermar
     3 * Copyright (c) 2012      Adam Hraska
    34 * All rights reserved.
    45 *
    … …  
    113114}
    114115
     116
    115117/** ia32 specific fast spinlock */
    116118NO_TRACE static inline void atomic_lock_arch(atomic_t *val)
    … …  
    142144}
    143145
     146
     147#define _atomic_cas_impl(pptr, exp_val, new_val, old_val, prefix) \
     148({ \
     149        switch (sizeof(typeof(*(pptr)))) { \
     150        case 1: \
     151                asm volatile ( \
     152                        prefix " cmpxchgb %[newval], %[ptr]\n" \
     153                        : /* Output operands. */ \
     154                        /* Old/current value is returned in eax. */ \
     155                        [oldval] "=a" (old_val), \
     156                        /* (*ptr) will be read and written to, hence "+" */ \
     157                        [ptr] "+m" (*pptr) \
     158                        : /* Input operands. */ \
     159                        /* Expected value must be in eax. */ \
     160                        [expval] "a" (exp_val), \
     161                        /* The new value may be in any register. */ \
     162                        [newval] "r" (new_val) \
     163                        : "memory" \
     164                ); \
     165                break; \
     166        case 2: \
     167                asm volatile ( \
     168                        prefix " cmpxchgw %[newval], %[ptr]\n" \
     169                        : /* Output operands. */ \
     170                        /* Old/current value is returned in eax. */ \
     171                        [oldval] "=a" (old_val), \
     172                        /* (*ptr) will be read and written to, hence "+" */ \
     173                        [ptr] "+m" (*pptr) \
     174                        : /* Input operands. */ \
     175                        /* Expected value must be in eax. */ \
     176                        [expval] "a" (exp_val), \
     177                        /* The new value may be in any register. */ \
     178                        [newval] "r" (new_val) \
     179                        : "memory" \
     180                ); \
     181                break; \
     182        case 4: \
     183                asm volatile ( \
     184                        prefix " cmpxchgl %[newval], %[ptr]\n" \
     185                        : /* Output operands. */ \
     186                        /* Old/current value is returned in eax. */ \
     187                        [oldval] "=a" (old_val), \
     188                        /* (*ptr) will be read and written to, hence "+" */ \
     189                        [ptr] "+m" (*pptr) \
     190                        : /* Input operands. */ \
     191                        /* Expected value must be in eax. */ \
     192                        [expval] "a" (exp_val), \
     193                        /* The new value may be in any register. */ \
     194                        [newval] "r" (new_val) \
     195                        : "memory" \
     196                ); \
     197                break; \
     198        } \
     199})
     200
     201
     202#ifndef local_atomic_cas
     203
     204#define local_atomic_cas(pptr, exp_val, new_val) \
     205({ \
     206        /* Use proper types and avoid name clashes */ \
     207        typeof(*(pptr)) _old_val_cas; \
     208        typeof(*(pptr)) _exp_val_cas = exp_val; \
     209        typeof(*(pptr)) _new_val_cas = new_val; \
     210        _atomic_cas_impl(pptr, _exp_val_cas, _new_val_cas, _old_val_cas, ""); \
     211        \
     212        _old_val_cas; \
     213})
     214
     215#else
     216/* Check if arch/atomic.h does not accidentally include /atomic.h .*/
     217#error Architecture specific cpu local atomics already defined! Check your includes.
     218#endif
     219
     220
     221#ifndef local_atomic_exchange
     222/*
     223 * Issuing a xchg instruction always implies lock prefix semantics.
     224 * Therefore, it is cheaper to use a cmpxchg without a lock prefix
     225 * in a loop.
     226 */
     227#define local_atomic_exchange(pptr, new_val) \
     228({ \
     229        /* Use proper types and avoid name clashes */ \
     230        typeof(*(pptr)) _exp_val_x; \
     231        typeof(*(pptr)) _old_val_x; \
     232        typeof(*(pptr)) _new_val_x = new_val; \
     233        \
     234        do { \
     235                _exp_val_x = *pptr; \
     236                _old_val_x = local_atomic_cas(pptr, _exp_val_x, _new_val_x); \
     237        } while (_old_val_x != _exp_val_x); \
     238        \
     239        _old_val_x; \
     240})
     241
     242#else
     243/* Check if arch/atomic.h does not accidentally include /atomic.h .*/
     244#error Architecture specific cpu local atomics already defined! Check your includes.
     245#endif
     246
     247
    144248#endif
    145249

  • kernel/arch/ia32/include/arch/cpu.h

    reae91e0 r235d31d  
    6161        unsigned int stepping;
    6262        cpuid_feature_info_t fi;
    63        
     63
     64        unsigned int id; /** CPU's local, ie physical, APIC ID. */
     65
    6466        tss_t *tss;
    6567       

  • kernel/arch/ia32/include/arch/interrupt.h

    reae91e0 r235d31d  
    7171#define VECTOR_TLB_SHOOTDOWN_IPI  (IVT_FREEBASE + 1)
    7272#define VECTOR_DEBUG_IPI          (IVT_FREEBASE + 2)
     73#define VECTOR_SMP_CALL_IPI       (IVT_FREEBASE + 3)
    7374
    7475extern void (* disable_irqs_function)(uint16_t);

  • kernel/arch/ia32/include/arch/smp/apic.h

    reae91e0 r235d31d  
    353353extern void l_apic_init(void);
    354354extern void l_apic_eoi(void);
     355extern int l_apic_send_custom_ipi(uint8_t, uint8_t);
    355356extern int l_apic_broadcast_custom_ipi(uint8_t);
    356357extern int l_apic_send_init_ipi(uint8_t);

  • kernel/arch/ia32/src/cpu/cpu.c

    reae91e0 r235d31d  
    160160void cpu_print_report(cpu_t* cpu)
    161161{
    162         printf("cpu%u: (%s family=%u model=%u stepping=%u) %" PRIu16 " MHz\n",
    163                 cpu->id, vendor_str[cpu->arch.vendor], cpu->arch.family,
    164                 cpu->arch.model, cpu->arch.stepping, cpu->frequency_mhz);
     162        printf("cpu%u: (%s family=%u model=%u stepping=%u apicid=%u) %" PRIu16
     163                " MHz\n", cpu->id, vendor_str[cpu->arch.vendor], cpu->arch.family,
     164                cpu->arch.model, cpu->arch.stepping, cpu->arch.id, cpu->frequency_mhz);
    165165}
    166166

  • kernel/arch/ia32/src/ia32.c

    reae91e0 r235d31d  
    124124}
    125125
    126 void arch_post_cpu_init()
     126void arch_post_cpu_init(void)
    127127{
    128128#ifdef CONFIG_SMP

  • kernel/arch/ia32/src/interrupt.c

    reae91e0 r235d31d  
    5454#include <symtab.h>
    5555#include <stacktrace.h>
     56#include <smp/smp_call.h>
     57#include <proc/task.h>
    5658
    5759/*
    … …  
    170172        tlb_shootdown_ipi_recv();
    171173}
     174
     175static void arch_smp_call_ipi_recv(unsigned int n, istate_t *istate)
     176{
     177        trap_virtual_eoi();
     178        smp_call_ipi_recv();
     179}
    172180#endif
    173181
    … …  
    230238        exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown", true,
    231239            (iroutine_t) tlb_shootdown_ipi);
     240        exc_register(VECTOR_SMP_CALL_IPI, "smp_call", true,
     241            (iroutine_t) arch_smp_call_ipi_recv);
    232242#endif
    233243}

  • kernel/arch/ia32/src/smp/apic.c

    reae91e0 r235d31d  
    264264}
    265265
    266 #define DELIVS_PENDING_SILENT_RETRIES   4       
    267 
     266/* Waits for the destination cpu to accept the previous ipi. */
    268267static void l_apic_wait_for_delivery(void)
    269268{
    270269        icr_t icr;
    271         unsigned retries = 0;
    272 
     270       
    273271        do {
    274                 if (retries++ > DELIVS_PENDING_SILENT_RETRIES) {
    275                         retries = 0;
    276 #ifdef CONFIG_DEBUG
    277                         log(LF_ARCH, LVL_DEBUG, "IPI is pending.");
    278 #endif
    279                         delay(20);
    280                 }
    281272                icr.lo = l_apic[ICRlo];
    282         } while (icr.delivs == DELIVS_PENDING);
    283        
     273        } while (icr.delivs != DELIVS_IDLE);
     274}
     275
     276/** Send one CPU an IPI vector.
     277 *
     278 * @param apicid Physical APIC ID of the destination CPU.
     279 * @param vector Interrupt vector to be sent.
     280 *
     281 * @return 0 on failure, 1 on success.
     282 */
     283int l_apic_send_custom_ipi(uint8_t apicid, uint8_t vector)
     284{
     285        icr_t icr;
     286
     287        /* Wait for a destination cpu to accept our previous ipi. */
     288        l_apic_wait_for_delivery();
     289       
     290        icr.lo = l_apic[ICRlo];
     291        icr.hi = l_apic[ICRhi];
     292       
     293        icr.delmod = DELMOD_FIXED;
     294        icr.destmod = DESTMOD_PHYS;
     295        icr.level = LEVEL_ASSERT;
     296        icr.shorthand = SHORTHAND_NONE;
     297        icr.trigger_mode = TRIGMOD_LEVEL;
     298        icr.vector = vector;
     299        icr.dest = apicid;
     300
     301        /* Send the IPI by writing to l_apic[ICRlo]. */
     302        l_apic[ICRhi] = icr.hi;
     303        l_apic[ICRlo] = icr.lo;
     304       
     305        return apic_poll_errors();
    284306}
    285307
    … …  
    294316{
    295317        icr_t icr;
     318
     319        /* Wait for a destination cpu to accept our previous ipi. */
     320        l_apic_wait_for_delivery();
    296321       
    297322        icr.lo = l_apic[ICRlo];
    … …  
    304329       
    305330        l_apic[ICRlo] = icr.lo;
    306 
    307         l_apic_wait_for_delivery();
    308331       
    309332        return apic_poll_errors();

  • kernel/arch/ia32/src/smp/smp.c

    reae91e0 r235d31d  
    5555#include <memstr.h>
    5656#include <arch/drivers/i8259.h>
     57#include <cpu.h>
    5758
    5859#ifdef CONFIG_SMP
    … …  
    7778                io_apic = (uint32_t *) km_map((uintptr_t) io_apic, PAGE_SIZE,
    7879                    PAGE_WRITE | PAGE_NOT_CACHEABLE);
     80        }
     81}
     82
     83static void cpu_arch_id_init(void)
     84{
     85        ASSERT(ops != NULL);
     86        ASSERT(cpus != NULL);
     87       
     88        for (unsigned int i = 0; i < config.cpu_count; ++i) {
     89                cpus[i].arch.id = ops->cpu_apic_id(i);
    7990        }
    8091}
    … …  
    92103       
    93104        ASSERT(ops != NULL);
     105
     106        /*
     107         * SMP initialized, cpus array allocated. Assign each CPU its
     108         * physical APIC ID.
     109         */
     110        cpu_arch_id_init();
    94111       
    95112        /*

  • kernel/arch/ia64/Makefile.inc

    reae91e0 r235d31d  
    6161        arch/$(KARCH)/src/ddi/ddi.c \
    6262        arch/$(KARCH)/src/smp/smp.c \
     63        arch/$(KARCH)/src/smp/smp_call.c \
    6364        arch/$(KARCH)/src/drivers/it.c
    6465

  • kernel/arch/ia64/include/arch/interrupt.h

    reae91e0 r235d31d  
    3636#define KERN_ia64_INTERRUPT_H_
    3737
     38#ifndef __ASM__
    3839#include <typedefs.h>
    3940#include <arch/istate.h>
     41#endif
     42
     43#define EXC_ALT_ITLB_FAULT      0xc
     44#define EXC_ALT_DTLB_FAULT      0x10
     45#define EXC_NESTED_TLB_FAULT    0x14
     46#define EXC_DATA_D_BIT_FAULT    0x20
     47#define EXC_INST_A_BIT_FAULT    0x24
     48#define EXC_DATA_A_BIT_FAULT    0x28
     49#define EXC_BREAK_INSTRUCTION   0x2c
     50#define EXC_EXT_INTERRUPT       0x30
     51#define EXC_PAGE_NOT_PRESENT    0x50
     52#define EXC_DATA_AR_FAULT       0x53
     53#define EXC_GENERAL_EXCEPTION   0x54
     54#define EXC_DISABLED_FP_REG     0x55
     55#define EXC_SPECULATION         0x57
    4056
    4157/** ia64 has 256 INRs. */
    4258#define INR_COUNT  256
    4359
    44 /*
    45  * We need to keep this just to compile.
    46  * We might eventually move interrupt/ stuff
    47  * to genarch.
    48  */
    49 #define IVT_ITEMS  0
     60#define IVT_ITEMS  128
    5061#define IVT_FIRST  0
    5162
    … …  
    7283#define EOI  0  /**< The actual value doesn't matter. */
    7384
     85#ifndef __ASM__
    7486extern void *ivt;
    7587
    76 extern void general_exception(uint64_t, istate_t *);
    77 extern int break_instruction(uint64_t, istate_t *);
    78 extern void universal_handler(uint64_t, istate_t *);
    79 extern void nop_handler(uint64_t, istate_t *);
    80 extern void external_interrupt(uint64_t, istate_t *);
    81 extern void disabled_fp_register(uint64_t, istate_t *);
     88extern void general_exception(unsigned int, istate_t *);
     89extern sysarg_t break_instruction(unsigned int, istate_t *);
     90extern void universal_handler(unsigned int, istate_t *);
     91extern void external_interrupt(unsigned int, istate_t *);
     92extern void disabled_fp_register(unsigned int, istate_t *);
    8293
    8394extern void trap_virtual_enable_irqs(uint16_t);
     95
     96void exception_init(void);
     97#endif
    8498
    8599#endif

  • kernel/arch/ia64/include/arch/mm/tlb.h

    reae91e0 r235d31d  
    8686extern void itc_pte_copy(pte_t *t);
    8787
    88 extern void alternate_instruction_tlb_fault(uint64_t vector, istate_t *istate);
    89 extern void alternate_data_tlb_fault(uint64_t vector, istate_t *istate);
    90 extern void data_nested_tlb_fault(uint64_t vector, istate_t *istate);
    91 extern void data_dirty_bit_fault(uint64_t vector, istate_t *istate);
    92 extern void instruction_access_bit_fault(uint64_t vector, istate_t *istate);
    93 extern void data_access_bit_fault(uint64_t vector, istate_t *istate);
    94 extern void data_access_rights_fault(uint64_t vector, istate_t *istate);
    95 extern void page_not_present(uint64_t vector, istate_t *istate);
     88extern void alternate_instruction_tlb_fault(unsigned int, istate_t *);
     89extern void alternate_data_tlb_fault(unsigned int, istate_t *);
     90extern void data_nested_tlb_fault(unsigned int, istate_t *);
     91extern void data_dirty_bit_fault(unsigned int, istate_t *);
     92extern void instruction_access_bit_fault(unsigned int, istate_t *);
     93extern void data_access_bit_fault(unsigned int, istate_t *);
     94extern void data_access_rights_fault(unsigned int, istate_t *);
     95extern void page_not_present(unsigned int, istate_t *);
    9696
    9797#endif

  • kernel/arch/ia64/src/ia64.c

    reae91e0 r235d31d  
    3737#include <errno.h>
    3838#include <interrupt.h>
     39#include <arch/interrupt.h>
    3940#include <macros.h>
    4041#include <str.h>
    … …  
    8586void arch_pre_mm_init(void)
    8687{
     88        if (config.cpu_active == 1)
     89                exception_init();
    8790}
    8891

  • kernel/arch/ia64/src/interrupt.c

    reae91e0 r235d31d  
    5454#include <synch/spinlock.h>
    5555#include <mm/tlb.h>
     56#include <arch/mm/tlb.h>
    5657#include <symtab.h>
    5758#include <putchar.h>
    … …  
    5960#define VECTORS_64_BUNDLE        20
    6061#define VECTORS_16_BUNDLE        48
    61 #define VECTORS_16_BUNDLE_START  0x5000
    62 
    63 #define VECTOR_MAX  0x7f00
    64 
    65 #define BUNDLE_SIZE  16
     62#define VECTORS_16_BUNDLE_START  0x50
     63
     64#define VECTOR_MAX  0x7f
    6665
    6766static const char *vector_names_64_bundle[VECTORS_64_BUNDLE] = {
    … …  
    122121};
    123122
    124 static const char *vector_to_string(uint16_t vector)
    125 {
    126         ASSERT(vector <= VECTOR_MAX);
    127        
    128         if (vector >= VECTORS_16_BUNDLE_START)
    129                 return vector_names_16_bundle[(vector -
    130                     VECTORS_16_BUNDLE_START) / (16 * BUNDLE_SIZE)];
     123static const char *vector_to_string(unsigned int n)
     124{
     125        ASSERT(n <= VECTOR_MAX);
     126       
     127        if (n >= VECTORS_16_BUNDLE_START)
     128                return vector_names_16_bundle[n - VECTORS_16_BUNDLE_START];
    131129        else
    132                 return vector_names_64_bundle[vector / (64 * BUNDLE_SIZE)];
     130                return vector_names_64_bundle[n / 4];
    133131}
    134132
    … …  
    153151}
    154152
    155 void general_exception(uint64_t vector, istate_t *istate)
     153void general_exception(unsigned int n, istate_t *istate)
    156154{
    157155        const char *desc;
    … …  
    182180       
    183181        fault_if_from_uspace(istate, "General Exception (%s).", desc);
    184         panic_badtrap(istate, vector, "General Exception (%s).", desc);
    185 }
    186 
    187 void disabled_fp_register(uint64_t vector, istate_t *istate)
     182        panic_badtrap(istate, n, "General Exception (%s).", desc);
     183}
     184
     185void disabled_fp_register(unsigned int n, istate_t *istate)
    188186{
    189187#ifdef CONFIG_FPU_LAZY
    … …  
    191189#else
    192190        fault_if_from_uspace(istate, "Interruption: %#hx (%s).",
    193             (uint16_t) vector, vector_to_string(vector));
     191            (uint16_t) n, vector_to_string(n));
    194192        panic_badtrap(istate, vector, "Interruption: %#hx (%s).",
    195             (uint16_t) vector, vector_to_string(vector));
     193            (uint16_t) n, vector_to_string(n));
    196194#endif
    197195}
    198196
    199 void nop_handler(uint64_t vector, istate_t *istate)
    200 {
    201 }
    202 
    203197/** Handle syscall. */
    204 int break_instruction(uint64_t vector, istate_t *istate)
    205 {
     198sysarg_t break_instruction(unsigned int n, istate_t *istate)
     199{
     200        sysarg_t ret;
     201
    206202        /*
    207203         * Move to next instruction after BREAK.
    … …  
    214210        }
    215211       
    216         return syscall_handler(istate->in0, istate->in1, istate->in2,
     212        interrupts_enable();
     213        ret = syscall_handler(istate->in0, istate->in1, istate->in2,
    217214            istate->in3, istate->in4, istate->in5, istate->in6);
    218 }
    219 
    220 void universal_handler(uint64_t vector, istate_t *istate)
     215        interrupts_disable();
     216
     217        return ret;
     218}
     219
     220void universal_handler(unsigned int n, istate_t *istate)
    221221{
    222222        fault_if_from_uspace(istate, "Interruption: %#hx (%s).",
    223             (uint16_t) vector, vector_to_string(vector));
    224         panic_badtrap(istate, vector, "Interruption: %#hx (%s).",
    225             (uint16_t) vector, vector_to_string(vector));
     223            n, vector_to_string(n));
     224        panic_badtrap(istate, n, "Interruption: %#hx (%s).",
     225            n, vector_to_string(n));
    226226}
    227227
    … …  
    229229{
    230230        asm volatile (
    231                 "mov cr.eoi=r0;;"
     231                "mov cr.eoi = r0 ;;"
    232232        );
    233233}
    234234
    235 void external_interrupt(uint64_t vector, istate_t *istate)
     235void external_interrupt(unsigned int n, istate_t *istate)
    236236{
    237237        cr_ivr_t ivr;
    … …  
    298298}
    299299
     300void exception_init(void)
     301{
     302        unsigned int i;
     303
     304        for (i = 0; i < IVT_ITEMS; i++)
     305                exc_register(i, "universal_handler", false, universal_handler);
     306
     307        exc_register(EXC_ALT_ITLB_FAULT,
     308            vector_to_string(EXC_ALT_ITLB_FAULT), true,
     309            alternate_instruction_tlb_fault);
     310        exc_register(EXC_ALT_DTLB_FAULT,
     311            vector_to_string(EXC_ALT_DTLB_FAULT), true,
     312            alternate_data_tlb_fault);
     313        exc_register(EXC_NESTED_TLB_FAULT,
     314            vector_to_string(EXC_NESTED_TLB_FAULT), false,
     315            data_nested_tlb_fault);
     316        exc_register(EXC_DATA_D_BIT_FAULT,
     317            vector_to_string(EXC_DATA_D_BIT_FAULT), true,
     318            data_dirty_bit_fault);
     319        exc_register(EXC_INST_A_BIT_FAULT,
     320            vector_to_string(EXC_INST_A_BIT_FAULT), true,
     321            instruction_access_bit_fault);
     322        exc_register(EXC_DATA_A_BIT_FAULT,
     323            vector_to_string(EXC_DATA_A_BIT_FAULT), true,
     324            data_access_bit_fault);
     325        exc_register(EXC_EXT_INTERRUPT,
     326            vector_to_string(EXC_EXT_INTERRUPT), true,
     327            external_interrupt);
     328
     329        exc_register(EXC_PAGE_NOT_PRESENT,
     330            vector_to_string(EXC_PAGE_NOT_PRESENT), true,
     331            page_not_present);
     332        exc_register(EXC_DATA_AR_FAULT,
     333            vector_to_string(EXC_DATA_AR_FAULT), true,
     334            data_access_rights_fault);
     335        exc_register(EXC_GENERAL_EXCEPTION,
     336            vector_to_string(EXC_GENERAL_EXCEPTION), false,
     337            general_exception);
     338        exc_register(EXC_DISABLED_FP_REG,
     339            vector_to_string(EXC_DISABLED_FP_REG), true,
     340            disabled_fp_register);
     341}
     342
    300343/** @}
    301344 */

  • kernel/arch/ia64/src/ivt.S

    reae91e0 r235d31d  
    3131#include <arch/register.h>
    3232#include <arch/mm/page.h>
     33#include <arch/interrupt.h>
    3334#include <arch/istate_struct.h>
    3435#include <align.h>
    … …  
    3940
    4041/** Partitioning of bank 0 registers. */
    41 #define R_OFFS          r16
     42#define R_VECTOR        r16
    4243#define R_HANDLER       r17
    4344#define R_RET           r18
    44 #define R_TMP           r19
    4545#define R_KSTACK_BSP    r22     /* keep in sync with before_thread_runs_arch() */
    4646#define R_KSTACK        r23     /* keep in sync with before_thread_runs_arch() */
    4747
    4848/* Speculation vector handler */
    49 .macro SPECULATION_VECTOR_HANDLER offs
    50     .org ivt + \offs
     49.macro SPECULATION_VECTOR_HANDLER vector
     50    .org ivt + \vector * 0x100
    5151
    5252    /* 1. Save predicates, IIM, IIP, IPSR and ISR CR's in bank 0 registers. */
    … …  
    9494 * @param handler Interrupt handler address.
    9595 */
    96 .macro HEAVYWEIGHT_HANDLER offs, handler=universal_handler
    97     .org ivt + \offs
    98         mov R_OFFS = \offs
     96.macro HEAVYWEIGHT_HANDLER vector, handler=exc_dispatch
     97    .org ivt + \vector * 0x100
     98        mov R_VECTOR = \vector
    9999        movl R_HANDLER = \handler ;;
    100100        br heavyweight_handler
    … …  
    165165         * copy input parameters to stack.
    166166         */
    167         mov R_TMP = 0x2c00 ;;
    168         cmp.eq p6, p5 = R_OFFS, R_TMP ;;
     167        cmp.eq p6, p5 = EXC_BREAK_INSTRUCTION, R_VECTOR ;;
    169168       
    170169        /*
    … …  
    309308        mov loc1 = R_RET        /* b0 belonging to interrupted context */
    310309        mov loc2 = R_HANDLER
    311         mov out0 = R_OFFS
     310        mov out0 = R_VECTOR
    312311       
    313312        add out1 = STACK_SCRATCH_AREA_SIZE, r12
    … …  
    543542.align 32768
    544543ivt:
    545         HEAVYWEIGHT_HANDLER 0x0000
    546         HEAVYWEIGHT_HANDLER 0x0400
    547         HEAVYWEIGHT_HANDLER 0x0800
    548         HEAVYWEIGHT_HANDLER 0x0c00 alternate_instruction_tlb_fault
    549         HEAVYWEIGHT_HANDLER 0x1000 alternate_data_tlb_fault
    550         HEAVYWEIGHT_HANDLER 0x1400 data_nested_tlb_fault
    551         HEAVYWEIGHT_HANDLER 0x1800
    552         HEAVYWEIGHT_HANDLER 0x1c00
    553         HEAVYWEIGHT_HANDLER 0x2000 data_dirty_bit_fault
    554         HEAVYWEIGHT_HANDLER 0x2400 instruction_access_bit_fault
    555         HEAVYWEIGHT_HANDLER 0x2800 data_access_bit_fault
    556         HEAVYWEIGHT_HANDLER 0x2c00 break_instruction
    557         HEAVYWEIGHT_HANDLER 0x3000 external_interrupt   /* For external interrupt, heavyweight handler is used. */
    558         HEAVYWEIGHT_HANDLER 0x3400
    559         HEAVYWEIGHT_HANDLER 0x3800
    560         HEAVYWEIGHT_HANDLER 0x3c00
    561         HEAVYWEIGHT_HANDLER 0x4000
    562         HEAVYWEIGHT_HANDLER 0x4400
    563         HEAVYWEIGHT_HANDLER 0x4800
    564         HEAVYWEIGHT_HANDLER 0x4c00
    565 
    566         HEAVYWEIGHT_HANDLER 0x5000 page_not_present
    567         HEAVYWEIGHT_HANDLER 0x5100
    568         HEAVYWEIGHT_HANDLER 0x5200
    569         HEAVYWEIGHT_HANDLER 0x5300 data_access_rights_fault
    570         HEAVYWEIGHT_HANDLER 0x5400 general_exception
    571         HEAVYWEIGHT_HANDLER 0x5500 disabled_fp_register
    572         HEAVYWEIGHT_HANDLER 0x5600
    573         SPECULATION_VECTOR_HANDLER 0x5700
    574         HEAVYWEIGHT_HANDLER 0x5800
    575         HEAVYWEIGHT_HANDLER 0x5900
    576         HEAVYWEIGHT_HANDLER 0x5a00
    577         HEAVYWEIGHT_HANDLER 0x5b00
    578         HEAVYWEIGHT_HANDLER 0x5c00
    579         HEAVYWEIGHT_HANDLER 0x5d00
    580         HEAVYWEIGHT_HANDLER 0x5e00
    581         HEAVYWEIGHT_HANDLER 0x5f00
    582        
    583         HEAVYWEIGHT_HANDLER 0x6000
    584         HEAVYWEIGHT_HANDLER 0x6100
    585         HEAVYWEIGHT_HANDLER 0x6200
    586         HEAVYWEIGHT_HANDLER 0x6300
    587         HEAVYWEIGHT_HANDLER 0x6400
    588         HEAVYWEIGHT_HANDLER 0x6500
    589         HEAVYWEIGHT_HANDLER 0x6600
    590         HEAVYWEIGHT_HANDLER 0x6700
    591         HEAVYWEIGHT_HANDLER 0x6800
    592         HEAVYWEIGHT_HANDLER 0x6900
    593         HEAVYWEIGHT_HANDLER 0x6a00
    594         HEAVYWEIGHT_HANDLER 0x6b00
    595         HEAVYWEIGHT_HANDLER 0x6c00
    596         HEAVYWEIGHT_HANDLER 0x6d00
    597         HEAVYWEIGHT_HANDLER 0x6e00
    598         HEAVYWEIGHT_HANDLER 0x6f00
    599 
    600         HEAVYWEIGHT_HANDLER 0x7000
    601         HEAVYWEIGHT_HANDLER 0x7100
    602         HEAVYWEIGHT_HANDLER 0x7200
    603         HEAVYWEIGHT_HANDLER 0x7300
    604         HEAVYWEIGHT_HANDLER 0x7400
    605         HEAVYWEIGHT_HANDLER 0x7500
    606         HEAVYWEIGHT_HANDLER 0x7600
    607         HEAVYWEIGHT_HANDLER 0x7700
    608         HEAVYWEIGHT_HANDLER 0x7800
    609         HEAVYWEIGHT_HANDLER 0x7900
    610         HEAVYWEIGHT_HANDLER 0x7a00
    611         HEAVYWEIGHT_HANDLER 0x7b00
    612         HEAVYWEIGHT_HANDLER 0x7c00
    613         HEAVYWEIGHT_HANDLER 0x7d00
    614         HEAVYWEIGHT_HANDLER 0x7e00
    615         HEAVYWEIGHT_HANDLER 0x7f00
     544        HEAVYWEIGHT_HANDLER 0x00
     545        HEAVYWEIGHT_HANDLER 0x04
     546        HEAVYWEIGHT_HANDLER 0x08
     547        HEAVYWEIGHT_HANDLER 0x0c
     548        HEAVYWEIGHT_HANDLER 0x10
     549        HEAVYWEIGHT_HANDLER 0x14
     550        HEAVYWEIGHT_HANDLER 0x18
     551        HEAVYWEIGHT_HANDLER 0x1c
     552        HEAVYWEIGHT_HANDLER 0x20
     553        HEAVYWEIGHT_HANDLER 0x24
     554        HEAVYWEIGHT_HANDLER 0x28
     555        HEAVYWEIGHT_HANDLER 0x2c break_instruction
     556        HEAVYWEIGHT_HANDLER 0x30
     557        HEAVYWEIGHT_HANDLER 0x34
     558        HEAVYWEIGHT_HANDLER 0x38
     559        HEAVYWEIGHT_HANDLER 0x3c
     560        HEAVYWEIGHT_HANDLER 0x40
     561        HEAVYWEIGHT_HANDLER 0x44
     562        HEAVYWEIGHT_HANDLER 0x48
     563        HEAVYWEIGHT_HANDLER 0x4c
     564
     565        HEAVYWEIGHT_HANDLER 0x50
     566        HEAVYWEIGHT_HANDLER 0x51
     567        HEAVYWEIGHT_HANDLER 0x52
     568        HEAVYWEIGHT_HANDLER 0x53
     569        HEAVYWEIGHT_HANDLER 0x54
     570        HEAVYWEIGHT_HANDLER 0x55
     571        HEAVYWEIGHT_HANDLER 0x56
     572        SPECULATION_VECTOR_HANDLER 0x57
     573        HEAVYWEIGHT_HANDLER 0x58
     574        HEAVYWEIGHT_HANDLER 0x59
     575        HEAVYWEIGHT_HANDLER 0x5a
     576        HEAVYWEIGHT_HANDLER 0x5b
     577        HEAVYWEIGHT_HANDLER 0x5c
     578        HEAVYWEIGHT_HANDLER 0x5d
     579        HEAVYWEIGHT_HANDLER 0x5e
     580        HEAVYWEIGHT_HANDLER 0x5f
     581       
     582        HEAVYWEIGHT_HANDLER 0x60
     583        HEAVYWEIGHT_HANDLER 0x61
     584        HEAVYWEIGHT_HANDLER 0x62
     585        HEAVYWEIGHT_HANDLER 0x63
     586        HEAVYWEIGHT_HANDLER 0x64
     587        HEAVYWEIGHT_HANDLER 0x65
     588        HEAVYWEIGHT_HANDLER 0x66
     589        HEAVYWEIGHT_HANDLER 0x67
     590        HEAVYWEIGHT_HANDLER 0x68
     591        HEAVYWEIGHT_HANDLER 0x69
     592        HEAVYWEIGHT_HANDLER 0x6a
     593        HEAVYWEIGHT_HANDLER 0x6b
     594        HEAVYWEIGHT_HANDLER 0x6c
     595        HEAVYWEIGHT_HANDLER 0x6d
     596        HEAVYWEIGHT_HANDLER 0x6e
     597        HEAVYWEIGHT_HANDLER 0x6f
     598
     599        HEAVYWEIGHT_HANDLER 0x70
     600        HEAVYWEIGHT_HANDLER 0x71
     601        HEAVYWEIGHT_HANDLER 0x72
     602        HEAVYWEIGHT_HANDLER 0x73
     603        HEAVYWEIGHT_HANDLER 0x74
     604        HEAVYWEIGHT_HANDLER 0x75
     605        HEAVYWEIGHT_HANDLER 0x76
     606        HEAVYWEIGHT_HANDLER 0x77
     607        HEAVYWEIGHT_HANDLER 0x78
     608        HEAVYWEIGHT_HANDLER 0x79
     609        HEAVYWEIGHT_HANDLER 0x7a
     610        HEAVYWEIGHT_HANDLER 0x7b
     611        HEAVYWEIGHT_HANDLER 0x7c
     612        HEAVYWEIGHT_HANDLER 0x7d
     613        HEAVYWEIGHT_HANDLER 0x7e
     614        HEAVYWEIGHT_HANDLER 0x7f

  • kernel/arch/ia64/src/mm/tlb.c

    reae91e0 r235d31d  
    477477/** Instruction TLB fault handler for faults with VHPT turned off.
    478478 *
    479  * @param vector Interruption vector.
    480  * @param istate Structure with saved interruption state.
    481  *
    482  */
    483 void alternate_instruction_tlb_fault(uint64_t vector, istate_t *istate)
     479 * @param n Interruption vector.
     480 * @param istate Structure with saved interruption state.
     481 *
     482 */
     483void alternate_instruction_tlb_fault(unsigned int n, istate_t *istate)
    484484{
    485485        uintptr_t va;
    … …  
    566566/** Data TLB fault handler for faults with VHPT turned off.
    567567 *
    568  * @param vector Interruption vector.
    569  * @param istate Structure with saved interruption state.
    570  *
    571  */
    572 void alternate_data_tlb_fault(uint64_t vector, istate_t *istate)
     568 * @param n Interruption vector.
     569 * @param istate Structure with saved interruption state.
     570 *
     571 */
     572void alternate_data_tlb_fault(unsigned int n, istate_t *istate)
    573573{
    574574        if (istate->cr_isr.sp) {
    … …  
    623623 * This fault should not occur.
    624624 *
    625  * @param vector Interruption vector.
    626  * @param istate Structure with saved interruption state.
    627  *
    628  */
    629 void data_nested_tlb_fault(uint64_t vector, istate_t *istate)
     625 * @param n Interruption vector.
     626 * @param istate Structure with saved interruption state.
     627 *
     628 */
     629void data_nested_tlb_fault(unsigned int n, istate_t *istate)
    630630{
    631631        ASSERT(false);
    … …  
    634634/** Data Dirty bit fault handler.
    635635 *
    636  * @param vector Interruption vector.
    637  * @param istate Structure with saved interruption state.
    638  *
    639  */
    640 void data_dirty_bit_fault(uint64_t vector, istate_t *istate)
     636 * @param n Interruption vector.
     637 * @param istate Structure with saved interruption state.
     638 *
     639 */
     640void data_dirty_bit_fault(unsigned int n, istate_t *istate)
    641641{
    642642        uintptr_t va;
    … …  
    665665/** Instruction access bit fault handler.
    666666 *
    667  * @param vector Interruption vector.
    668  * @param istate Structure with saved interruption state.
    669  *
    670  */
    671 void instruction_access_bit_fault(uint64_t vector, istate_t *istate)
     667 * @param n Interruption vector.
     668 * @param istate Structure with saved interruption state.
     669 *
     670 */
     671void instruction_access_bit_fault(unsigned int n, istate_t *istate)
    672672{
    673673        uintptr_t va;
    … …  
    694694/** Data access bit fault handler.
    695695 *
    696  * @param vector Interruption vector.
    697  * @param istate Structure with saved interruption state.
    698  *
    699  */
    700 void data_access_bit_fault(uint64_t vector, istate_t *istate)
     696 * @param n Interruption vector.
     697 * @param istate Structure with saved interruption state.
     698 *
     699 */
     700void data_access_bit_fault(unsigned int n, istate_t *istate)
    701701{
    702702        uintptr_t va;
    … …  
    729729/** Data access rights fault handler.
    730730 *
    731  * @param vector Interruption vector.
    732  * @param istate Structure with saved interruption state.
    733  *
    734  */
    735 void data_access_rights_fault(uint64_t vector, istate_t *istate)
     731 * @param n Interruption vector.
     732 * @param istate Structure with saved interruption state.
     733 *
     734 */
     735void data_access_rights_fault(unsigned int n, istate_t *istate)
    736736{
    737737        uintptr_t va;
    … …  
    753753/** Page not present fault handler.
    754754 *
    755  * @param vector Interruption vector.
    756  * @param istate Structure with saved interruption state.
    757  *
    758  */
    759 void page_not_present(uint64_t vector, istate_t *istate)
     755 * @param n Interruption vector.
     756 * @param istate Structure with saved interruption state.
     757 *
     758 */
     759void page_not_present(unsigned int n, istate_t *istate)
    760760{
    761761        uintptr_t va;

  • kernel/arch/mips32/Makefile.inc

    reae91e0 r235d31d  
    7171        arch/$(KARCH)/src/fpu_context.c \
    7272        arch/$(KARCH)/src/smp/smp.c \
     73        arch/$(KARCH)/src/smp/smp_call.c \
    7374        arch/$(KARCH)/src/machine_func.c
    7475

  • kernel/arch/sparc32/include/arch/stack.h

    reae91e0 r235d31d  
    5454#define STACK_ARG_SAVE_AREA_SIZE  (6 * STACK_ITEM_SIZE)
    5555
    56 /**
    57  * Offsets of arguments on stack.
    58  */
    59 #define STACK_ARG0  0
    60 #define STACK_ARG1  4
    61 #define STACK_ARG2  8
    62 #define STACK_ARG3  12
    63 #define STACK_ARG4  16
    64 #define STACK_ARG5  20
    65 #define STACK_ARG6  24
    66 
    6756#endif
    6857

  • kernel/arch/sparc32/src/cpu/cpu.c

    reae91e0 r235d31d  
    3434
    3535#include <arch/cpu.h>
     36#include <cpu.h>
    3637#include <arch.h>
    3738#include <typedefs.h>

  • kernel/arch/sparc32/src/debug/stacktrace.c

    reae91e0 r235d31d  
    3939#include <arch.h>
    4040#include <arch/stack.h>
     41#include <proc/thread.h>
    4142
    4243#define FRAME_OFFSET_FP_PREV  14

  • kernel/arch/sparc32/src/sparc32.c

    reae91e0 r235d31d  
    3737#include <arch/interrupt.h>
    3838#include <arch/asm.h>
     39#include <arch/barrier.h>
    3940#include <arch/machine_func.h>
    4041#include <func.h>
    … …  
    169170}
    170171
     172bool __atomic_compare_exchange_4(uint32_t *ptr, uint32_t *expected,
     173    uint32_t desired, bool weak, int success_mm, int failure_mm)
     174{
     175        ipl_t ipl;
     176        bool success;
     177
     178        /* XXX: This is a rather dummy implementation. */
     179
     180        ipl = interrupts_disable();
     181        memory_barrier();
     182        if (*ptr == *expected) {
     183                success = true;
     184                *ptr = desired;
     185        } else {
     186                success = false;
     187                *expected = *ptr;
     188        }
     189        memory_barrier();
     190        interrupts_restore(ipl);
     191
     192        return success;
     193}
     194
    171195/** @}
    172196 */

  • kernel/arch/sparc64/Makefile.inc

    reae91e0 r235d31d  
    100100        ARCH_SOURCES += \
    101101                arch/$(KARCH)/src/smp/$(USARCH)/smp.c \
     102                arch/$(KARCH)/src/smp/$(USARCH)/smp_call.c \
    102103                arch/$(KARCH)/src/smp/$(USARCH)/ipi.c
    103104endif

  • kernel/arch/sparc64/include/arch/barrier.h

    reae91e0 r235d31d  
    3737
    3838#include <trace.h>
     39
     40#ifdef KERNEL
     41#include <arch/common.h>
     42#else
     43#include <libarch/common.h>
     44#endif
    3945
    4046/*

  • kernel/arch/sparc64/include/arch/interrupt.h

    reae91e0 r235d31d  
    4040#include <arch/istate.h>
    4141
    42 #define IVT_ITEMS  15
    43 #define IVT_FIRST  1
     42#define IVT_ITEMS  512
     43#define IVT_FIRST  0
    4444
    4545/* This needs to be defined for inter-architecture API portability. */
    … …  
    4747
    4848enum {
    49         IPI_TLB_SHOOTDOWN = VECTOR_TLB_SHOOTDOWN_IPI
     49        IPI_TLB_SHOOTDOWN = VECTOR_TLB_SHOOTDOWN_IPI,
     50        IPI_SMP_CALL
    5051};
     52
     53extern void exc_arch_init(void);
    5154
    5255#endif

  • kernel/arch/sparc64/include/arch/istate_struct.ag

    reae91e0 r235d31d  
    4141
    4242        members : [
     43
     44                #
     45                # Window save area for locals and inputs. Required by ABI.
     46                # Before using these, make sure that the corresponding register
     47                # window has been spilled into memory, otherwise l0-l7 and
     48                # i0-i7 will have undefined values.
     49                #
     50                {
     51                        name : l0,
     52                        type : uint64_t,
     53                },
     54                {
     55                        name : l1,
     56                        type : uint64_t,
     57                },
     58                {
     59                        name : l2,
     60                        type : uint64_t,
     61                },
     62                {
     63                        name : l3,
     64                        type : uint64_t,
     65                },
     66                {
     67                        name : l4,
     68                        type : uint64_t,
     69                },
     70                {
     71                        name : l5,
     72                        type : uint64_t,
     73                },
     74                {
     75                        name : l6,
     76                        type : uint64_t,
     77                },
     78                {
     79                        name : l7,
     80                        type : uint64_t,
     81                },
     82                {
     83                        name : i0,
     84                        type : uint64_t,
     85                },
     86                {
     87                        name : i1,
     88                        type : uint64_t,
     89                },
     90                {
     91                        name : i2,
     92                        type : uint64_t,
     93                },
     94                {
     95                        name : i3,
     96                        type : uint64_t,
     97                },
     98                {
     99                        name : i4,
     100                        type : uint64_t,
     101                },
     102                {
     103                        name : i5,
     104                        type : uint64_t,
     105                },
     106                {
     107                        name : i6,
     108                        type : uint64_t,
     109                },
     110                {
     111                        name : i7,
     112                        type : uint64_t,
     113                },
     114
     115                #
     116                # Six mandatory argument slots, required by the ABI, plus an
     117                # optional argument slot for the 7th argument used by our
     118                # syscalls. Since the preemptible handler is always passing
     119                # integral arguments, undef_arg[0] - undef_arg[5] are always
     120                # undefined.
     121                #
     122                {
     123                        name : undef_arg,
     124                        type : uint64_t,
     125                        elements : 6,
     126                },
     127                {
     128                        name : arg6,
     129                        type : uint64_t,
     130                },
     131
     132                #
     133                # From this point onwards, the istate layout is not dicated by
     134                # the ABI. The only requirement is the stack alignment.
     135                #
     136
    43137                {
    44138                        name : tnpc,
    … …  
    51145                {
    52146                        name : tstate,
     147                        type : uint64_t
     148                },
     149                {
     150                        name : y,
     151                        type : uint64_t,
     152                },
     153
     154                #
     155                # At the moment, these are defined only when needed by the
     156                # preemptible handler, so consider them undefined for now.
     157                #
     158                {
     159                        name : o0,
     160                        type : uint64_t,
     161                },
     162                {
     163                        name : o1,
     164                        type : uint64_t,
     165                },
     166                {
     167                        name : o2,
     168                        type : uint64_t,
     169                },
     170                {
     171                        name : o3,
     172                        type : uint64_t,
     173                },
     174                {
     175                        name : o4,
     176                        type : uint64_t,
     177                },
     178                {
     179                        name : o5,
     180                        type : uint64_t,
     181                },
     182                {
     183                        name : o6,
     184                        type : uint64_t,
     185                },
     186                {
     187                        name : o7,
     188                        type : uint64_t,
     189                },
     190
     191                #
     192                # I/DTLB Tag Access register or zero for non-MMU traps.
     193                #
     194                {
     195                        name : tlb_tag_access,
    53196                        type : uint64_t
    54197                }

  • kernel/arch/sparc64/include/arch/mm/sun4u/tlb.h

    reae91e0 r235d31d  
    678678}
    679679
    680 extern void fast_instruction_access_mmu_miss(sysarg_t, istate_t *);
    681 extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t, istate_t *);
    682 extern void fast_data_access_protection(tlb_tag_access_reg_t , istate_t *);
     680extern void fast_instruction_access_mmu_miss(unsigned int, istate_t *);
     681extern void fast_data_access_mmu_miss(unsigned int, istate_t *);
     682extern void fast_data_access_protection(unsigned int, istate_t *);
    683683
    684684extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool);

  • kernel/arch/sparc64/include/arch/mm/sun4v/tlb.h

    reae91e0 r235d31d  
    141141}
    142142
    143 extern void fast_instruction_access_mmu_miss(sysarg_t, istate_t *);
    144 extern void fast_data_access_mmu_miss(sysarg_t, istate_t *);
    145 extern void fast_data_access_protection(sysarg_t, istate_t *);
     143extern void fast_instruction_access_mmu_miss(unsigned int, istate_t *);
     144extern void fast_data_access_mmu_miss(unsigned int, istate_t *);
     145extern void fast_data_access_protection(unsigned int, istate_t *);
    146146
    147147extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool);

  • kernel/arch/sparc64/include/arch/trap/exception.h

    reae91e0 r235d31d  
    7171extern void dump_istate(istate_t *istate);
    7272
    73 extern void instruction_access_exception(int n, istate_t *istate);
    74 extern void instruction_access_error(int n, istate_t *istate);
    75 extern void illegal_instruction(int n, istate_t *istate);
    76 extern void privileged_opcode(int n, istate_t *istate);
    77 extern void unimplemented_LDD(int n, istate_t *istate);
    78 extern void unimplemented_STD(int n, istate_t *istate);
    79 extern void fp_disabled(int n, istate_t *istate);
    80 extern void fp_exception_ieee_754(int n, istate_t *istate);
    81 extern void fp_exception_other(int n, istate_t *istate);
    82 extern void tag_overflow(int n, istate_t *istate);
    83 extern void division_by_zero(int n, istate_t *istate);
    84 extern void data_access_exception(int n, istate_t *istate);
    85 extern void data_access_error(int n, istate_t *istate);
    86 extern void mem_address_not_aligned(int n, istate_t *istate);
    87 extern void LDDF_mem_address_not_aligned(int n, istate_t *istate);
    88 extern void STDF_mem_address_not_aligned(int n, istate_t *istate);
    89 extern void privileged_action(int n, istate_t *istate);
    90 extern void LDQF_mem_address_not_aligned(int n, istate_t *istate);
    91 extern void STQF_mem_address_not_aligned(int n, istate_t *istate);
     73extern void instruction_access_exception(unsigned int, istate_t *);
     74extern void instruction_access_error(unsigned int, istate_t *);
     75extern void illegal_instruction(unsigned int, istate_t *);
     76extern void privileged_opcode(unsigned int, istate_t *);
     77extern void unimplemented_LDD(unsigned int, istate_t *);
     78extern void unimplemented_STD(unsigned int, istate_t *);
     79extern void fp_disabled(unsigned int, istate_t *);
     80extern void fp_exception_ieee_754(unsigned int, istate_t *);
     81extern void fp_exception_other(unsigned int, istate_t *);
     82extern void tag_overflow(unsigned int, istate_t *);
     83extern void division_by_zero(unsigned int, istate_t *);
     84extern void data_access_exception(unsigned int, istate_t *);
     85extern void data_access_error(unsigned int, istate_t *);
     86extern void mem_address_not_aligned(unsigned int, istate_t *);
     87extern void LDDF_mem_address_not_aligned(unsigned int, istate_t *);
     88extern void STDF_mem_address_not_aligned(unsigned int, istate_t *);
     89extern void privileged_action(unsigned int, istate_t *);
     90extern void LDQF_mem_address_not_aligned(unsigned int, istate_t *);
     91extern void STQF_mem_address_not_aligned(unsigned int, istate_t *);
    9292
    9393#endif /* !__ASM__ */

  • kernel/arch/sparc64/include/arch/trap/interrupt.h

    reae91e0 r235d31d  
    6363#define IGN_SHIFT       6
    6464
    65 
    66 #ifdef __ASM__
    67 .macro INTERRUPT_LEVEL_N_HANDLER n
    68         mov \n - 1, %g2
    69         PREEMPTIBLE_HANDLER exc_dispatch
    70 .endm
    71 #endif
    72 
    7365#ifndef __ASM__
    7466
    7567#include <arch/interrupt.h>
    7668
    77 extern void interrupt(int n, istate_t *istate);
     69extern void interrupt(unsigned int n, istate_t *istate);
     70
    7871#endif /* !def __ASM__ */
    7972

  • kernel/arch/sparc64/include/arch/trap/sun4u/interrupt.h

    reae91e0 r235d31d  
    9292#define INTERRUPT_VECTOR_TRAP_HANDLER_SIZE      TRAP_TABLE_ENTRY_SIZE
    9393
    94 #ifdef __ASM__
    95 .macro INTERRUPT_VECTOR_TRAP_HANDLER
    96         PREEMPTIBLE_HANDLER interrupt
    97 .endm
    98 #endif /* __ASM__ */
    99 
    100 
    10194#endif
    10295

  • kernel/arch/sparc64/include/arch/trap/sun4u/mmu.h

    reae91e0 r235d31d  
    74740:
    7575        wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
    76         PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss
     76        mov TT_FAST_INSTRUCTION_ACCESS_MMU_MISS, %g2
     77        mov VA_IMMU_TAG_ACCESS, %g5
     78        ldxa [%g5] ASI_IMMU, %g5                        ! read the faulting Context and VPN
     79        PREEMPTIBLE_HANDLER exc_dispatch
    7780.endm
    7881
    … …  
    107110        wr %g0, ASI_DMMU, %asi
    108111        ldxa [VA_DMMU_TAG_ACCESS] %asi, %g1             ! read the faulting Context and VPN
    109         set TLB_TAG_ACCESS_CONTEXT_MASK, %g2
     112        ldx [%g7 + %lo(tlb_tag_access_context_mask)], %g2
    110113        andcc %g1, %g2, %g3                             ! get Context
    111114        bnz %xcc, 0f                                    ! Context is non-zero
    … …  
    138141        wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
    139142
    140         /*
    141          * Read the Tag Access register for the higher-level handler.
    142          * This is necessary to survive nested DTLB misses.
    143          */     
    144         ldxa [VA_DMMU_TAG_ACCESS] %asi, %g2
    145 
    146         /*
    147          * g2 will be passed as an argument to fast_data_access_mmu_miss().
    148          */
    149         PREEMPTIBLE_HANDLER fast_data_access_mmu_miss
     143        mov TT_FAST_DATA_ACCESS_MMU_MISS, %g2
     144        ldxa [VA_DMMU_TAG_ACCESS] %asi, %g5             ! read the faulting Context and VPN
     145        PREEMPTIBLE_HANDLER exc_dispatch
    150146.endm
    151147
    … …  
    164160        wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
    165161
    166         /*
    167          * Read the Tag Access register for the higher-level handler.
    168          * This is necessary to survive nested DTLB misses.
    169          */     
    170         mov VA_DMMU_TAG_ACCESS, %g2
    171         ldxa [%g2] ASI_DMMU, %g2
    172 
    173         /*
    174          * g2 will be passed as an argument to fast_data_access_mmu_miss().
    175          */
    176         PREEMPTIBLE_HANDLER fast_data_access_protection
     162        mov TT_FAST_DATA_ACCESS_PROTECTION, %g2
     163        mov VA_DMMU_TAG_ACCESS, %g5
     164        ldxa [%g5] ASI_DMMU, %g5                        ! read the faulting Context and VPN
     165        PREEMPTIBLE_HANDLER exc_dispatch
    177166.endm
    178167

  • kernel/arch/sparc64/include/arch/trap/sun4v/interrupt.h

    reae91e0 r235d31d  
    4040#ifndef __ASM__
    4141
     42#include <arch/istate_struct.h>
     43
    4244extern void sun4v_ipi_init(void);
    43 extern void cpu_mondo(void);
     45extern void cpu_mondo(unsigned int, istate_t *);
    4446
    4547#endif

  • kernel/arch/sparc64/include/arch/trap/sun4v/mmu.h

    reae91e0 r235d31d  
    7373
    7474.macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
    75         PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss
     75        mov TT_FAST_INSTRUCTION_ACCESS_MMU_MISS, %g2
     76        clr %g5         ! XXX
     77        PREEMPTIBLE_HANDLER exc_dispatch
    7678.endm
    7779
    … …  
    123125         * mapped. In such a case, this handler will be called from TL = 1.
    124126         * We handle the situation by pretending that the MMU miss occurred
    125          * on TL = 0. Once the MMU miss trap is services, the instruction which
     127         * on TL = 0. Once the MMU miss trap is serviced, the instruction which
    126128         * caused the spill/fill trap is restarted, the spill/fill trap occurs,
    127          * but this time its handler accesse memory which IS mapped.
     129         * but this time its handler accesses memory which is mapped.
    128130         */
    129131        .if (\tl > 0)
    … …  
    131133        .endif
    132134
     135        mov TT_FAST_DATA_ACCESS_MMU_MISS, %g2
     136
    133137        /*
    134          * Save the faulting virtual page and faulting context to the %g2
    135          * register. The most significant 51 bits of the %g2 register will
     138         * Save the faulting virtual page and faulting context to the %g5
     139         * register. The most significant 51 bits of the %g5 register will
    136140         * contain the virtual address which caused the fault truncated to the
    137          * page boundary. The least significant 13 bits of the %g2 register
     141         * page boundary. The least significant 13 bits of the %g5 register
    138142         * will contain the number of the context in which the fault occurred.
    139          * The value of the %g2 register will be passed as a parameter to the
    140          * higher level service routine.
     143         * The value of the %g5 register will be stored in the istate structure
     144         * for inspeciton by the higher level service routine.
    141145         */
    142         or %g1, %g3, %g2
     146        or %g1, %g3, %g5
    143147
    144         PREEMPTIBLE_HANDLER fast_data_access_mmu_miss
     148        PREEMPTIBLE_HANDLER exc_dispatch
    145149.endm
    146150
    … …  
    170174        sllx %g1, TTE_DATA_TADDR_OFFSET, %g1
    171175
     176        mov TT_FAST_DATA_ACCESS_PROTECTION, %g2
     177
    172178        /* the same as for FAST_DATA_ACCESS_MMU_MISS_HANDLER */
    173         or %g1, %g3, %g2
     179        or %g1, %g3, %g5
    174180
    175         PREEMPTIBLE_HANDLER fast_data_access_protection
     181        PREEMPTIBLE_HANDLER exc_dispatch
    176182.endm
    177183#endif /* __ASM__ */

  • kernel/arch/sparc64/include/arch/trap/trap_table.h

    reae91e0 r235d31d  
    4343#define TRAP_TABLE_SIZE         (TRAP_TABLE_ENTRY_COUNT * TRAP_TABLE_ENTRY_SIZE)
    4444
    45 #define ISTATE_END_OFFSET(o)    ((o) - ISTATE_SIZE)
    46 
    47 /*
    48  * The one STACK_ITEM_SIZE is counted for space holding the 7th
    49  * argument to syscall_handler (i.e. syscall number) and the other
    50  * STACK_ITEM_SIZE is counted because of the required alignment.
    51  */
    52 #define PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE \
    53     (STACK_WINDOW_SAVE_AREA_SIZE + STACK_ARG_SAVE_AREA_SIZE + \
    54     (2 * STACK_ITEM_SIZE) + (ISTATE_SIZE + 9 * 8))
    55 /* <-- istate_t ends here */
    56 #define SAVED_TSTATE    ISTATE_END_OFFSET(ISTATE_OFFSET_TSTATE)
    57 #define SAVED_TPC       ISTATE_END_OFFSET(ISTATE_OFFSET_TPC)
    58 #define SAVED_TNPC      ISTATE_END_OFFSET(ISTATE_OFFSET_TNPC)
    59 /* <-- istate_t begins here */
    60 #define SAVED_Y         -(1 * 8 + ISTATE_SIZE)
    61 #define SAVED_I0        -(2 * 8 + ISTATE_SIZE)
    62 #define SAVED_I1        -(3 * 8 + ISTATE_SIZE)
    63 #define SAVED_I2        -(4 * 8 + ISTATE_SIZE)
    64 #define SAVED_I3        -(5 * 8 + ISTATE_SIZE)
    65 #define SAVED_I4        -(6 * 8 + ISTATE_SIZE)
    66 #define SAVED_I5        -(7 * 8 + ISTATE_SIZE)
    67 #define SAVED_I6        -(8 * 8 + ISTATE_SIZE)
    68 #define SAVED_I7        -(9 * 8 + ISTATE_SIZE)
    69 
    7045#ifndef __ASM__
    7146
    … …  
    8055extern trap_table_entry_t trap_table[TRAP_TABLE_ENTRY_COUNT];
    8156extern trap_table_entry_t trap_table_save[TRAP_TABLE_ENTRY_COUNT];
     57
    8258#endif /* !__ASM__ */
    8359

  • kernel/arch/sparc64/src/debug/stacktrace.c

    reae91e0 r235d31d  
    3636#include <syscall/copy.h>
    3737#include <typedefs.h>
     38#include <proc/thread.h>
    3839
    3940#include <arch.h>
    4041#include <arch/stack.h>
    4142#include <arch/trap/trap_table.h>
     43
     44#include <arch/istate_struct.h>
    4245
    4346#if defined(SUN4V)
    … …  
    6164
    6265        kstack += STACK_BIAS;
    63         kstack -= PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE;
     66        kstack -= ISTATE_SIZE;
    6467
    6568        if (THREAD && (ctx->fp == kstack))

  • kernel/arch/sparc64/src/drivers/tick.c

    reae91e0 r235d31d  
    3535#include <arch/drivers/tick.h>
    3636#include <arch/interrupt.h>
     37#include <arch/trap/interrupt.h>
    3738#include <arch/sparc64.h>
    3839#include <arch/asm.h>
    … …  
    5152        softint_reg_t clear;
    5253
    53         interrupt_register(14, "tick_int", tick_interrupt);
    5454        compare.int_dis = false;
    5555        compare.tick_cmpr = tick_counter_read() +
    … …  
    7979/** Process tick interrupt.
    8080 *
    81  * @param n      Interrupt Level (14, can be ignored)
     81 * @param n      Trap type (0x4e, can be ignored)
    8282 * @param istate Interrupted state.
    8383 *
    … …  
    9393         * Make sure we are servicing interrupt_level_14
    9494         */
    95         ASSERT(n == 14);
     95        ASSERT(n == TT_INTERRUPT_LEVEL_14);
    9696       
    9797        /*

  • kernel/arch/sparc64/src/mm/sun4u/tlb.c

    reae91e0 r235d31d  
    194194
    195195/** ITLB miss handler. */
    196 void fast_instruction_access_mmu_miss(sysarg_t unused, istate_t *istate)
     196void fast_instruction_access_mmu_miss(unsigned int tt, istate_t *istate)
    197197{
    198198        size_t index = (istate->tpc >> MMU_PAGE_WIDTH) % MMU_PAGES_PER_PAGE;
    … …  
    224224 * low-level, assembly language part of the fast_data_access_mmu_miss handler.
    225225 *
    226  * @param tag           Content of the TLB Tag Access register as it existed
    227  *                      when the trap happened. This is to prevent confusion
    228  *                      created by clobbered Tag Access register during a nested
    229  *                      DTLB miss.
     226 * @param tt            Trap type.
    230227 * @param istate        Interrupted state saved on the stack.
    231228 */
    232 void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate)
    233 {
     229void fast_data_access_mmu_miss(unsigned int tt, istate_t *istate)
     230{
     231        tlb_tag_access_reg_t tag;
    234232        uintptr_t page_8k;
    235233        uintptr_t page_16k;
    … …  
    238236        as_t *as = AS;
    239237
     238        tag.value = istate->tlb_tag_access;
    240239        page_8k = (uint64_t) tag.vpn << MMU_PAGE_WIDTH;
    241240        page_16k = ALIGN_DOWN(page_8k, PAGE_SIZE);
    … …  
    276275/** DTLB protection fault handler.
    277276 *
    278  * @param tag           Content of the TLB Tag Access register as it existed
    279  *                      when the trap happened. This is to prevent confusion
    280  *                      created by clobbered Tag Access register during a nested
    281  *                      DTLB miss.
     277 * @param tt            Trap type.
    282278 * @param istate        Interrupted state saved on the stack.
    283279 */
    284 void fast_data_access_protection(tlb_tag_access_reg_t tag, istate_t *istate)
    285 {
     280void fast_data_access_protection(unsigned int tt, istate_t *istate)
     281{
     282        tlb_tag_access_reg_t tag;
    286283        uintptr_t page_16k;
    287284        size_t index;
    … …  
    289286        as_t *as = AS;
    290287
     288        tag.value = istate->tlb_tag_access;
    291289        page_16k = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE);
    292290        index = tag.vpn % MMU_PAGES_PER_PAGE;   /* 16K-page emulation */

  • kernel/arch/sparc64/src/mm/sun4v/tlb.c

    reae91e0 r235d31d  
    208208
    209209/** ITLB miss handler. */
    210 void fast_instruction_access_mmu_miss(sysarg_t unused, istate_t *istate)
     210void fast_instruction_access_mmu_miss(unsigned int tt, istate_t *istate)
    211211{
    212212        uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);
    … …  
    239239 * low-level, assembly language part of the fast_data_access_mmu_miss handler.
    240240 *
    241  * @param page_and_ctx  A 64-bit value describing the fault. The most
    242  *                      significant 51 bits of the value contain the virtual
    243  *                      address which caused the fault truncated to the page
    244  *                      boundary. The least significant 13 bits of the value
    245  *                      contain the number of the context in which the fault
    246  *                      occurred.
     241 * @param tt            Trap type.
    247242 * @param istate        Interrupted state saved on the stack.
    248243 */
    249 void fast_data_access_mmu_miss(uint64_t page_and_ctx, istate_t *istate)
     244void fast_data_access_mmu_miss(unsigned int tt, istate_t *istate)
    250245{
    251246        pte_t *t;
    252         uintptr_t va = DMISS_ADDRESS(page_and_ctx);
    253         uint16_t ctx = DMISS_CONTEXT(page_and_ctx);
     247        uintptr_t va = DMISS_ADDRESS(istate->tlb_tag_access);
     248        uint16_t ctx = DMISS_CONTEXT(istate->tlb_tag_access);
    254249        as_t *as = AS;
    255250
    … …  
    288283/** DTLB protection fault handler.
    289284 *
    290  * @param page_and_ctx  A 64-bit value describing the fault. The most
    291  *                      significant 51 bits of the value contain the virtual
    292  *                      address which caused the fault truncated to the page
    293  *                      boundary. The least significant 13 bits of the value
    294  *                      contain the number of the context in which the fault
    295  *                      occurred.
     285 * @param tt            Trap type.
    296286 * @param istate        Interrupted state saved on the stack.
    297287 */
    298 void fast_data_access_protection(uint64_t page_and_ctx, istate_t *istate)
     288void fast_data_access_protection(unsigned int tt, istate_t *istate)
    299289{
    300290        pte_t *t;
    301         uintptr_t va = DMISS_ADDRESS(page_and_ctx);
    302         uint16_t ctx = DMISS_CONTEXT(page_and_ctx);
     291        uintptr_t va = DMISS_ADDRESS(istate->tlb_tag_access);
     292        uint16_t ctx = DMISS_CONTEXT(istate->tlb_tag_access);
    303293        as_t *as = AS;
    304294

  • kernel/arch/sparc64/src/smp/sun4u/ipi.c

    reae91e0 r235d31d  
    3434
    3535#include <smp/ipi.h>
     36#include <arch/smp/sun4u/ipi.h>
    3637#include <cpu.h>
    3738#include <arch.h>
    … …  
    4041#include <config.h>
    4142#include <mm/tlb.h>
     43#include <smp/smp_call.h>
    4244#include <arch/interrupt.h>
    4345#include <arch/trap/interrupt.h>
    … …  
    171173}
    172174
     175
     176/*
     177 * Deliver an IPI to the specified processors (except the current one).
     178 *
     179 * Interrupts must be disabled.
     180 *
     181 * @param cpu_id Destination cpu id (index into cpus array). Must not
     182 *               be the current cpu.
     183 * @param ipi    IPI number.
     184 */
     185void ipi_unicast_arch(unsigned int cpu_id, int ipi)
     186{
     187        ASSERT(&cpus[cpu_id] != CPU);
     188       
     189        if (ipi == IPI_SMP_CALL) {
     190                cross_call(cpus[cpu_id].arch.mid, smp_call_ipi_recv);
     191        } else {
     192                panic("Unknown IPI (%d).\n", ipi);
     193                return;
     194        }
     195}
     196
    173197/** @}
    174198 */

  • kernel/arch/sparc64/src/sun4u/sparc64.c

    reae91e0 r235d31d  
    8686void arch_pre_mm_init(void)
    8787{
    88         if (config.cpu_active == 1)
     88        if (config.cpu_active == 1) {
    8989                trap_init();
     90                exc_arch_init();
     91        }
    9092}
    9193

  • kernel/arch/sparc64/src/sun4u/start.S

    reae91e0 r235d31d  
    401401
    402402/*
    403  * The fast_data_access_mmu_miss_data_hi label and the end_of_identity and
    404  * kernel_8k_tlb_data_template variables are meant to stay together,
    405  * aligned on 16B boundary.
     403 * The fast_data_access_mmu_miss_data_hi label, the end_of_identity,
     404 * kernel_8k_tlb_data_template and tlb_tag_access_context_mask variables
     405 * are meant to stay together, aligned on a 32B boundary.
    406406 */
    407407.global fast_data_access_mmu_miss_data_hi
    408408.global end_of_identity
    409409.global kernel_8k_tlb_data_template
    410 
    411 .align 16
     410.global tlb_tag_access_context_mask
     411
     412.align 32
    412413/*
    413414 * This label is used by the fast_data_access_MMU_miss trap handler.
    … …  
    435436#endif /* CONFIG_VIRT_IDX_DCACHE */
    436437
     438/*
     439 * This variable is used by the fast_data_access_MMU_miss trap handler.
     440 * It allows us to save one precious instruction slot of this handler.
     441 */
     442tlb_tag_access_context_mask:
     443        .quad TLB_TAG_ACCESS_CONTEXT_MASK
     444

  • kernel/arch/sparc64/src/sun4v/sparc64.c

    reae91e0 r235d31d  
    8484void arch_pre_mm_init(void)
    8585{
    86         if (config.cpu_active == 1)
     86        if (config.cpu_active == 1) {
    8787                trap_init();
     88                exc_arch_init();
     89        }
    8890}
    8991

  • kernel/arch/sparc64/src/trap/exception.c

    reae91e0 r235d31d  
    5555
    5656/** Handle instruction_access_exception. (0x8) */
    57 void instruction_access_exception(int n, istate_t *istate)
     57void instruction_access_exception(unsigned int n, istate_t *istate)
    5858{
    5959        fault_if_from_uspace(istate, "%s.", __func__);
    … …  
    6262
    6363/** Handle instruction_access_error. (0xa) */
    64 void instruction_access_error(int n, istate_t *istate)
     64void instruction_access_error(unsigned int n, istate_t *istate)
    6565{
    6666        fault_if_from_uspace(istate, "%s.", __func__);
    … …  
    6969
    7070/** Handle illegal_instruction. (0x10) */
    71 void illegal_instruction(int n, istate_t *istate)
     71void illegal_instruction(unsigned int n, istate_t *istate)
    7272{
    7373        fault_if_from_uspace(istate, "%s.", __func__);
    … …  
    7676
    7777/** Handle privileged_opcode. (0x11) */
    78 void privileged_opcode(int n, istate_t *istate)
     78void privileged_opcode(unsigned int n, istate_t *istate)
    7979{
    8080        fault_if_from_uspace(istate, "%s.", __func__);
    … …  
    8383
    8484/** Handle unimplemented_LDD. (0x12) */
    85 void unimplemented_LDD(int n, istate_t *istate)
     85void unimplemented_LDD(unsigned int n, istate_t *istate)
    8686{
    8787        fault_if_from_uspace(istate, "%s.", __func__);
    … …  
    9090
    9191/** Handle unimplemented_STD. (0x13) */
    92 void unimplemented_STD(int n, istate_t *istate)
     92void unimplemented_STD(unsigned int n, istate_t *istate)
    9393{
    9494        fault_if_from_uspace(istate, "%s.", __func__);
    … …  
    9797
    9898/** Handle fp_disabled. (0x20) */
    99 void fp_disabled(int n, istate_t *istate)
     99void fp_disabled(unsigned int n, istate_t *istate)
    100100{
    101101        fprs_reg_t fprs;
    … …  
    117117
    118118/** Handle fp_exception_ieee_754. (0x21) */
    119 void fp_exception_ieee_754(int n, istate_t *istate)
     119void fp_exception_ieee_754(unsigned int n, istate_t *istate)
    120120{
    121121        fault_if_from_uspace(istate, "%s.", __func__);
    … …  
    124124
    125125/** Handle fp_exception_other. (0x22) */
    126 void fp_exception_other(int n, istate_t *istate)
     126void fp_exception_other(unsigned int n, istate_t *istate)
    127127{
    128128        fault_if_from_uspace(istate, "%s.", __func__);
    … …  
    131131
    132132/** Handle tag_overflow. (0x23) */
    133 void tag_overflow(int n, istate_t *istate)
     133void tag_overflow(unsigned int n, istate_t *istate)
    134134{
    135135        fault_if_from_uspace(istate, "%s.", __func__);
    … …  
    138138
    139139/** Handle division_by_zero. (0x28) */
    140 void division_by_zero(int n, istate_t *istate)
     140void division_by_zero(unsigned int n, istate_t *istate)
    141141{
    142142        fault_if_from_uspace(istate, "%s.", __func__);
    … …  
    145145
    146146/** Handle data_access_exception. (0x30) */
    147 void data_access_exception(int n, istate_t *istate)
     147void data_access_exception(unsigned int n, istate_t *istate)
    148148{
    149149        fault_if_from_uspace(istate, "%s.", __func__);
    … …  
    152152
    153153/** Handle data_access_error. (0x32) */
    154 void data_access_error(int n, istate_t *istate)
     154void data_access_error(unsigned int n, istate_t *istate)
    155155{
    156156        fault_if_from_uspace(istate, "%s.", __func__);
    … …  
    159159
    160160/** Handle mem_address_not_aligned. (0x34) */
    161 void mem_address_not_aligned(int n, istate_t *istate)
     161void mem_address_not_aligned(unsigned int n, istate_t *istate)
    162162{
    163163        fault_if_from_uspace(istate, "%s.", __func__);
    … …  
    166166
    167167/** Handle LDDF_mem_address_not_aligned. (0x35) */
    168 void LDDF_mem_address_not_aligned(int n, istate_t *istate)
     168void LDDF_mem_address_not_aligned(unsigned int n, istate_t *istate)
    169169{
    170170        fault_if_from_uspace(istate, "%s.", __func__);
    … …  
    173173
    174174/** Handle STDF_mem_address_not_aligned. (0x36) */
    175 void STDF_mem_address_not_aligned(int n, istate_t *istate)
     175void STDF_mem_address_not_aligned(unsigned int n, istate_t *istate)
    176176{
    177177        fault_if_from_uspace(istate, "%s.", __func__);
    … …  
    180180
    181181/** Handle privileged_action. (0x37) */
    182 void privileged_action(int n, istate_t *istate)
     182void privileged_action(unsigned int n, istate_t *istate)
    183183{
    184184        fault_if_from_uspace(istate, "%s.", __func__);
    … …  
    187187
    188188/** Handle LDQF_mem_address_not_aligned. (0x38) */
    189 void LDQF_mem_address_not_aligned(int n, istate_t *istate)
     189void LDQF_mem_address_not_aligned(unsigned int n, istate_t *istate)
    190190{
    191191        fault_if_from_uspace(istate, "%s.", __func__);
    … …  
    194194
    195195/** Handle STQF_mem_address_not_aligned. (0x39) */
    196 void STQF_mem_address_not_aligned(int n, istate_t *istate)
     196void STQF_mem_address_not_aligned(unsigned int n, istate_t *istate)
    197197{
    198198        fault_if_from_uspace(istate, "%s.", __func__);

  • kernel/arch/sparc64/src/trap/interrupt.c

    reae91e0 r235d31d  
    3636#include <arch/interrupt.h>
    3737#include <arch/trap/interrupt.h>
     38#include <arch/trap/exception.h>
     39#include <arch/trap/mmu.h>
    3840#include <arch/sparc64.h>
    3941#include <interrupt.h>
    … …  
    4345#include <arch/asm.h>
    4446#include <arch/barrier.h>
     47#include <arch/drivers/tick.h>
    4548#include <print.h>
    4649#include <arch.h>
    … …  
    4952#include <synch/spinlock.h>
    5053
    51 /** Register Interrupt Level Handler.
    52  *
    53  * @param n       Interrupt Level (1 - 15).
    54  * @param name    Short descriptive string.
    55  * @param handler Handler.
    56  *
    57  */
    58 void interrupt_register(unsigned int n, const char *name, iroutine_t handler)
     54void exc_arch_init(void)
    5955{
    60         ASSERT(n >= IVT_FIRST);
    61         ASSERT(n <= IVT_ITEMS);
    62        
    63         exc_register(n - IVT_FIRST, name, true, handler);
     56        exc_register(TT_INSTRUCTION_ACCESS_EXCEPTION,
     57            "instruction_access_exception", false,
     58            instruction_access_exception);
     59        exc_register(TT_INSTRUCTION_ACCESS_ERROR,
     60            "instruction_access_error", false,
     61            instruction_access_error);
     62
     63#ifdef SUN4V
     64        exc_register(TT_IAE_UNAUTH_ACCESS,
     65            "iae_unauth_access", false,
     66            instruction_access_exception);
     67        exc_register(TT_IAE_NFO_PAGE,
     68            "iae_nfo_page", false,
     69            instruction_access_exception);
     70#endif
     71
     72        exc_register(TT_ILLEGAL_INSTRUCTION,
     73            "illegal_instruction", false,
     74            illegal_instruction);
     75        exc_register(TT_PRIVILEGED_OPCODE,
     76            "privileged_opcode", false,
     77            privileged_opcode);
     78        exc_register(TT_UNIMPLEMENTED_LDD,
     79            "unimplemented_LDD", false,
     80            unimplemented_LDD);
     81        exc_register(TT_UNIMPLEMENTED_STD,
     82            "unimplemented_STD", false,
     83            unimplemented_STD);
     84
     85#ifdef SUN4V
     86        exc_register(TT_DAE_INVALID_ASI,
     87            "dae_invalid_asi", false,
     88            data_access_exception);
     89        exc_register(TT_DAE_PRIVILEGE_VIOLATION,
     90            "dae_privilege_violation", false,
     91            data_access_exception);
     92        exc_register(TT_DAE_NC_PAGE,
     93            "dae_nc_page", false,
     94            data_access_exception);
     95        exc_register(TT_DAE_NC_PAGE,
     96            "dae_nc_page", false,
     97            data_access_exception);
     98        exc_register(TT_DAE_NFO_PAGE,
     99            "dae_nfo_page", false,
     100            data_access_exception);
     101#endif
     102
     103        exc_register(TT_FP_DISABLED,
     104            "fp_disabled", true,
     105            fp_disabled);
     106        exc_register(TT_FP_EXCEPTION_IEEE_754,
     107            "fp_exception_ieee_754", false,
     108            fp_exception_ieee_754);
     109        exc_register(TT_FP_EXCEPTION_OTHER,
     110            "fp_exception_other", false,
     111            fp_exception_other);
     112        exc_register(TT_TAG_OVERFLOW,
     113            "tag_overflow", false,
     114            tag_overflow);     
     115        exc_register(TT_DIVISION_BY_ZERO,
     116            "division_by_zero", false,
     117            division_by_zero);
     118        exc_register(TT_DATA_ACCESS_EXCEPTION,
     119            "data_access_exception", false,
     120            data_access_exception);
     121        exc_register(TT_DATA_ACCESS_ERROR,
     122            "data_access_error", false,
     123            data_access_error);
     124        exc_register(TT_MEM_ADDRESS_NOT_ALIGNED,
     125            "mem_address_not_aligned", false,
     126            mem_address_not_aligned);
     127        exc_register(TT_LDDF_MEM_ADDRESS_NOT_ALIGNED,
     128            "LDDF_mem_address_not_aligned", false,
     129            LDDF_mem_address_not_aligned);
     130        exc_register(TT_STDF_MEM_ADDRESS_NOT_ALIGNED,
     131            "STDF_mem_address_not_aligned", false,
     132            STDF_mem_address_not_aligned);
     133        exc_register(TT_PRIVILEGED_ACTION,
     134            "privileged_action", false,
     135            privileged_action);
     136        exc_register(TT_LDQF_MEM_ADDRESS_NOT_ALIGNED,
     137            "LDQF_mem_address_not_aligned", false,
     138            LDQF_mem_address_not_aligned);
     139        exc_register(TT_STQF_MEM_ADDRESS_NOT_ALIGNED,
     140            "STQF_mem_address_not_aligned", false,
     141            STQF_mem_address_not_aligned);
     142
     143        exc_register(TT_INTERRUPT_LEVEL_14,
     144            "interrupt_level_14", true,
     145            tick_interrupt);
     146
     147#ifdef SUN4U
     148        exc_register(TT_INTERRUPT_VECTOR_TRAP,
     149            "interrupt_vector_trap", true,
     150            interrupt);
     151#endif
     152
     153        exc_register(TT_FAST_INSTRUCTION_ACCESS_MMU_MISS,
     154            "fast_instruction_access_mmu_miss", true,
     155            fast_instruction_access_mmu_miss);
     156        exc_register(TT_FAST_DATA_ACCESS_MMU_MISS,
     157            "fast_data_access_mmu_miss", true,
     158            fast_data_access_mmu_miss);
     159        exc_register(TT_FAST_DATA_ACCESS_PROTECTION,
     160            "fast_data_access_protection", true,
     161            fast_data_access_protection);       
     162
     163#ifdef SUN4V
     164        exc_register(TT_CPU_MONDO,
     165            "cpu_mondo", true,
     166            cpu_mondo);
     167#endif
     168
    64169}
    65170

  • kernel/arch/sparc64/src/trap/sun4u/interrupt.c

    reae91e0 r235d31d  
    5353 * @param istate Ignored.
    5454 */
    55 void interrupt(int n, istate_t *istate)
     55void interrupt(unsigned int n, istate_t *istate)
    5656{
    5757        uint64_t status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);

  • kernel/arch/sparc64/src/trap/sun4u/trap_table.S

    reae91e0 r235d31d  
    6363instruction_access_exception_tl0:
    6464        wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
    65         PREEMPTIBLE_HANDLER instruction_access_exception
     65        mov TT_INSTRUCTION_ACCESS_EXCEPTION, %g2
     66        clr %g5
     67        PREEMPTIBLE_HANDLER exc_dispatch
    6668
    6769/* TT = 0x0a, TL = 0, instruction_access_error */
    … …  
    6971.global instruction_access_error_tl0
    7072instruction_access_error_tl0:
    71         PREEMPTIBLE_HANDLER instruction_access_error
     73        mov TT_INSTRUCTION_ACCESS_ERROR, %g2
     74        clr %g5
     75        PREEMPTIBLE_HANDLER exc_dispatch
    7276
    7377/* TT = 0x10, TL = 0, illegal_instruction */
    … …  
    7579.global illegal_instruction_tl0
    7680illegal_instruction_tl0:
    77         PREEMPTIBLE_HANDLER illegal_instruction
     81        mov TT_ILLEGAL_INSTRUCTION, %g2
     82        clr %g5
     83        PREEMPTIBLE_HANDLER exc_dispatch
    7884
    7985/* TT = 0x11, TL = 0, privileged_opcode */
    … …  
    8187.global privileged_opcode_tl0
    8288privileged_opcode_tl0:
    83         PREEMPTIBLE_HANDLER privileged_opcode
     89        mov TT_PRIVILEGED_OPCODE, %g2
     90        clr %g5
     91        PREEMPTIBLE_HANDLER exc_dispatch
    8492
    8593/* TT = 0x12, TL = 0, unimplemented_LDD */
    … …  
    8795.global unimplemented_LDD_tl0
    8896unimplemented_LDD_tl0:
    89         PREEMPTIBLE_HANDLER unimplemented_LDD
     97        mov TT_UNIMPLEMENTED_LDD, %g2
     98        clr %g5
     99        PREEMPTIBLE_HANDLER exc_dispatch
    90100
    91101/* TT = 0x13, TL = 0, unimplemented_STD */
    … …  
    93103.global unimplemented_STD_tl0
    94104unimplemented_STD_tl0:
    95         PREEMPTIBLE_HANDLER unimplemented_STD
     105        mov TT_UNIMPLEMENTED_STD, %g2
     106        clr %g5
     107        PREEMPTIBLE_HANDLER exc_dispatch
    96108
    97109/* TT = 0x20, TL = 0, fb_disabled handler */
    … …  
    99111.global fb_disabled_tl0
    100112fp_disabled_tl0:
    101         PREEMPTIBLE_HANDLER fp_disabled
     113        mov TT_FP_DISABLED, %g2
     114        clr %g5
     115        PREEMPTIBLE_HANDLER exc_dispatch
    102116
    103117/* TT = 0x21, TL = 0, fb_exception_ieee_754 handler */
    … …  
    105119.global fb_exception_ieee_754_tl0
    106120fp_exception_ieee_754_tl0:
    107         PREEMPTIBLE_HANDLER fp_exception_ieee_754
     121        mov TT_FP_EXCEPTION_IEEE_754, %g2
     122        clr %g5
     123        PREEMPTIBLE_HANDLER exc_dispatch
    108124
    109125/* TT = 0x22, TL = 0, fb_exception_other handler */
    … …  
    111127.global fb_exception_other_tl0
    112128fp_exception_other_tl0:
    113         PREEMPTIBLE_HANDLER fp_exception_other
     129        mov TT_FP_EXCEPTION_OTHER, %g2
     130        clr %g5
     131        PREEMPTIBLE_HANDLER exc_dispatch
    114132
    115133/* TT = 0x23, TL = 0, tag_overflow */
    … …  
    117135.global tag_overflow_tl0
    118136tag_overflow_tl0:
    119         PREEMPTIBLE_HANDLER tag_overflow
     137        mov TT_TAG_OVERFLOW, %g2
     138        clr %g5
     139        PREEMPTIBLE_HANDLER exc_dispatch
    120140
    121141/* TT = 0x24, TL = 0, clean_window handler */
    … …  
    129149.global division_by_zero_tl0
    130150division_by_zero_tl0:
    131         PREEMPTIBLE_HANDLER division_by_zero
     151        mov TT_DIVISION_BY_ZERO, %g2
     152        clr %g5
     153        PREEMPTIBLE_HANDLER exc_dispatch
    132154
    133155/* TT = 0x30, TL = 0, data_access_exception */
    … …  
    136158data_access_exception_tl0:
    137159        wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
    138         PREEMPTIBLE_HANDLER data_access_exception
     160        mov TT_DATA_ACCESS_EXCEPTION, %g2
     161        clr %g5
     162        PREEMPTIBLE_HANDLER exc_dispatch
    139163
    140164/* TT = 0x32, TL = 0, data_access_error */
    … …  
    142166.global data_access_error_tl0
    143167data_access_error_tl0:
    144         PREEMPTIBLE_HANDLER data_access_error
     168        mov TT_DATA_ACCESS_ERROR, %g2
     169        clr %g5
     170        PREEMPTIBLE_HANDLER exc_dispatch
    145171
    146172/* TT = 0x34, TL = 0, mem_address_not_aligned */
    … …  
    148174.global mem_address_not_aligned_tl0
    149175mem_address_not_aligned_tl0:
    150         PREEMPTIBLE_HANDLER mem_address_not_aligned
     176        mov TT_MEM_ADDRESS_NOT_ALIGNED, %g2
     177        clr %g5
     178        PREEMPTIBLE_HANDLER exc_dispatch
    151179
    152180/* TT = 0x35, TL = 0, LDDF_mem_address_not_aligned */
    … …  
    154182.global LDDF_mem_address_not_aligned_tl0
    155183LDDF_mem_address_not_aligned_tl0:
    156         PREEMPTIBLE_HANDLER LDDF_mem_address_not_aligned
     184        mov TT_LDDF_MEM_ADDRESS_NOT_ALIGNED, %g2
     185        clr %g5
     186        PREEMPTIBLE_HANDLER exc_dispatch
    157187
    158188/* TT = 0x36, TL = 0, STDF_mem_address_not_aligned */
    … …  
    160190.global STDF_mem_address_not_aligned_tl0
    161191STDF_mem_address_not_aligned_tl0:
    162         PREEMPTIBLE_HANDLER STDF_mem_address_not_aligned
     192        mov TT_STDF_MEM_ADDRESS_NOT_ALIGNED, %g2
     193        clr %g5
     194        PREEMPTIBLE_HANDLER exc_dispatch
    163195
    164196/* TT = 0x37, TL = 0, privileged_action */
    … …  
    166198.global privileged_action_tl0
    167199privileged_action_tl0:
    168         PREEMPTIBLE_HANDLER privileged_action
     200        mov TT_PRIVILEGED_ACTION, %g2
     201        clr %g5
     202        PREEMPTIBLE_HANDLER exc_dispatch
    169203
    170204/* TT = 0x38, TL = 0, LDQF_mem_address_not_aligned */
    … …  
    172206.global LDQF_mem_address_not_aligned_tl0
    173207LDQF_mem_address_not_aligned_tl0:
    174         PREEMPTIBLE_HANDLER LDQF_mem_address_not_aligned
     208        mov TT_LDQF_MEM_ADDRESS_NOT_ALIGNED, %g2
     209        clr %g5
     210        PREEMPTIBLE_HANDLER exc_dispatch
    175211
    176212/* TT = 0x39, TL = 0, STQF_mem_address_not_aligned */
    … …  
    178214.global STQF_mem_address_not_aligned_tl0
    179215STQF_mem_address_not_aligned_tl0:
    180         PREEMPTIBLE_HANDLER STQF_mem_address_not_aligned
     216        mov TT_STQF_MEM_ADDRESS_NOT_ALIGNED, %g2
     217        clr %g5
     218        PREEMPTIBLE_HANDLER exc_dispatch
    181219
    182220/* TT = 0x41, TL = 0, interrupt_level_1 handler */
    … …  
    184222.global interrupt_level_1_handler_tl0
    185223interrupt_level_1_handler_tl0:
    186         INTERRUPT_LEVEL_N_HANDLER 1
     224        mov TT_INTERRUPT_LEVEL_1, %g2
     225        clr %g5
     226        PREEMPTIBLE_HANDLER exc_dispatch
    187227
    188228/* TT = 0x42, TL = 0, interrupt_level_2 handler */
    … …  
    190230.global interrupt_level_2_handler_tl0
    191231interrupt_level_2_handler_tl0:
    192         INTERRUPT_LEVEL_N_HANDLER 2
     232        mov TT_INTERRUPT_LEVEL_2, %g2
     233        clr %g5
     234        PREEMPTIBLE_HANDLER exc_dispatch
    193235
    194236/* TT = 0x43, TL = 0, interrupt_level_3 handler */
    … …  
    196238.global interrupt_level_3_handler_tl0
    197239interrupt_level_3_handler_tl0:
    198         INTERRUPT_LEVEL_N_HANDLER 3
     240        mov TT_INTERRUPT_LEVEL_3, %g2
     241        clr %g5
     242        PREEMPTIBLE_HANDLER exc_dispatch
    199243
    200244/* TT = 0x44, TL = 0, interrupt_level_4 handler */
    … …  
    202246.global interrupt_level_4_handler_tl0
    203247interrupt_level_4_handler_tl0:
    204         INTERRUPT_LEVEL_N_HANDLER 4
     248        mov TT_INTERRUPT_LEVEL_4, %g2
     249        clr %g5
     250        PREEMPTIBLE_HANDLER exc_dispatch
    205251
    206252/* TT = 0x45, TL = 0, interrupt_level_5 handler */
    … …  
    208254.global interrupt_level_5_handler_tl0
    209255interrupt_level_5_handler_tl0:
    210         INTERRUPT_LEVEL_N_HANDLER 5
     256        mov TT_INTERRUPT_LEVEL_5, %g2
     257        clr %g5
     258        PREEMPTIBLE_HANDLER exc_dispatch
    211259
    212260/* TT = 0x46, TL = 0, interrupt_level_6 handler */
    … …  
    214262.global interrupt_level_6_handler_tl0
    215263interrupt_level_6_handler_tl0:
    216         INTERRUPT_LEVEL_N_HANDLER 6
     264        mov TT_INTERRUPT_LEVEL_6, %g2
     265        clr %g5
     266        PREEMPTIBLE_HANDLER exc_dispatch
    217267
    218268/* TT = 0x47, TL = 0, interrupt_level_7 handler */
    … …  
    220270.global interrupt_level_7_handler_tl0
    221271interrupt_level_7_handler_tl0:
    222         INTERRUPT_LEVEL_N_HANDLER 7
     272        mov TT_INTERRUPT_LEVEL_7, %g2
     273        clr %g5
     274        PREEMPTIBLE_HANDLER exc_dispatch
    223275
    224276/* TT = 0x48, TL = 0, interrupt_level_8 handler */
    … …  
    226278.global interrupt_level_8_handler_tl0
    227279interrupt_level_8_handler_tl0:
    228         INTERRUPT_LEVEL_N_HANDLER 8
     280        mov TT_INTERRUPT_LEVEL_8, %g2
     281        clr %g5
     282        PREEMPTIBLE_HANDLER exc_dispatch
    229283
    230284/* TT = 0x49, TL = 0, interrupt_level_9 handler */
    … …  
    232286.global interrupt_level_9_handler_tl0
    233287interrupt_level_9_handler_tl0:
    234         INTERRUPT_LEVEL_N_HANDLER 9
     288        mov TT_INTERRUPT_LEVEL_9, %g2
     289        clr %g5
     290        PREEMPTIBLE_HANDLER exc_dispatch
    235291
    236292/* TT = 0x4a, TL = 0, interrupt_level_10 handler */
    … …  
    238294.global interrupt_level_10_handler_tl0
    239295interrupt_level_10_handler_tl0:
    240         INTERRUPT_LEVEL_N_HANDLER 10
     296        mov TT_INTERRUPT_LEVEL_10, %g2
     297        clr %g5
     298        PREEMPTIBLE_HANDLER exc_dispatch
    241299
    242300/* TT = 0x4b, TL = 0, interrupt_level_11 handler */
    … …  
    244302.global interrupt_level_11_handler_tl0
    245303interrupt_level_11_handler_tl0:
    246         INTERRUPT_LEVEL_N_HANDLER 11
     304        mov TT_INTERRUPT_LEVEL_11, %g2
     305        clr %g5
     306        PREEMPTIBLE_HANDLER exc_dispatch
    247307
    248308/* TT = 0x4c, TL = 0, interrupt_level_12 handler */
    … …  
    250310.global interrupt_level_12_handler_tl0
    251311interrupt_level_12_handler_tl0:
    252         INTERRUPT_LEVEL_N_HANDLER 12
     312        mov TT_INTERRUPT_LEVEL_12, %g2
     313        clr %g5
     314        PREEMPTIBLE_HANDLER exc_dispatch
    253315
    254316/* TT = 0x4d, TL = 0, interrupt_level_13 handler */
    … …  
    256318.global interrupt_level_13_handler_tl0
    257319interrupt_level_13_handler_tl0:
    258         INTERRUPT_LEVEL_N_HANDLER 13
     320        mov TT_INTERRUPT_LEVEL_13, %g2
     321        clr %g5
     322        PREEMPTIBLE_HANDLER exc_dispatch
    259323
    260324/* TT = 0x4e, TL = 0, interrupt_level_14 handler */
    … …  
    262326.global interrupt_level_14_handler_tl0
    263327interrupt_level_14_handler_tl0:
    264         INTERRUPT_LEVEL_N_HANDLER 14
     328        mov TT_INTERRUPT_LEVEL_14, %g2
     329        clr %g5
     330        PREEMPTIBLE_HANDLER exc_dispatch
    265331
    266332/* TT = 0x4f, TL = 0, interrupt_level_15 handler */
    … …  
    268334.global interrupt_level_15_handler_tl0
    269335interrupt_level_15_handler_tl0:
    270         INTERRUPT_LEVEL_N_HANDLER 15
     336        mov TT_INTERRUPT_LEVEL_15, %g2
     337        clr %g5
     338        PREEMPTIBLE_HANDLER exc_dispatch
    271339
    272340/* TT = 0x60, TL = 0, interrupt_vector_trap handler */
    … …  
    274342.global interrupt_vector_trap_handler_tl0
    275343interrupt_vector_trap_handler_tl0:
    276         INTERRUPT_VECTOR_TRAP_HANDLER
     344        mov TT_INTERRUPT_VECTOR_TRAP, %g2
     345        clr %g5
     346        PREEMPTIBLE_HANDLER exc_dispatch
    277347
    278348/* TT = 0x64, TL = 0, fast_instruction_access_MMU_miss */
    … …  
    342412.global trap_instruction_\cur\()_tl0
    343413trap_instruction_\cur\()_tl0:
     414        mov \cur, %g2
    344415        ba %xcc, trap_instruction_handler
    345         mov \cur, %g2
     416        clr %g5
    346417.endr
    347418
    … …  
    356427        wrpr %g0, 1, %tl
    357428        wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
    358         PREEMPTIBLE_HANDLER instruction_access_exception
     429        mov TT_INSTRUCTION_ACCESS_EXCEPTION, %g2
     430        clr %g5
     431        PREEMPTIBLE_HANDLER exc_dispatch
    359432
    360433/* TT = 0x0a, TL > 0, instruction_access_error */
    … …  
    363436instruction_access_error_tl1:
    364437        wrpr %g0, 1, %tl
    365         PREEMPTIBLE_HANDLER instruction_access_error
     438        mov TT_INSTRUCTION_ACCESS_ERROR, %g2
     439        clr %g5
     440        PREEMPTIBLE_HANDLER exc_dispatch
    366441
    367442/* TT = 0x10, TL > 0, illegal_instruction */
    … …  
    370445illegal_instruction_tl1:
    371446        wrpr %g0, 1, %tl
    372         PREEMPTIBLE_HANDLER illegal_instruction
     447        mov TT_ILLEGAL_INSTRUCTION, %g2
     448        clr %g5
     449        PREEMPTIBLE_HANDLER exc_dispatch
    373450
    374451/* TT = 0x24, TL > 0, clean_window handler */
    … …  
    383460division_by_zero_tl1:
    384461        wrpr %g0, 1, %tl
    385         PREEMPTIBLE_HANDLER division_by_zero
     462        mov TT_DIVISION_BY_ZERO, %g2
     463        clr %g5
     464        PREEMPTIBLE_HANDLER exc_dispatch
    386465
    387466/* TT = 0x30, TL > 0, data_access_exception */
    … …  
    391470        wrpr %g0, 1, %tl
    392471        wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
    393         PREEMPTIBLE_HANDLER data_access_exception
     472        mov TT_DATA_ACCESS_EXCEPTION, %g2
     473        clr %g5
     474        PREEMPTIBLE_HANDLER exc_dispatch
    394475
    395476/* TT = 0x32, TL > 0, data_access_error */
    … …  
    398479data_access_error_tl1:
    399480        wrpr %g0, 1, %tl
    400         PREEMPTIBLE_HANDLER data_access_error
     481        mov TT_DATA_ACCESS_ERROR, %g2
     482        clr %g5
     483        PREEMPTIBLE_HANDLER exc_dispatch
    401484
    402485/* TT = 0x34, TL > 0, mem_address_not_aligned */
    … …  
    405488mem_address_not_aligned_tl1:
    406489        wrpr %g0, 1, %tl
    407         PREEMPTIBLE_HANDLER mem_address_not_aligned
     490        mov TT_MEM_ADDRESS_NOT_ALIGNED, %g2
     491        clr %g5
     492        PREEMPTIBLE_HANDLER exc_dispatch
    408493
    409494/* TT = 0x68, TL > 0, fast_data_access_MMU_miss */
    … …  
    470555 *      %g1             Address of function to call if this is not a syscall.
    471556 *      %g2             First argument for the function.
     557 *      %g5             I/DTLB_TAG_ACCESS register if applicable.
    472558 *      %g6             Pre-set as kernel stack base if trap from userspace.
    473559 *      %g7             Pre-set as address of the userspace window buffer.
    474560 */
    475561.macro PREEMPTIBLE_HANDLER_TEMPLATE is_syscall
    476         /*
    477          * ASSERT(%tl == 1)
    478          */
    479         rdpr %tl, %g3
    480         cmp %g3, 1
    481         be %xcc, 1f
    482         nop
    483         ! this is for debugging, if we ever get here it will be easy to find
    484 0:      ba,a %xcc, 0b
    485 
    486 1:
    487562.if NOT(\is_syscall)
    488563        rdpr %tstate, %g3
    … …  
    502577        bnz %xcc, 0f                            ! ...skip setting of kernel stack and primary context
    503578        nop
    504        
    505579.endif
     580
    506581        /*
    507582         * Normal window spills will go to the userspace window buffer.
    … …  
    516591         * and the new window's %fp.
    517592         */
    518         save %g6, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp
     593        save %g6, -ISTATE_SIZE, %sp
    519594
    520595.if \is_syscall
    … …  
    548623        ba,a %xcc, 1f
    5496240:
    550         save %sp, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp
     625        save %sp, -ISTATE_SIZE, %sp
    551626
    552627        /*
    … …  
    570645.else
    571646        ! store the syscall number on the stack as 7th argument
    572         stx %g2, [%sp + STACK_WINDOW_SAVE_AREA_SIZE + STACK_BIAS + STACK_ARG6]
     647        stx %g2, [%sp + STACK_BIAS + ISTATE_OFFSET_ARG6]
    573648.endif
    574649
    575650        /*
    576          * Save TSTATE, TPC and TNPC aside.
     651         * Save TSTATE, TPC, TNPC and I/DTLB_TAG_ACCESS aside.
    577652         */
    578653        rdpr %tstate, %g1
    … …  
    581656        rd %y, %g4
    582657
    583         stx %g1, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TSTATE]
    584         stx %g2, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TPC]
    585         stx %g3, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC]
     658        stx %g1, [%sp + STACK_BIAS + ISTATE_OFFSET_TSTATE]
     659        stx %g2, [%sp + STACK_BIAS + ISTATE_OFFSET_TPC]
     660        stx %g3, [%sp + STACK_BIAS + ISTATE_OFFSET_TNPC]
     661        stx %g5, [%sp + STACK_BIAS + ISTATE_OFFSET_TLB_TAG_ACCESS]
    586662
    587663        /*
    588664         * Save the Y register.
    589          * This register is deprecated according to SPARC V9 specification
    590          * and is only present for backward compatibility with previous
    591          * versions of the SPARC architecture.
    592          * Surprisingly, gcc makes use of this register without a notice.
    593          */
    594         stx %g4, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_Y]
     665         */
     666        stx %g4, [%sp + STACK_BIAS + ISTATE_OFFSET_Y]
    595667       
    596668        wrpr %g0, 0, %tl
    … …  
    603675         */
    604676        call %l0
    605         add %sp, PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC, %o1
     677        add %sp, STACK_BIAS, %o1
    606678.else
    607679        /*
    … …  
    621693         * Read TSTATE, TPC and TNPC from saved copy.
    622694         */
    623         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TSTATE], %g1
    624         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TPC], %g2
    625         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC], %g3
     695        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_TSTATE], %g1
     696        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_TPC], %g2
     697        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_TNPC], %g3
    626698
    627699        /*
    … …  
    644716         * Restore Y.
    645717         */
    646         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_Y], %g4
     718        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_Y], %g4
    647719        wr %g4, %y
    648720
    … …  
    684756         */
    685757        mov %sp, %g2
    686         stx %i0, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I0]
    687         stx %i1, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I1]
    688         stx %i2, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I2]
    689         stx %i3, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I3]
    690         stx %i4, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I4]
    691         stx %i5, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I5]
    692         stx %i6, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I6]
    693         stx %i7, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I7]
     758        stx %i0, [%sp + STACK_BIAS + ISTATE_OFFSET_O0]
     759        stx %i1, [%sp + STACK_BIAS + ISTATE_OFFSET_O1]
     760        stx %i2, [%sp + STACK_BIAS + ISTATE_OFFSET_O2]
     761        stx %i3, [%sp + STACK_BIAS + ISTATE_OFFSET_O3]
     762        stx %i4, [%sp + STACK_BIAS + ISTATE_OFFSET_O4]
     763        stx %i5, [%sp + STACK_BIAS + ISTATE_OFFSET_O5]
     764        stx %i6, [%sp + STACK_BIAS + ISTATE_OFFSET_O6]
     765        stx %i7, [%sp + STACK_BIAS + ISTATE_OFFSET_O7]
    694766        wrpr %l0, 0, %cwp
    695767        mov %g2, %sp
    696         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I0], %i0
    697         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I1], %i1
    698         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I2], %i2
    699         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I3], %i3
    700         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I4], %i4
    701         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I5], %i5
    702         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I6], %i6
    703         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I7], %i7
     768        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O0], %i0
     769        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O1], %i1
     770        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O2], %i2
     771        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O3], %i3
     772        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O4], %i4
     773        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O5], %i5
     774        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O6], %i6
     775        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O7], %i7
    704776
    705777        /*
    … …  
    807879         * If the:
    808880         *
    809          *      save %g6, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp
     881         *      save %g6, -ISTATE_SIZE, %sp
    810882         *
    811883         * instruction trapped and spilled a register window into the userspace

  • kernel/arch/sparc64/src/trap/sun4v/interrupt.c

    reae91e0 r235d31d  
    9595 * register and processes the message (invokes a function call).
    9696 */
    97 void cpu_mondo(void)
     97void cpu_mondo(unsigned int tt, istate_t *istate)
    9898{
    9999#ifdef CONFIG_SMP

  • kernel/arch/sparc64/src/trap/sun4v/trap_table.S

    reae91e0 r235d31d  
    6666.global instruction_access_exception_tl0
    6767instruction_access_exception_tl0:
    68         PREEMPTIBLE_HANDLER instruction_access_exception
     68        mov TT_INSTRUCTION_ACCESS_EXCEPTION, %g2
     69        clr %g5
     70        PREEMPTIBLE_HANDLER exc_dispatch
    6971
    7072/* TT = 0x09, TL = 0, instruction_access_mmu_miss */
    … …  
    7779.global instruction_access_error_tl0
    7880instruction_access_error_tl0:
    79         PREEMPTIBLE_HANDLER instruction_access_error
     81        mov TT_INSTRUCTION_ACCESS_ERROR, %g2
     82        clr %g5
     83        PREEMPTIBLE_HANDLER exc_dispatch
    8084
    8185/* TT = 0x0b, TL = 0, IAE_unauth_access */
    … …  
    8387.global iae_unauth_access_tl0
    8488iae_unauth_access_tl0:
    85         PREEMPTIBLE_HANDLER instruction_access_exception
     89        mov TT_IAE_UNAUTH_ACCESS, %g2
     90        clr %g5
     91        PREEMPTIBLE_HANDLER exc_dispatch
    8692
    8793/* TT = 0x0c, TL = 0, IAE_nfo_page */
    … …  
    8995.global iae_nfo_page_tl0
    9096iae_nfo_page_tl0:
    91         PREEMPTIBLE_HANDLER instruction_access_exception
     97        mov TT_IAE_NFO_PAGE, %g2
     98        clr %g5
     99        PREEMPTIBLE_HANDLER exc_dispatch
    92100
    93101/* TT = 0x10, TL = 0, illegal_instruction */
    … …  
    95103.global illegal_instruction_tl0
    96104illegal_instruction_tl0:
    97         PREEMPTIBLE_HANDLER illegal_instruction
     105        mov TT_ILLEGAL_INSTRUCTION, %g2
     106        clr %g5
     107        PREEMPTIBLE_HANDLER exc_dispatch
    98108
    99109/* TT = 0x11, TL = 0, privileged_opcode */
    … …  
    101111.global privileged_opcode_tl0
    102112privileged_opcode_tl0:
    103         PREEMPTIBLE_HANDLER privileged_opcode
     113        mov TT_PRIVILEGED_OPCODE, %g2
     114        clr %g5
     115        PREEMPTIBLE_HANDLER exc_dispatch
    104116
    105117/* TT = 0x12, TL = 0, unimplemented_LDD */
    … …  
    107119.global unimplemented_LDD_tl0
    108120unimplemented_LDD_tl0:
    109         PREEMPTIBLE_HANDLER unimplemented_LDD
     121        mov TT_UNIMPLEMENTED_LDD, %g2
     122        clr %g5
     123        PREEMPTIBLE_HANDLER exc_dispatch
    110124
    111125/* TT = 0x13, TL = 0, unimplemented_STD */
    … …  
    113127.global unimplemented_STD_tl0
    114128unimplemented_STD_tl0:
    115         PREEMPTIBLE_HANDLER unimplemented_STD
     129        mov TT_UNIMPLEMENTED_STD, %g2
     130        clr %g5
     131        PREEMPTIBLE_HANDLER exc_dispatch
    116132
    117133/* TT = 0x14, TL = 0, DAE_invalid_asi */
    … …  
    119135.global dae_invalid_asi_tl0
    120136dae_invalid_asi_tl0:
    121         PREEMPTIBLE_HANDLER data_access_exception
     137        mov TT_DAE_INVALID_ASI, %g2
     138        clr %g5
     139        PREEMPTIBLE_HANDLER exc_dispatch
    122140
    123141/* TT = 0x15, TL = 0, DAE_privilege_violation */
    … …  
    125143.global dae_privilege_violation_tl0
    126144dae_privilege_violation_tl0:
    127         PREEMPTIBLE_HANDLER data_access_exception
     145        mov TT_DAE_PRIVILEGE_VIOLATION, %g2
     146        clr %g5
     147        PREEMPTIBLE_HANDLER exc_dispatch
    128148
    129149/* TT = 0x16, TL = 0, DAE_nc_page */
    … …  
    131151.global dae_nc_page_tl0
    132152dae_nc_page_tl0:
    133         PREEMPTIBLE_HANDLER data_access_exception
     153        mov TT_DAE_NC_PAGE, %g2
     154        clr %g5
     155        PREEMPTIBLE_HANDLER exc_dispatch
    134156
    135157/* TT = 0x17, TL = 0, DAE_nfo_page */
    … …  
    137159.global dae_nfo_page_tl0
    138160dae_nfo_page_tl0:
    139         PREEMPTIBLE_HANDLER data_access_exception
     161        mov TT_DAE_NFO_PAGE, %g2
     162        clr %g5
     163        PREEMPTIBLE_HANDLER exc_dispatch
    140164
    141165/* TT = 0x20, TL = 0, fb_disabled handler */
    … …  
    143167.global fb_disabled_tl0
    144168fp_disabled_tl0:
    145         PREEMPTIBLE_HANDLER fp_disabled
     169        mov TT_FP_DISABLED, %g2
     170        clr %g5
     171        PREEMPTIBLE_HANDLER exc_dispatch
    146172
    147173/* TT = 0x21, TL = 0, fb_exception_ieee_754 handler */
    … …  
    149175.global fb_exception_ieee_754_tl0
    150176fp_exception_ieee_754_tl0:
    151         PREEMPTIBLE_HANDLER fp_exception_ieee_754
     177        mov TT_FP_EXCEPTION_IEEE_754, %g2
     178        clr %g5
     179        PREEMPTIBLE_HANDLER exc_dispatch
    152180
    153181/* TT = 0x22, TL = 0, fb_exception_other handler */
    … …  
    155183.global fb_exception_other_tl0
    156184fp_exception_other_tl0:
    157         PREEMPTIBLE_HANDLER fp_exception_other
     185        mov TT_FP_EXCEPTION_OTHER, %g2
     186        clr %g5
     187        PREEMPTIBLE_HANDLER exc_dispatch
    158188
    159189/* TT = 0x23, TL = 0, tag_overflow */
    … …  
    161191.global tag_overflow_tl0
    162192tag_overflow_tl0:
    163         PREEMPTIBLE_HANDLER tag_overflow
     193        mov TT_TAG_OVERFLOW, %g2
     194        clr %g5
     195        PREEMPTIBLE_HANDLER exc_dispatch
    164196
    165197/* TT = 0x24, TL = 0, clean_window handler */
    … …  
    173205.global division_by_zero_tl0
    174206division_by_zero_tl0:
    175         PREEMPTIBLE_HANDLER division_by_zero
     207        mov TT_DIVISION_BY_ZERO, %g2
     208        clr %g5
     209        PREEMPTIBLE_HANDLER exc_dispatch
    176210
    177211/* TT = 0x30, TL = 0, data_access_exception */
    … …  
    180214.global data_access_exception_tl0
    181215data_access_exception_tl0:
    182         PREEMPTIBLE_HANDLER data_access_exception
     216        mov TT_DATA_ACCESS_EXCEPTION, %g2
     217        clr %g5
     218        PREEMPTIBLE_HANDLER exc_dispatch
    183219
    184220/* TT = 0x31, TL = 0, data_access_mmu_miss */
    … …  
    192228.global data_access_error_tl0
    193229data_access_error_tl0:
    194         PREEMPTIBLE_HANDLER data_access_error
     230        mov TT_DATA_ACCESS_ERROR, %g2
     231        clr %g5
     232        PREEMPTIBLE_HANDLER exc_dispatch
    195233
    196234/* TT = 0x34, TL = 0, mem_address_not_aligned */
    … …  
    198236.global mem_address_not_aligned_tl0
    199237mem_address_not_aligned_tl0:
    200         PREEMPTIBLE_HANDLER mem_address_not_aligned
     238        mov TT_MEM_ADDRESS_NOT_ALIGNED, %g2
     239        clr %g5
     240        PREEMPTIBLE_HANDLER exc_dispatch
    201241
    202242/* TT = 0x35, TL = 0, LDDF_mem_address_not_aligned */
    … …  
    204244.global LDDF_mem_address_not_aligned_tl0
    205245LDDF_mem_address_not_aligned_tl0:
    206         PREEMPTIBLE_HANDLER LDDF_mem_address_not_aligned
     246        mov TT_LDDF_MEM_ADDRESS_NOT_ALIGNED, %g2
     247        clr %g5
     248        PREEMPTIBLE_HANDLER exc_dispatch
    207249
    208250/* TT = 0x36, TL = 0, STDF_mem_address_not_aligned */
    … …  
    210252.global STDF_mem_address_not_aligned_tl0
    211253STDF_mem_address_not_aligned_tl0:
    212         PREEMPTIBLE_HANDLER STDF_mem_address_not_aligned
     254        mov TT_STDF_MEM_ADDRESS_NOT_ALIGNED, %g2
     255        clr %g5
     256        PREEMPTIBLE_HANDLER exc_dispatch
    213257
    214258/* TT = 0x37, TL = 0, privileged_action */
    … …  
    216260.global privileged_action_tl0
    217261privileged_action_tl0:
    218         PREEMPTIBLE_HANDLER privileged_action
     262        mov TT_PRIVILEGED_ACTION, %g2
     263        clr %g5
     264        PREEMPTIBLE_HANDLER exc_dispatch
    219265
    220266/* TT = 0x38, TL = 0, LDQF_mem_address_not_aligned */
    … …  
    222268.global LDQF_mem_address_not_aligned_tl0
    223269LDQF_mem_address_not_aligned_tl0:
    224         PREEMPTIBLE_HANDLER LDQF_mem_address_not_aligned
     270        mov TT_LDQF_MEM_ADDRESS_NOT_ALIGNED, %g2
     271        clr %g5
     272        PREEMPTIBLE_HANDLER exc_dispatch
    225273
    226274/* TT = 0x39, TL = 0, STQF_mem_address_not_aligned */
    … …  
    228276.global STQF_mem_address_not_aligned_tl0
    229277STQF_mem_address_not_aligned_tl0:
    230         PREEMPTIBLE_HANDLER STQF_mem_address_not_aligned
     278        mov TT_STQF_MEM_ADDRESS_NOT_ALIGNED, %g2
     279        clr %g5
     280        PREEMPTIBLE_HANDLER exc_dispatch
    231281
    232282/* TT = 0x41, TL = 0, interrupt_level_1 handler */
    … …  
    234284.global interrupt_level_1_handler_tl0
    235285interrupt_level_1_handler_tl0:
    236         INTERRUPT_LEVEL_N_HANDLER 1
     286        mov TT_INTERRUPT_LEVEL_1, %g2
     287        clr %g5
     288        PREEMPTIBLE_HANDLER exc_dispatch
    237289
    238290/* TT = 0x42, TL = 0, interrupt_level_2 handler */
    … …  
    240292.global interrupt_level_2_handler_tl0
    241293interrupt_level_2_handler_tl0:
    242         INTERRUPT_LEVEL_N_HANDLER 2
     294        mov TT_INTERRUPT_LEVEL_2, %g2
     295        clr %g5
     296        PREEMPTIBLE_HANDLER exc_dispatch
    243297
    244298/* TT = 0x43, TL = 0, interrupt_level_3 handler */
    … …  
    246300.global interrupt_level_3_handler_tl0
    247301interrupt_level_3_handler_tl0:
    248         INTERRUPT_LEVEL_N_HANDLER 3
     302        mov TT_INTERRUPT_LEVEL_3, %g2
     303        clr %g5
     304        PREEMPTIBLE_HANDLER exc_dispatch
    249305
    250306/* TT = 0x44, TL = 0, interrupt_level_4 handler */
    … …  
    252308.global interrupt_level_4_handler_tl0
    253309interrupt_level_4_handler_tl0:
    254         INTERRUPT_LEVEL_N_HANDLER 4
     310        mov TT_INTERRUPT_LEVEL_4, %g2
     311        clr %g5
     312        PREEMPTIBLE_HANDLER exc_dispatch
    255313
    256314/* TT = 0x45, TL = 0, interrupt_level_5 handler */
    … …  
    258316.global interrupt_level_5_handler_tl0
    259317interrupt_level_5_handler_tl0:
    260         INTERRUPT_LEVEL_N_HANDLER 5
     318        mov TT_INTERRUPT_LEVEL_5, %g2
     319        clr %g5
     320        PREEMPTIBLE_HANDLER exc_dispatch
    261321
    262322/* TT = 0x46, TL = 0, interrupt_level_6 handler */
    … …  
    264324.global interrupt_level_6_handler_tl0
    265325interrupt_level_6_handler_tl0:
    266         INTERRUPT_LEVEL_N_HANDLER 6
     326        mov TT_INTERRUPT_LEVEL_6, %g2
     327        clr %g5
     328        PREEMPTIBLE_HANDLER exc_dispatch
    267329
    268330/* TT = 0x47, TL = 0, interrupt_level_7 handler */
    … …  
    270332.global interrupt_level_7_handler_tl0
    271333interrupt_level_7_handler_tl0:
    272         INTERRUPT_LEVEL_N_HANDLER 7
     334        mov TT_INTERRUPT_LEVEL_7, %g2
     335        clr %g5
     336        PREEMPTIBLE_HANDLER exc_dispatch
    273337
    274338/* TT = 0x48, TL = 0, interrupt_level_8 handler */
    … …  
    276340.global interrupt_level_8_handler_tl0
    277341interrupt_level_8_handler_tl0:
    278         INTERRUPT_LEVEL_N_HANDLER 8
     342        mov TT_INTERRUPT_LEVEL_8, %g2
     343        clr %g5
     344        PREEMPTIBLE_HANDLER exc_dispatch
    279345
    280346/* TT = 0x49, TL = 0, interrupt_level_9 handler */
    … …  
    282348.global interrupt_level_9_handler_tl0
    283349interrupt_level_9_handler_tl0:
    284         INTERRUPT_LEVEL_N_HANDLER 9
     350        mov TT_INTERRUPT_LEVEL_9, %g2
     351        clr %g5
     352        PREEMPTIBLE_HANDLER exc_dispatch
    285353
    286354/* TT = 0x4a, TL = 0, interrupt_level_10 handler */
    … …  
    288356.global interrupt_level_10_handler_tl0
    289357interrupt_level_10_handler_tl0:
    290         INTERRUPT_LEVEL_N_HANDLER 10
     358        mov TT_INTERRUPT_LEVEL_10, %g2
     359        clr %g5
     360        PREEMPTIBLE_HANDLER exc_dispatch
    291361
    292362/* TT = 0x4b, TL = 0, interrupt_level_11 handler */
    … …  
    294364.global interrupt_level_11_handler_tl0
    295365interrupt_level_11_handler_tl0:
    296         INTERRUPT_LEVEL_N_HANDLER 11
     366        mov TT_INTERRUPT_LEVEL_11, %g2
     367        clr %g5
     368        PREEMPTIBLE_HANDLER exc_dispatch
    297369
    298370/* TT = 0x4c, TL = 0, interrupt_level_12 handler */
    … …  
    300372.global interrupt_level_12_handler_tl0
    301373interrupt_level_12_handler_tl0:
    302         INTERRUPT_LEVEL_N_HANDLER 12
     374        mov TT_INTERRUPT_LEVEL_12, %g2
     375        clr %g5
     376        PREEMPTIBLE_HANDLER exc_dispatch
    303377
    304378/* TT = 0x4d, TL = 0, interrupt_level_13 handler */
    … …  
    306380.global interrupt_level_13_handler_tl0
    307381interrupt_level_13_handler_tl0:
    308         INTERRUPT_LEVEL_N_HANDLER 13
     382        mov TT_INTERRUPT_LEVEL_13, %g2
     383        clr %g5
     384        PREEMPTIBLE_HANDLER exc_dispatch
    309385
    310386/* TT = 0x4e, TL = 0, interrupt_level_14 handler */
    … …  
    312388.global interrupt_level_14_handler_tl0
    313389interrupt_level_14_handler_tl0:
    314         INTERRUPT_LEVEL_N_HANDLER 14
     390        mov TT_INTERRUPT_LEVEL_14, %g2
     391        clr %g5
     392        PREEMPTIBLE_HANDLER exc_dispatch
    315393
    316394/* TT = 0x4f, TL = 0, interrupt_level_15 handler */
    … …  
    318396.global interrupt_level_15_handler_tl0
    319397interrupt_level_15_handler_tl0:
    320         INTERRUPT_LEVEL_N_HANDLER 15
     398        mov TT_INTERRUPT_LEVEL_15, %g2
     399        clr %g5
     400        PREEMPTIBLE_HANDLER exc_dispatch
    321401
    322402/* TT = 0x64, TL = 0, fast_instruction_access_MMU_miss */
    … …  
    342422.global cpu_mondo_handler_tl0
    343423cpu_mondo_handler_tl0:
    344 PREEMPTIBLE_HANDLER cpu_mondo
     424        mov TT_CPU_MONDO, %g2
     425        clr %g5
     426        PREEMPTIBLE_HANDLER exc_dispatch
    345427
    346428/* TT = 0x80, TL = 0, spill_0_normal handler */
    … …  
    392474.global trap_instruction_\cur\()_tl0
    393475trap_instruction_\cur\()_tl0:
     476        mov \cur, %g2
    394477        ba %xcc, trap_instruction_handler
    395         mov \cur, %g2
     478        clr %g5
    396479.endr
    397480
    … …  
    406489instruction_access_exception_tl1:
    407490        wrpr %g0, 1, %tl
    408         PREEMPTIBLE_HANDLER instruction_access_exception
     491        mov TT_INSTRUCTION_ACCESS_EXCEPTION, %g2
     492        clr %g5
     493        PREEMPTIBLE_HANDLER exc_dispatch
    409494
    410495/* TT = 0x09, TL > 0, instruction_access_mmu_miss */
    … …  
    419504instruction_access_error_tl1:
    420505        wrpr %g0, 1, %tl
    421         PREEMPTIBLE_HANDLER instruction_access_error
     506        mov TT_INSTRUCTION_ACCESS_ERROR, %g2
     507        clr %g5
     508        PREEMPTIBLE_HANDLER exc_dispatch
    422509
    423510/* TT = 0x0b, TL > 0, IAE_unauth_access */
    … …  
    426513iae_unauth_access_tl1:
    427514        wrpr %g0, 1, %tl
    428         PREEMPTIBLE_HANDLER instruction_access_exception
     515        mov TT_IAE_UNAUTH_ACCESS, %g2
     516        clr %g5
     517        PREEMPTIBLE_HANDLER exc_dispatch
    429518
    430519/* TT = 0x0c, TL > 0, IAE_nfo_page */
    … …  
    433522iae_nfo_page_tl1:
    434523        wrpr %g0, 1, %tl
    435         PREEMPTIBLE_HANDLER instruction_access_exception
     524        mov TT_IAE_NFO_PAGE, %g2
     525        clr %g5
     526        PREEMPTIBLE_HANDLER exc_dispatch
    436527
    437528/* TT = 0x10, TL > 0, illegal_instruction */
    … …  
    440531illegal_instruction_tl1:
    441532        wrpr %g0, 1, %tl
    442         PREEMPTIBLE_HANDLER illegal_instruction
     533        mov TT_ILLEGAL_INSTRUCTION, %g2
     534        clr %g5
     535        PREEMPTIBLE_HANDLER exc_dispatch
    443536
    444537/* TT = 0x14, TL > 0, DAE_invalid_asi */
    … …  
    447540dae_invalid_asi_tl1:
    448541        wrpr %g0, 1, %tl
    449         PREEMPTIBLE_HANDLER data_access_exception
     542        mov TT_DAE_INVALID_ASI, %g2
     543        clr %g5
     544        PREEMPTIBLE_HANDLER exc_dispatch
    450545
    451546/* TT = 0x15, TL > 0, DAE_privilege_violation */
    … …  
    454549dae_privilege_violation_tl1:
    455550        wrpr %g0, 1, %tl
    456         PREEMPTIBLE_HANDLER data_access_exception
     551        mov TT_DAE_PRIVILEGE_VIOLATION, %g2
     552        clr %g5
     553        PREEMPTIBLE_HANDLER exc_dispatch
    457554
    458555/* TT = 0x16, TL > 0, DAE_nc_page */
    … …  
    461558dae_nc_page_tl1:
    462559        wrpr %g0, 1, %tl
    463         PREEMPTIBLE_HANDLER data_access_exception
     560        mov TT_DAE_NC_PAGE, %g2
     561        clr %g5
     562        PREEMPTIBLE_HANDLER exc_dispatch
    464563
    465564/* TT = 0x17, TL > 0, DAE_nfo_page */
    … …  
    468567dae_nfo_page_tl1:
    469568        wrpr %g0, 1, %tl
    470         PREEMPTIBLE_HANDLER data_access_exception
     569        mov TT_DAE_NFO_PAGE, %g2
     570        clr %g5
     571        PREEMPTIBLE_HANDLER exc_dispatch
    471572
    472573/* TT = 0x24, TL > 0, clean_window handler */
    … …  
    481582division_by_zero_tl1:
    482583        wrpr %g0, 1, %tl
    483         PREEMPTIBLE_HANDLER division_by_zero
     584        mov TT_DIVISION_BY_ZERO, %g2
     585        clr %g5
     586        PREEMPTIBLE_HANDLER exc_dispatch
    484587
    485588/* TT = 0x30, TL > 0, data_access_exception */
    … …  
    487590.global data_access_exception_tl1
    488591data_access_exception_tl1:
    489         /*wrpr %g0, 1, %tl
    490         wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
    491         PREEMPTIBLE_HANDLER data_access_exception*/
     592        wrpr %g0, 1, %tl
     593        mov TT_DATA_ACCESS_EXCEPTION, %g2
     594        clr %g5
     595        PREEMPTIBLE_HANDLER exc_dispatch
    492596
    493597/* TT = 0x31, TL > 0, data_access_mmu_miss */
    … …  
    502606data_access_error_tl1:
    503607        wrpr %g0, 1, %tl
    504         PREEMPTIBLE_HANDLER data_access_error
     608        mov TT_DATA_ACCESS_ERROR, %g2
     609        clr %g5
     610        PREEMPTIBLE_HANDLER exc_dispatch
    505611
    506612/* TT = 0x34, TL > 0, mem_address_not_aligned */
    … …  
    509615mem_address_not_aligned_tl1:
    510616        wrpr %g0, 1, %tl
    511         PREEMPTIBLE_HANDLER mem_address_not_aligned
     617        mov TT_MEM_ADDRESS_NOT_ALIGNED, %g2
     618        clr %g5
     619        PREEMPTIBLE_HANDLER exc_dispatch
    512620
    513621/* TT = 0x68, TL > 0, fast_data_access_MMU_miss */
    … …  
    528636cpu_mondo_handler_tl1:
    529637        wrpr %g0, %tl
    530         PREEMPTIBLE_HANDLER cpu_mondo
     638        mov TT_CPU_MONDO, %g2
     639        clr %g5
     640        PREEMPTIBLE_HANDLER exc_dispatch
    531641
    532642/* TT = 0x80, TL > 0, spill_0_normal handler */
    … …  
    654764.else
    655765        ! store the syscall number on the stack as 7th argument
    656         stx %g2, [%sp + STACK_WINDOW_SAVE_AREA_SIZE + STACK_BIAS + STACK_ARG6]
     766        stx %g2, [%sp + STACK_BIAS + ISTATE_OFFSET_ARG6]
    657767.endif
    658768
    … …  
    664774        rdpr %tnpc, %g3
    665775
    666         stx %g1, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TSTATE]
    667         stx %g2, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TPC]
    668         stx %g3, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC]
     776        stx %g1, [%sp + STACK_BIAS + ISTATE_OFFSET_TSTATE]
     777        stx %g2, [%sp + STACK_BIAS + ISTATE_OFFSET_TPC]
     778        stx %g3, [%sp + STACK_BIAS + ISTATE_OFFSET_TNPC]
    669779
    670780        /*
    671781         * Save the Y register.
    672          * This register is deprecated according to SPARC V9 specification
    673          * and is only present for backward compatibility with previous
    674          * versions of the SPARC architecture.
    675          * Surprisingly, gcc makes use of this register without a notice.
    676782         */
    677783        rd %y, %g4
    678         stx %g4, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_Y]
     784        stx %g4, [%sp + STACK_BIAS + ISTATE_OFFSET_Y]
     785
     786        /*
     787         * Save the faulting page and context.
     788         */
     789        stx %g5, [%sp + STACK_BIAS + ISTATE_OFFSET_TLB_TAG_ACCESS]
    679790
    680791        /* switch to TL = 0, explicitly enable FPU */
    … …  
    689800        /* call higher-level service routine, pass istate as its 2nd parameter */
    690801        call %l0
    691         add %sp, PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC, %o1
     802        add %sp, STACK_BIAS, %o1
    692803.else
    693804        /* Call the higher-level syscall handler. */
    … …  
    711822
    712823        /* Read TSTATE, TPC and TNPC from saved copy. */
    713         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TSTATE], %g1
    714         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TPC], %g2
    715         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC], %g3
     824        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_TSTATE], %g1
     825        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_TPC], %g2
     826        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_TNPC], %g3
    716827
    717828        /* Copy PSTATE.PEF to the in-register copy of TSTATE. */
    … …  
    728839
    729840        /* Restore Y. */
    730         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_Y], %g4
     841        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_Y], %g4
    731842        wr %g4, %y
    732843       
    … …  
    750861         */
    751862        mov %sp, %g2
    752         stx %i0, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I0]
    753         stx %i1, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I1]
    754         stx %i2, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I2]
    755         stx %i3, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I3]
    756         stx %i4, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I4]
    757         stx %i5, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I5]
    758         stx %i6, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I6]
    759         stx %i7, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I7]
     863        stx %i0, [%sp + STACK_BIAS + ISTATE_OFFSET_O0]
     864        stx %i1, [%sp + STACK_BIAS + ISTATE_OFFSET_O1]
     865        stx %i2, [%sp + STACK_BIAS + ISTATE_OFFSET_O2]
     866        stx %i3, [%sp + STACK_BIAS + ISTATE_OFFSET_O3]
     867        stx %i4, [%sp + STACK_BIAS + ISTATE_OFFSET_O4]
     868        stx %i5, [%sp + STACK_BIAS + ISTATE_OFFSET_O5]
     869        stx %i6, [%sp + STACK_BIAS + ISTATE_OFFSET_O6]
     870        stx %i7, [%sp + STACK_BIAS + ISTATE_OFFSET_O7]
    760871        wrpr %l0, 0, %cwp
    761872        mov %g2, %sp
    762         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I0], %i0
    763         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I1], %i1
    764         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I2], %i2
    765         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I3], %i3
    766         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I4], %i4
    767         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I5], %i5
    768         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I6], %i6
    769         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I7], %i7
     873        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O0], %i0
     874        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O1], %i1
     875        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O2], %i2
     876        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O3], %i3
     877        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O4], %i4
     878        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O5], %i5
     879        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O6], %i6
     880        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O7], %i7
    770881.endm
    771882
    … …  
    774885 */
    775886.macro PREEMPTIBLE_HANDLER_KERNEL
    776 
    777         /*
    778          * ASSERT(%tl == 1)
    779          */
    780         rdpr %tl, %g3
    781         cmp %g3, 1
    782         be %xcc, 1f
    783         nop
    784 
    785         ! this is for debugging, if we ever get here it will be easy to find
    786 0:      ba,a %xcc, 0b
    787 
    788 1:
    789887        /* prevent unnecessary CLEANWIN exceptions */
    790888        wrpr %g0, NWINDOWS - 1, %cleanwin
    … …  
    799897        brnz %g3, 2f
    800898        nop
     899        rdpr %otherwin, %g4
     900        brnz %g4, 1f
     901        nop
     902
     903        /* OTHERWIN is zero, we are spilling a kernel window. */
    801904        INLINE_SPILL %g3, %g4
     905        ba,a %xcc, 2f
     906
     9071:
     908        /* OTHERWIN is non-zero, we are spilling a uspace window. */
     909        INLINE_SPILL_TO_WBUF %g3, %g4, %g7
    802910
    8039112:
    804912        /* ask for new register window */
    805         save %sp, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp
     913        save %sp, -ISTATE_SIZE, %sp
    806914
    807915        MIDDLE_PART 0
    … …  
    882990        set SCRATCHPAD_KSTACK, %g4
    883991        ldxa [%g4] ASI_SCRATCHPAD, %g6
    884         save %g6, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp
     992        save %g6, -ISTATE_SIZE, %sp
    885993
    886994.if \is_syscall
    … …  
    10151123         * If the:
    10161124         *
    1017          *      save %g6, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp
     1125         *      save %g6, -ISTATE_SIZE, %sp
    10181126         *
    10191127         * instruction trapped and spilled a register window into the userspace
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