source: mainline/kernel/arch/amd64/src/interrupt.c@ b1c57a8

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since b1c57a8 was b1c57a8, checked in by Jakub Jermar <jakub@…>, 11 years ago

Merge from lp:~adam-hraska+lp/helenos/rcu/.

Only merge from the feature branch and resolve all conflicts.

  • Property mode set to 100644
File size: 6.7 KB
Line 
1/*
2 * Copyright (c) 2001-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup amd64interrupt
30 * @{
31 */
32/** @file
33 */
34
35#include <arch/interrupt.h>
36#include <print.h>
37#include <log.h>
38#include <debug.h>
39#include <panic.h>
40#include <arch/drivers/i8259.h>
41#include <func.h>
42#include <cpu.h>
43#include <arch/asm.h>
44#include <mm/tlb.h>
45#include <mm/as.h>
46#include <arch.h>
47#include <arch/asm.h>
48#include <proc/scheduler.h>
49#include <proc/thread.h>
50#include <proc/task.h>
51#include <synch/spinlock.h>
52#include <arch/ddi/ddi.h>
53#include <interrupt.h>
54#include <ddi/irq.h>
55#include <symtab.h>
56#include <stacktrace.h>
57#include <smp/smp_call.h>
58
59/*
60 * Interrupt and exception dispatching.
61 */
62
63void (* disable_irqs_function)(uint16_t irqmask) = NULL;
64void (* enable_irqs_function)(uint16_t irqmask) = NULL;
65void (* eoi_function)(void) = NULL;
66const char *irqs_info = NULL;
67
68void istate_decode(istate_t *istate)
69{
70 log_printf("cs =%0#18" PRIx64 "\trip=%0#18" PRIx64 "\t"
71 "rfl=%0#18" PRIx64 "\terr=%0#18" PRIx64 "\n",
72 istate->cs, istate->rip, istate->rflags, istate->error_word);
73
74 if (istate_from_uspace(istate))
75 log_printf("ss =%0#18" PRIx64 "\n", istate->ss);
76
77 log_printf("rax=%0#18" PRIx64 "\trbx=%0#18" PRIx64 "\t"
78 "rcx=%0#18" PRIx64 "\trdx=%0#18" PRIx64 "\n",
79 istate->rax, istate->rbx, istate->rcx, istate->rdx);
80
81 log_printf("rsi=%0#18" PRIx64 "\trdi=%0#18" PRIx64 "\t"
82 "rbp=%0#18" PRIx64 "\trsp=%0#18" PRIx64 "\n",
83 istate->rsi, istate->rdi, istate->rbp,
84 istate_from_uspace(istate) ? istate->rsp :
85 (uintptr_t) &istate->rsp);
86
87 log_printf("r8 =%0#18" PRIx64 "\tr9 =%0#18" PRIx64 "\t"
88 "r10=%0#18" PRIx64 "\tr11=%0#18" PRIx64 "\n",
89 istate->r8, istate->r9, istate->r10, istate->r11);
90
91 log_printf("r12=%0#18" PRIx64 "\tr13=%0#18" PRIx64 "\t"
92 "r14=%0#18" PRIx64 "\tr15=%0#18" PRIx64 "\n",
93 istate->r12, istate->r13, istate->r14, istate->r15);
94}
95
96static void trap_virtual_eoi(void)
97{
98 if (eoi_function)
99 eoi_function();
100 else
101 panic("No eoi_function.");
102
103}
104
105static void null_interrupt(unsigned int n, istate_t *istate)
106{
107 fault_if_from_uspace(istate, "Unserviced interrupt: %u.", n);
108 panic_badtrap(istate, n, "Unserviced interrupt.");
109}
110
111static void de_fault(unsigned int n, istate_t *istate)
112{
113 fault_if_from_uspace(istate, "Divide error.");
114 panic_badtrap(istate, n, "Divide error.");
115}
116
117/** General Protection Fault.
118 *
119 */
120static void gp_fault(unsigned int n, istate_t *istate)
121{
122 if (TASK) {
123 irq_spinlock_lock(&TASK->lock, false);
124 size_t ver = TASK->arch.iomapver;
125 irq_spinlock_unlock(&TASK->lock, false);
126
127 if (CPU->arch.iomapver_copy != ver) {
128 /*
129 * This fault can be caused by an early access
130 * to I/O port because of an out-dated
131 * I/O Permission bitmap installed on CPU.
132 * Install the fresh copy and restart
133 * the instruction.
134 */
135 io_perm_bitmap_install();
136 return;
137 }
138 fault_if_from_uspace(istate, "General protection fault.");
139 }
140 panic_badtrap(istate, n, "General protection fault.");
141}
142
143static void ss_fault(unsigned int n, istate_t *istate)
144{
145 fault_if_from_uspace(istate, "Stack fault.");
146 panic_badtrap(istate, n, "Stack fault.");
147}
148
149static void nm_fault(unsigned int n, istate_t *istate)
150{
151#ifdef CONFIG_FPU_LAZY
152 scheduler_fpu_lazy_request();
153#else
154 fault_if_from_uspace(istate, "FPU fault.");
155 panic("FPU fault.");
156#endif
157}
158
159#ifdef CONFIG_SMP
160static void tlb_shootdown_ipi(unsigned int n, istate_t *istate)
161{
162 trap_virtual_eoi();
163 tlb_shootdown_ipi_recv();
164}
165
166static void arch_smp_call_ipi_recv(unsigned int n, istate_t *istate)
167{
168 trap_virtual_eoi();
169 smp_call_ipi_recv();
170}
171#endif
172
173/** Handler of IRQ exceptions.
174 *
175 */
176static void irq_interrupt(unsigned int n, istate_t *istate)
177{
178 ASSERT(n >= IVT_IRQBASE);
179
180 unsigned int inum = n - IVT_IRQBASE;
181 bool ack = false;
182 ASSERT(inum < IRQ_COUNT);
183 ASSERT((inum != IRQ_PIC_SPUR) && (inum != IRQ_PIC1));
184
185 irq_t *irq = irq_dispatch_and_lock(inum);
186 if (irq) {
187 /*
188 * The IRQ handler was found.
189 */
190
191 if (irq->preack) {
192 /* Send EOI before processing the interrupt */
193 trap_virtual_eoi();
194 ack = true;
195 }
196 irq->handler(irq);
197 irq_spinlock_unlock(&irq->lock, false);
198 } else {
199 /*
200 * Spurious interrupt.
201 */
202#ifdef CONFIG_DEBUG
203 log(LF_ARCH, LVL_DEBUG, "cpu%u: spurious interrupt (inum=%u)",
204 CPU->id, inum);
205#endif
206 }
207
208 if (!ack)
209 trap_virtual_eoi();
210}
211
212void interrupt_init(void)
213{
214 unsigned int i;
215
216 for (i = 0; i < IVT_ITEMS; i++)
217 exc_register(i, "null", false, (iroutine_t) null_interrupt);
218
219 for (i = 0; i < IRQ_COUNT; i++) {
220 if ((i != IRQ_PIC_SPUR) && (i != IRQ_PIC1))
221 exc_register(IVT_IRQBASE + i, "irq", true,
222 (iroutine_t) irq_interrupt);
223 }
224
225 exc_register(0, "de_fault", true, (iroutine_t) de_fault);
226 exc_register(7, "nm_fault", true, (iroutine_t) nm_fault);
227 exc_register(12, "ss_fault", true, (iroutine_t) ss_fault);
228 exc_register(13, "gp_fault", true, (iroutine_t) gp_fault);
229
230#ifdef CONFIG_SMP
231 exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown", true,
232 (iroutine_t) tlb_shootdown_ipi);
233 exc_register(VECTOR_SMP_CALL_IPI, "smp_call", true,
234 (iroutine_t) arch_smp_call_ipi_recv);
235#endif
236}
237
238void trap_virtual_enable_irqs(uint16_t irqmask)
239{
240 if (enable_irqs_function)
241 enable_irqs_function(irqmask);
242 else
243 panic("No enable_irqs_function.");
244}
245
246void trap_virtual_disable_irqs(uint16_t irqmask)
247{
248 if (disable_irqs_function)
249 disable_irqs_function(irqmask);
250 else
251 panic("No disable_irqs_function.");
252}
253
254/** @}
255 */
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