Changeset 04803bf in mainline for kernel/arch/ia32/include


Ignore:
Timestamp:
2011-03-21T22:00:17Z (14 years ago)
Author:
Jiri Svoboda <jiri@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
143932e3
Parents:
b50b5af2 (diff), 7308e84 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge mainline changes (needs fixes).

Location:
kernel/arch/ia32/include
Files:
31 edited
1 moved

Legend:

Unmodified
Added
Removed

  • kernel/arch/ia32/include/asm.h

    rb50b5af2 r04803bf  
    3838
    3939#include <arch/pm.h>
    40 #include <arch/types.h>
     40#include <arch/cpu.h>
    4141#include <typedefs.h>
    4242#include <config.h>
    43 
    44 extern uint32_t interrupt_handler_size;
    45 
    46 extern void paging_on(void);
    47 
    48 extern void interrupt_handlers(void);
    49 
    50 extern void enable_l_apic_in_msr(void);
    51 
    52 
    53 extern void asm_delay_loop(uint32_t t);
    54 extern void asm_fake_loop(uint32_t t);
    55 
     43#include <trace.h>
    5644
    5745/** Halt CPU
    … …  
    6048 *
    6149 */
    62 static inline void cpu_halt(void)
    63 {
    64         asm volatile (
    65                 "0:\n"
    66                 "       hlt\n"
    67                 "       jmp 0b\n"
    68         );
    69 }
    70 
    71 static inline void cpu_sleep(void)
    72 {
    73         asm volatile ("hlt\n");
    74 }
    75 
    76 #define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
     50NO_TRACE static inline __attribute__((noreturn)) void cpu_halt(void)
     51{
     52        while (true) {
     53                asm volatile (
     54                        "hlt\n"
     55                );
     56        }
     57}
     58
     59NO_TRACE static inline void cpu_sleep(void)
     60{
     61        asm volatile (
     62                "hlt\n"
     63        );
     64}
     65
     66#define GEN_READ_REG(reg) NO_TRACE static inline sysarg_t read_ ##reg (void) \
    7767        { \
    78                 unative_t res; \
     68                sysarg_t res; \
    7969                asm volatile ( \
    8070                        "movl %%" #reg ", %[res]" \
    … …  
    8474        }
    8575
    86 #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
     76#define GEN_WRITE_REG(reg) NO_TRACE static inline void write_ ##reg (sysarg_t regn) \
    8777        { \
    8878                asm volatile ( \
    … …  
    119109 *
    120110 */
    121 static inline void pio_write_8(ioport8_t *port, uint8_t val)
     111NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t val)
    122112{
    123113        asm volatile (
    124114                "outb %b[val], %w[port]\n"
    125                 :: [val] "a" (val), [port] "d" (port)
     115                :: [val] "a" (val),
     116                   [port] "d" (port)
    126117        );
    127118}
    … …  
    135126 *
    136127 */
    137 static inline void pio_write_16(ioport16_t *port, uint16_t val)
     128NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t val)
    138129{
    139130        asm volatile (
    140131                "outw %w[val], %w[port]\n"
    141                 :: [val] "a" (val), [port] "d" (port)
     132                :: [val] "a" (val),
     133                   [port] "d" (port)
    142134        );
    143135}
    … …  
    151143 *
    152144 */
    153 static inline void pio_write_32(ioport32_t *port, uint32_t val)
     145NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t val)
    154146{
    155147        asm volatile (
    156148                "outl %[val], %w[port]\n"
    157                 :: [val] "a" (val), [port] "d" (port)
     149                :: [val] "a" (val),
     150                   [port] "d" (port)
    158151        );
    159152}
    … …  
    167160 *
    168161 */
    169 static inline uint8_t pio_read_8(ioport8_t *port)
     162NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
    170163{
    171164        uint8_t val;
    … …  
    188181 *
    189182 */
    190 static inline uint16_t pio_read_16(ioport16_t *port)
     183NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
    191184{
    192185        uint16_t val;
    … …  
    209202 *
    210203 */
    211 static inline uint32_t pio_read_32(ioport32_t *port)
     204NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
    212205{
    213206        uint32_t val;
    … …  
    230223 *
    231224 */
    232 static inline ipl_t interrupts_enable(void)
     225NO_TRACE static inline ipl_t interrupts_enable(void)
    233226{
    234227        ipl_t v;
    … …  
    252245 *
    253246 */
    254 static inline ipl_t interrupts_disable(void)
     247NO_TRACE static inline ipl_t interrupts_disable(void)
    255248{
    256249        ipl_t v;
    … …  
    273266 *
    274267 */
    275 static inline void interrupts_restore(ipl_t ipl)
     268NO_TRACE static inline void interrupts_restore(ipl_t ipl)
    276269{
    277270        asm volatile (
    … …  
    287280 *
    288281 */
    289 static inline ipl_t interrupts_read(void)
     282NO_TRACE static inline ipl_t interrupts_read(void)
    290283{
    291284        ipl_t v;
    … …  
    300293}
    301294
     295/** Check interrupts state.
     296 *
     297 * @return True if interrupts are disabled.
     298 *
     299 */
     300NO_TRACE static inline bool interrupts_disabled(void)
     301{
     302        ipl_t v;
     303       
     304        asm volatile (
     305                "pushf\n"
     306                "popl %[v]\n"
     307                : [v] "=r" (v)
     308        );
     309       
     310        return ((v & EFLAGS_IF) == 0);
     311}
     312
    302313/** Write to MSR */
    303 static inline void write_msr(uint32_t msr, uint64_t value)
     314NO_TRACE static inline void write_msr(uint32_t msr, uint64_t value)
    304315{
    305316        asm volatile (
    306317                "wrmsr"
    307                 :: "c" (msr), "a" ((uint32_t) (value)),
     318                :: "c" (msr),
     319                   "a" ((uint32_t) (value)),
    308320                   "d" ((uint32_t) (value >> 32))
    309321        );
    310322}
    311323
    312 static inline uint64_t read_msr(uint32_t msr)
     324NO_TRACE static inline uint64_t read_msr(uint32_t msr)
    313325{
    314326        uint32_t ax, dx;
    … …  
    316328        asm volatile (
    317329                "rdmsr"
    318                 : "=a" (ax), "=d" (dx)
     330                : "=a" (ax),
     331                  "=d" (dx)
    319332                : "c" (msr)
    320333        );
    … …  
    331344 *
    332345 */
    333 static inline uintptr_t get_stack_base(void)
     346NO_TRACE static inline uintptr_t get_stack_base(void)
    334347{
    335348        uintptr_t v;
    … …  
    344357}
    345358
    346 /** Return current IP address */
    347 static inline uintptr_t * get_ip()
    348 {
    349         uintptr_t *ip;
    350        
    351         asm volatile (
    352                 "mov %%eip, %[ip]"
    353                 : [ip] "=r" (ip)
    354         );
    355        
    356         return ip;
    357 }
    358 
    359359/** Invalidate TLB Entry.
    360360 *
    … …  
    362362 *
    363363 */
    364 static inline void invlpg(uintptr_t addr)
     364NO_TRACE static inline void invlpg(uintptr_t addr)
    365365{
    366366        asm volatile (
    367367                "invlpg %[addr]\n"
    368                 :: [addr] "m" (*(unative_t *) addr)
     368                :: [addr] "m" (*(sysarg_t *) addr)
    369369        );
    370370}
    … …  
    375375 *
    376376 */
    377 static inline void gdtr_load(ptr_16_32_t *gdtr_reg)
     377NO_TRACE static inline void gdtr_load(ptr_16_32_t *gdtr_reg)
    378378{
    379379        asm volatile (
    … …  
    388388 *
    389389 */
    390 static inline void gdtr_store(ptr_16_32_t *gdtr_reg)
     390NO_TRACE static inline void gdtr_store(ptr_16_32_t *gdtr_reg)
    391391{
    392392        asm volatile (
    393393                "sgdtl %[gdtr_reg]\n"
    394                 :: [gdtr_reg] "m" (*gdtr_reg)
     394                : [gdtr_reg] "=m" (*gdtr_reg)
    395395        );
    396396}
    … …  
    401401 *
    402402 */
    403 static inline void idtr_load(ptr_16_32_t *idtr_reg)
     403NO_TRACE static inline void idtr_load(ptr_16_32_t *idtr_reg)
    404404{
    405405        asm volatile (
    … …  
    414414 *
    415415 */
    416 static inline void tr_load(uint16_t sel)
     416NO_TRACE static inline void tr_load(uint16_t sel)
    417417{
    418418        asm volatile (
    … …  
    422422}
    423423
     424extern void paging_on(void);
     425extern void enable_l_apic_in_msr(void);
     426
     427extern void asm_delay_loop(uint32_t);
     428extern void asm_fake_loop(uint32_t);
     429
     430extern uintptr_t int_syscall;
     431
     432extern uintptr_t int_0;
     433extern uintptr_t int_1;
     434extern uintptr_t int_2;
     435extern uintptr_t int_3;
     436extern uintptr_t int_4;
     437extern uintptr_t int_5;
     438extern uintptr_t int_6;
     439extern uintptr_t int_7;
     440extern uintptr_t int_8;
     441extern uintptr_t int_9;
     442extern uintptr_t int_10;
     443extern uintptr_t int_11;
     444extern uintptr_t int_12;
     445extern uintptr_t int_13;
     446extern uintptr_t int_14;
     447extern uintptr_t int_15;
     448extern uintptr_t int_16;
     449extern uintptr_t int_17;
     450extern uintptr_t int_18;
     451extern uintptr_t int_19;
     452extern uintptr_t int_20;
     453extern uintptr_t int_21;
     454extern uintptr_t int_22;
     455extern uintptr_t int_23;
     456extern uintptr_t int_24;
     457extern uintptr_t int_25;
     458extern uintptr_t int_26;
     459extern uintptr_t int_27;
     460extern uintptr_t int_28;
     461extern uintptr_t int_29;
     462extern uintptr_t int_30;
     463extern uintptr_t int_31;
     464extern uintptr_t int_32;
     465extern uintptr_t int_33;
     466extern uintptr_t int_34;
     467extern uintptr_t int_35;
     468extern uintptr_t int_36;
     469extern uintptr_t int_37;
     470extern uintptr_t int_38;
     471extern uintptr_t int_39;
     472extern uintptr_t int_40;
     473extern uintptr_t int_41;
     474extern uintptr_t int_42;
     475extern uintptr_t int_43;
     476extern uintptr_t int_44;
     477extern uintptr_t int_45;
     478extern uintptr_t int_46;
     479extern uintptr_t int_47;
     480extern uintptr_t int_48;
     481extern uintptr_t int_49;
     482extern uintptr_t int_50;
     483extern uintptr_t int_51;
     484extern uintptr_t int_52;
     485extern uintptr_t int_53;
     486extern uintptr_t int_54;
     487extern uintptr_t int_55;
     488extern uintptr_t int_56;
     489extern uintptr_t int_57;
     490extern uintptr_t int_58;
     491extern uintptr_t int_59;
     492extern uintptr_t int_60;
     493extern uintptr_t int_61;
     494extern uintptr_t int_62;
     495extern uintptr_t int_63;
     496
    424497#endif
    425498

  • kernel/arch/ia32/include/atomic.h

    rb50b5af2 r04803bf  
    3636#define KERN_ia32_ATOMIC_H_
    3737
    38 #include <arch/types.h>
     38#include <typedefs.h>
    3939#include <arch/barrier.h>
    4040#include <preemption.h>
     41#include <trace.h>
    4142
    42 static inline void atomic_inc(atomic_t *val) {
     43NO_TRACE static inline void atomic_inc(atomic_t *val)
     44{
    4345#ifdef CONFIG_SMP
    4446        asm volatile (
    … …  
    5456}
    5557
    56 static inline void atomic_dec(atomic_t *val) {
     58NO_TRACE static inline void atomic_dec(atomic_t *val)
     59{
    5760#ifdef CONFIG_SMP
    5861        asm volatile (
    … …  
    6871}
    6972
    70 static inline long atomic_postinc(atomic_t *val)
     73NO_TRACE static inline atomic_count_t atomic_postinc(atomic_t *val)
    7174{
    72         long r = 1;
     75        atomic_count_t r = 1;
    7376       
    7477        asm volatile (
    7578                "lock xaddl %[r], %[count]\n"
    76                 : [count] "+m" (val->count), [r] "+r" (r)
     79                : [count] "+m" (val->count),
     80                  [r] "+r" (r)
    7781        );
    7882       
    … …  
    8084}
    8185
    82 static inline long atomic_postdec(atomic_t *val)
     86NO_TRACE static inline atomic_count_t atomic_postdec(atomic_t *val)
    8387{
    84         long r = -1;
     88        atomic_count_t r = -1;
    8589       
    8690        asm volatile (
    8791                "lock xaddl %[r], %[count]\n"
    88                 : [count] "+m" (val->count), [r] "+r"(r)
     92                : [count] "+m" (val->count),
     93                  [r] "+r" (r)
    8994        );
    9095       
    … …  
    95100#define atomic_predec(val)  (atomic_postdec(val) - 1)
    96101
    97 static inline uint32_t test_and_set(atomic_t *val) {
    98         uint32_t v;
     102NO_TRACE static inline atomic_count_t test_and_set(atomic_t *val)
     103{
     104        atomic_count_t v = 1;
    99105       
    100106        asm volatile (
    101                 "movl $1, %[v]\n"
    102107                "xchgl %[v], %[count]\n"
    103                 : [v] "=r" (v), [count] "+m" (val->count)
     108                : [v] "+r" (v),
     109                  [count] "+m" (val->count)
    104110        );
    105111       
    … …  
    108114
    109115/** ia32 specific fast spinlock */
    110 static inline void atomic_lock_arch(atomic_t *val)
     116NO_TRACE static inline void atomic_lock_arch(atomic_t *val)
    111117{
    112         uint32_t tmp;
     118        atomic_count_t tmp;
    113119       
    114120        preemption_disable();
    … …  
    124130                "testl %[tmp], %[tmp]\n"
    125131                "jnz 0b\n"
    126                 : [count] "+m" (val->count), [tmp] "=&r" (tmp)
     132                : [count] "+m" (val->count),
     133                  [tmp] "=&r" (tmp)
    127134        );
     135       
    128136        /*
    129137         * Prevent critical section code from bleeding out this way up.

  • kernel/arch/ia32/include/barrier.h

    rb50b5af2 r04803bf  
    3636#define KERN_ia32_BARRIER_H_
    3737
     38#include <trace.h>
     39
    3840/*
    3941 * NOTE:
    … …  
    5052#define CS_LEAVE_BARRIER()  asm volatile ("" ::: "memory")
    5153
    52 static inline void cpuid_serialization(void)
     54NO_TRACE static inline void cpuid_serialization(void)
    5355{
    5456#ifndef __IN_SHARED_LIBC__

  • kernel/arch/ia32/include/bios/bios.h

    rb50b5af2 r04803bf  
    2727 */
    2828
    29 /** @addtogroup ia32   
     29/** @addtogroup ia32
    3030 * @{
    3131 */
    … …  
    3636#define KERN_ia32_BIOS_H_
    3737
    38 #include <arch/types.h>
    39 
    40 #define BIOS_EBDA_PTR   0x40e
     38#include <typedefs.h>
    4139
    4240extern uintptr_t ebda;

  • kernel/arch/ia32/include/boot/boot.h

    rb50b5af2 r04803bf  
    3838#define BOOT_OFFSET      0x108000
    3939#define AP_BOOT_OFFSET   0x8000
    40 #define BOOT_STACK_SIZE  0x400
     40#define BOOT_STACK_SIZE  0x0400
    4141
    4242#define MULTIBOOT_HEADER_MAGIC  0x1BADB002

  • kernel/arch/ia32/include/boot/memmap.h

    rb50b5af2 r04803bf  
    6161#ifndef __ASM__
    6262
    63 #include <arch/types.h>
     63#include <typedefs.h>
    6464
    6565typedef struct {
    … …  
    7070
    7171extern e820memmap_t e820table[MEMMAP_E820_MAX_RECORDS];
    72 extern uint8_t e820counter; 
     72extern uint8_t e820counter;
    7373
    7474#endif

  • kernel/arch/ia32/include/context.h

    rb50b5af2 r04803bf  
    2727 */
    2828
    29 /** @addtogroup ia32   
     29/** @addtogroup ia32
    3030 * @{
    3131 */
    … …  
    3737
    3838#ifdef KERNEL
    39 #include <arch/types.h>
    4039
    41 #define STACK_ITEM_SIZE 4
     40#include <typedefs.h>
     41
     42#define STACK_ITEM_SIZE  4
    4243
    4344/*
    … …  
    4748 * One item is put onto stack to support get_stack_base().
    4849 */
    49 #define SP_DELTA        (8 + STACK_ITEM_SIZE)
     50#define SP_DELTA  (8 + STACK_ITEM_SIZE)
     51
     52#define context_set(c, _pc, stack, size) \
     53        do { \
     54                (c)->pc = (uintptr_t) (_pc); \
     55                (c)->sp = ((uintptr_t) (stack)) + (size) - SP_DELTA; \
     56                (c)->ebp = 0; \
     57        } while (0)
    5058
    5159#endif /* KERNEL */

  • kernel/arch/ia32/include/context_offset.h

    rb50b5af2 r04803bf  
    2727 */
    2828
    29 /** @addtogroup ia32   
     29/** @addtogroup ia32
    3030 * @{
    3131 */
    … …  
    3636#define KERN_ia32_CONTEXT_OFFSET_H_
    3737
    38 #define OFFSET_SP  0x0
    39 #define OFFSET_PC  0x4
    40 #define OFFSET_EBX 0x8
    41 #define OFFSET_ESI 0xC
    42 #define OFFSET_EDI 0x10
    43 #define OFFSET_EBP 0x14
     38#define OFFSET_SP   0x00
     39#define OFFSET_PC   0x04
     40#define OFFSET_EBX  0x08
     41#define OFFSET_ESI  0x0C
     42#define OFFSET_EDI  0x10
     43#define OFFSET_EBP  0x14
    4444
    45 #ifdef KERNEL 
    46 # define OFFSET_IPL 0x18
     45#ifdef KERNEL
     46        #define OFFSET_IPL 0x18
    4747#else
    48 # define OFFSET_TLS 0x18
     48        #define OFFSET_TLS 0x18
    4949#endif
    5050
     51#ifdef __ASM__
    5152
    52 #ifdef __ASM__
    53 
    54 # ctx: address of the structure with saved context
     53# ctx: address of the structure with saved context
    5554# pc: return address
    5655
    5756.macro CONTEXT_SAVE_ARCH_CORE ctx:req pc:req
    58         movl %esp,OFFSET_SP(\ctx)       # %esp -> ctx->sp       
     57        movl %esp,OFFSET_SP(\ctx)       # %esp -> ctx->sp
    5958        movl \pc,OFFSET_PC(\ctx)        # %eip -> ctx->pc
    60         movl %ebx,OFFSET_EBX(\ctx)      # %ebx -> ctx->ebx     
    61         movl %esi,OFFSET_ESI(\ctx)      # %esi -> ctx->esi     
    62         movl %edi,OFFSET_EDI(\ctx)      # %edi -> ctx->edi     
    63         movl %ebp,OFFSET_EBP(\ctx)      # %ebp -> ctx->ebp     
     59        movl %ebx,OFFSET_EBX(\ctx)      # %ebx -> ctx->ebx
     60        movl %esi,OFFSET_ESI(\ctx)      # %esi -> ctx->esi
     61        movl %edi,OFFSET_EDI(\ctx)      # %edi -> ctx->edi
     62        movl %ebp,OFFSET_EBP(\ctx)      # %ebp -> ctx->ebp
    6463.endm
    6564
    66 # ctx: address of the structure with saved context 
     65# ctx: address of the structure with saved context
    6766
    6867.macro CONTEXT_RESTORE_ARCH_CORE ctx:req pc:req
    … …  
    7574.endm
    7675
    77 #endif /* __ASM__ */ 
     76#endif /* __ASM__ */
    7877
    7978#endif
    … …  
    8180/** @}
    8281 */
    83 

  • kernel/arch/ia32/include/cpu.h

    rb50b5af2 r04803bf  
    3737
    3838#define EFLAGS_IF       (1 << 9)
     39#define EFLAGS_DF       (1 << 10)
     40#define EFLAGS_NT       (1 << 14)
    3941#define EFLAGS_RF       (1 << 16)
    4042
    … …  
    4244
    4345/* Support for SYSENTER and SYSEXIT */
    44 #define IA32_MSR_SYSENTER_CS    0x174
    45 #define IA32_MSR_SYSENTER_ESP   0x175
    46 #define IA32_MSR_SYSENTER_EIP   0x176
     46#define IA32_MSR_SYSENTER_CS   0x174U
     47#define IA32_MSR_SYSENTER_ESP  0x175U
     48#define IA32_MSR_SYSENTER_EIP  0x176U
    4749
    4850#ifndef __ASM__
    … …  
    5052#include <arch/pm.h>
    5153#include <arch/asm.h>
     54#include <arch/cpuid.h>
    5255
    5356typedef struct {
    … …  
    5659        unsigned int model;
    5760        unsigned int stepping;
     61        cpuid_feature_info fi;
     62
    5863        tss_t *tss;
    5964       

  • kernel/arch/ia32/include/cpuid.h

    rb50b5af2 r04803bf  
    4343#ifndef __ASM__
    4444
    45 #include <arch/types.h>
     45#include <typedefs.h>
    4646
    4747typedef struct {
    … …  
    6363
    6464struct __cpuid_feature_info {
    65         unsigned                        : 23;
     65        unsigned      : 11;
     66        unsigned sep  :  1;
     67        unsigned      : 11;
    6668        unsigned mmx  :  1;
    6769        unsigned fxsr :  1;

  • kernel/arch/ia32/include/cycle.h

    rb50b5af2 r04803bf  
    2727 */
    2828
    29 /** @addtogroup ia32   
     29/** @addtogroup ia32
    3030 * @{
    3131 */
    … …  
    3636#define KERN_ia32_CYCLE_H_
    3737
    38 static inline uint64_t get_cycle(void)
     38#include <trace.h>
     39
     40NO_TRACE static inline uint64_t get_cycle(void)
    3941{
    4042        uint64_t v;

  • kernel/arch/ia32/include/ddi/ddi.h

    rb50b5af2 r04803bf  
    3232/**
    3333 * @file
    34  * @brief       ia32 specific DDI declarations and macros.
     34 * @brief ia32 specific DDI declarations and macros.
    3535 */
    3636

  • kernel/arch/ia32/include/drivers/i8254.h

    rb50b5af2 r04803bf  
    3636#define KERN_ia32_I8254_H_
    3737
    38 #include <arch/types.h>
    39 
    4038extern void i8254_init(void);
    4139extern void i8254_calibrate_delay_loop(void);

  • kernel/arch/ia32/include/drivers/i8259.h

    rb50b5af2 r04803bf  
    3636#define KERN_ia32_I8259_H_
    3737
    38 #include <arch/types.h>
     38#include <typedefs.h>
    3939#include <arch/interrupt.h>
    4040
    41 #define PIC_PIC0PORT1  ((ioport8_t *) 0x20)
    42 #define PIC_PIC0PORT2  ((ioport8_t *) 0x21)
    43 #define PIC_PIC1PORT1  ((ioport8_t *) 0xa0)
    44 #define PIC_PIC1PORT2  ((ioport8_t *) 0xa1)
     41#define PIC_PIC0PORT1  ((ioport8_t *) 0x20U)
     42#define PIC_PIC0PORT2  ((ioport8_t *) 0x21U)
     43#define PIC_PIC1PORT1  ((ioport8_t *) 0xa0U)
     44#define PIC_PIC1PORT2  ((ioport8_t *) 0xa1U)
    4545
    4646#define PIC_NEEDICW4  (1 << 0)
    … …  
    4848
    4949extern void i8259_init(void);
    50 extern void pic_enable_irqs(uint16_t irqmask);
    51 extern void pic_disable_irqs(uint16_t irqmask);
     50extern void pic_enable_irqs(uint16_t);
     51extern void pic_disable_irqs(uint16_t);
    5252extern void pic_eoi(void);
    5353

  • kernel/arch/ia32/include/drivers/vesa.h

    rb50b5af2 r04803bf  
    3636#define KERN_ia32_VESA_H_
    3737
    38 #include <arch/types.h>
     38#include <typedefs.h>
    3939
    4040extern bool vesa_init(void);

  • kernel/arch/ia32/include/faddr.h

    rb50b5af2 r04803bf  
    2727 */
    2828
    29 /** @addtogroup ia32   
     29/** @addtogroup ia32
    3030 * @{
    3131 */
    … …  
    3636#define KERN_ia32_FADDR_H_
    3737
    38 #include <arch/types.h>
     38#include <typedefs.h>
    3939
    40 #define FADDR(fptr)             ((uintptr_t) (fptr))
     40#define FADDR(fptr)  ((uintptr_t) (fptr))
    4141
    4242#endif

  • kernel/arch/ia32/include/fpu_context.h

    rb50b5af2 r04803bf  
    2727 */
    2828
    29 /** @addtogroup ia32   
     29/** @addtogroup ia32
    3030 * @{
    3131 */
    … …  
    3636#define KERN_ia32_FPU_CONTEXT_H_
    3737
    38 #include <arch/types.h>
     38#include <typedefs.h>
    3939
    40 #define FPU_CONTEXT_ALIGN 16
    41 
    42 void fpu_fxsr(void);
    43 void fpu_fsr(void);
    44 
     40#define FPU_CONTEXT_ALIGN  16
    4541
    4642typedef struct {
    47         uint8_t fpu[512];               /* FXSAVE & FXRSTOR storage area */
     43        uint8_t fpu[512];  /* FXSAVE & FXRSTOR storage area */
    4844} fpu_context_t;
     45
     46extern void fpu_fxsr(void);
     47extern void fpu_fsr(void);
    4948
    5049#endif

  • kernel/arch/ia32/include/interrupt.h

    rb50b5af2 r04803bf  
    3636#define KERN_ia32_INTERRUPT_H_
    3737
    38 #include <arch/types.h>
     38#include <typedefs.h>
     39#include <arch/istate.h>
    3940#include <arch/pm.h>
    4041
    41 #define IVT_ITEMS       IDT_ITEMS
    42 #define IVT_FIRST       0
     42#define IVT_ITEMS  IDT_ITEMS
     43#define IVT_FIRST  0
    4344
    44 #define EXC_COUNT       32
    45 #define IRQ_COUNT       16
     45#define EXC_COUNT  32
     46#define IRQ_COUNT  16
    4647
    47 #define IVT_EXCBASE     0
    48 #define IVT_IRQBASE     (IVT_EXCBASE + EXC_COUNT)
    49 #define IVT_FREEBASE    (IVT_IRQBASE + IRQ_COUNT)
     48#define IVT_EXCBASE   0
     49#define IVT_IRQBASE   (IVT_EXCBASE + EXC_COUNT)
     50#define IVT_FREEBASE  (IVT_IRQBASE + IRQ_COUNT)
    5051
    51 #define IRQ_CLK         0
    52 #define IRQ_KBD         1
    53 #define IRQ_PIC1        2
    54 #define IRQ_PIC_SPUR    7
    55 #define IRQ_MOUSE       12
     52#define IRQ_CLK       0
     53#define IRQ_KBD       1
     54#define IRQ_PIC1      2
     55#define IRQ_PIC_SPUR  7
     56#define IRQ_MOUSE     12
     57#define IRQ_NE2000    5
    5658
    57 /* this one must have four least significant bits set to ones */
    58 #define VECTOR_APIC_SPUR        (IVT_ITEMS - 1)
     59/* This one must have four least significant bits set to ones */
     60#define VECTOR_APIC_SPUR  (IVT_ITEMS - 1)
    5961
    6062#if (((VECTOR_APIC_SPUR + 1) % 16) || VECTOR_APIC_SPUR >= IVT_ITEMS)
    … …  
    6264#endif
    6365
    64 #define VECTOR_DEBUG                    1
    65 #define VECTOR_CLK                      (IVT_IRQBASE + IRQ_CLK)
    66 #define VECTOR_PIC_SPUR                 (IVT_IRQBASE + IRQ_PIC_SPUR)
    67 #define VECTOR_SYSCALL                  IVT_FREEBASE
    68 #define VECTOR_TLB_SHOOTDOWN_IPI        (IVT_FREEBASE + 1)
    69 #define VECTOR_DEBUG_IPI                (IVT_FREEBASE + 2)
     66#define VECTOR_DEBUG              1
     67#define VECTOR_CLK                (IVT_IRQBASE + IRQ_CLK)
     68#define VECTOR_PIC_SPUR           (IVT_IRQBASE + IRQ_PIC_SPUR)
     69#define VECTOR_SYSCALL            IVT_FREEBASE
     70#define VECTOR_TLB_SHOOTDOWN_IPI  (IVT_FREEBASE + 1)
     71#define VECTOR_DEBUG_IPI          (IVT_FREEBASE + 2)
    7072
    71 typedef struct {
    72         uint32_t eax;
    73         uint32_t ecx;
    74         uint32_t edx;
     73extern void (* disable_irqs_function)(uint16_t);
     74extern void (* enable_irqs_function)(uint16_t);
     75extern void (* eoi_function)(void);
     76extern const char *irqs_info;
    7577
    76         uint32_t gs;
    77         uint32_t fs;
    78         uint32_t es;
    79         uint32_t ds;
    80 
    81         uint32_t error_word;
    82         uint32_t eip;
    83         uint32_t cs;
    84         uint32_t eflags;
    85         uint32_t stack[];
    86 } istate_t;
    87 
    88 /** Return true if exception happened while in userspace */
    89 static inline int istate_from_uspace(istate_t *istate)
    90 {
    91         return !(istate->eip & 0x80000000);
    92 }
    93 
    94 static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr)
    95 {
    96         istate->eip = retaddr;
    97 }
    98 
    99 static inline unative_t istate_get_pc(istate_t *istate)
    100 {
    101         return istate->eip;
    102 }
    103 
    104 extern void (* disable_irqs_function)(uint16_t irqmask);
    105 extern void (* enable_irqs_function)(uint16_t irqmask);
    106 extern void (* eoi_function)(void);
    107 
    108 extern void decode_istate(istate_t *istate);
    10978extern void interrupt_init(void);
    110 extern void trap_virtual_enable_irqs(uint16_t irqmask);
    111 extern void trap_virtual_disable_irqs(uint16_t irqmask);
     79extern void trap_virtual_enable_irqs(uint16_t);
     80extern void trap_virtual_disable_irqs(uint16_t);
    11281
    11382#endif

  • kernel/arch/ia32/include/istate.h

    rb50b5af2 r04803bf  
    2727 */
    2828
    29 /** @addtogroup sync
     29/** @addtogroup ia32interrupt
    3030 * @{
    3131 */
    … …  
    3333 */
    3434
    35 #ifndef KERN_RWLOCK_H_
    36 #define KERN_RWLOCK_H_
     35#ifndef KERN_ia32_ISTATE_H_
     36#define KERN_ia32_ISTATE_H_
    3737
    38 #include <arch/types.h>
    39 #include <synch/mutex.h>
    40 #include <synch/synch.h>
    41 #include <synch/spinlock.h>
     38#ifdef KERNEL
    4239
    43 typedef enum {
    44         RWLOCK_NONE,
    45         RWLOCK_READER,
    46         RWLOCK_WRITER
    47 } rwlock_type_t;
     40#include <typedefs.h>
     41#include <trace.h>
    4842
    49 typedef struct {
    50         SPINLOCK_DECLARE(lock);
    51         /**
    52          * Mutex for writers, readers can bypass it if readers_in is positive.
     43#else /* KERNEL */
     44
     45#include <sys/types.h>
     46
     47#define NO_TRACE
     48
     49#endif /* KERNEL */
     50
     51typedef struct istate {
     52        /*
     53         * The strange order of the GPRs is given by the requirement to use the
     54         * istate structure for both regular interrupts and exceptions as well
     55         * as for syscall handlers which use this order as an optimization.
    5356         */
    54         mutex_t exclusive;
    55         /** Number of readers in critical section. */
    56         size_t readers_in;
    57 } rwlock_t;
     57        uint32_t edx;
     58        uint32_t ecx;
     59        uint32_t ebx;
     60        uint32_t esi;
     61        uint32_t edi;
     62        uint32_t ebp;
     63        uint32_t eax;
     64       
     65        uint32_t ebp_frame;  /* imitation of frame pointer linkage */
     66        uint32_t eip_frame;  /* imitation of return address linkage */
     67       
     68        uint32_t gs;
     69        uint32_t fs;
     70        uint32_t es;
     71        uint32_t ds;
     72       
     73        uint32_t error_word;  /* real or fake error word */
     74        uint32_t eip;
     75        uint32_t cs;
     76        uint32_t eflags;
     77        uint32_t esp;         /* only if istate_t is from uspace */
     78        uint32_t ss;          /* only if istate_t is from uspace */
     79} istate_t;
    5880
    59 #define rwlock_write_lock(rwl) \
    60         _rwlock_write_lock_timeout((rwl), SYNCH_NO_TIMEOUT, SYNCH_FLAGS_NONE)
    61 #define rwlock_read_lock(rwl) \
    62         _rwlock_read_lock_timeout((rwl), SYNCH_NO_TIMEOUT, SYNCH_FLAGS_NONE)
    63 #define rwlock_write_trylock(rwl) \
    64         _rwlock_write_lock_timeout((rwl), SYNCH_NO_TIMEOUT, \
    65             SYNCH_FLAGS_NON_BLOCKING)
    66 #define rwlock_read_trylock(rwl) \
    67         _rwlock_read_lock_timeout((rwl), SYNCH_NO_TIMEOUT, \
    68             SYNCH_FLAGS_NON_BLOCKING)
    69 #define rwlock_write_lock_timeout(rwl, usec) \
    70         _rwlock_write_lock_timeout((rwl), (usec), SYNCH_FLAGS_NONE)
    71 #define rwlock_read_lock_timeout(rwl, usec) \
    72         _rwlock_read_lock_timeout((rwl), (usec), SYNCH_FLAGS_NONE)
     81/** Return true if exception happened while in userspace */
     82NO_TRACE static inline int istate_from_uspace(istate_t *istate)
     83{
     84        return !(istate->eip & UINT32_C(0x80000000));
     85}
    7386
    74 extern void rwlock_initialize(rwlock_t *rwl);
    75 extern void rwlock_read_unlock(rwlock_t *rwl);
    76 extern void rwlock_write_unlock(rwlock_t *rwl);
    77 extern int _rwlock_read_lock_timeout(rwlock_t *rwl, uint32_t usec, int flags);
    78 extern int _rwlock_write_lock_timeout(rwlock_t *rwl, uint32_t usec, int flags);
     87NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
     88    uintptr_t retaddr)
     89{
     90        istate->eip = retaddr;
     91}
     92
     93NO_TRACE static inline uintptr_t istate_get_pc(istate_t *istate)
     94{
     95        return istate->eip;
     96}
     97
     98NO_TRACE static inline uintptr_t istate_get_fp(istate_t *istate)
     99{
     100        return istate->ebp;
     101}
    79102
    80103#endif

  • kernel/arch/ia32/include/memstr.h

    rb50b5af2 r04803bf  
    2727 */
    2828
    29 /** @addtogroup ia32   
     29/** @addtogroup ia32
    3030 * @{
    3131 */
    … …  
    3838#define memcpy(dst, src, cnt)  __builtin_memcpy((dst), (src), (cnt))
    3939
    40 extern void memsetw(void *dst, size_t cnt, uint16_t x);
    41 extern void memsetb(void *dst, size_t cnt, uint8_t x);
    42 
    43 extern int memcmp(const void *a, const void *b, size_t cnt);
     40extern void memsetw(void *, size_t, uint16_t);
     41extern void memsetb(void *, size_t, uint8_t);
    4442
    4543#endif

  • kernel/arch/ia32/include/mm/as.h

    rb50b5af2 r04803bf  
    2727 */
    2828
    29 /** @addtogroup ia32mm 
     29/** @addtogroup ia32mm
    3030 * @{
    3131 */
    … …  
    3636#define KERN_ia32_AS_H_
    3737
    38 #define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH      0
     38#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH  0
    3939
    40 #define KERNEL_ADDRESS_SPACE_START_ARCH         ((unsigned long) 0x80000000)
    41 #define KERNEL_ADDRESS_SPACE_END_ARCH           ((unsigned long) 0xffffffff)
    42 #define USER_ADDRESS_SPACE_START_ARCH           ((unsigned long) 0x00000000)
    43 #define USER_ADDRESS_SPACE_END_ARCH             ((unsigned long) 0x7fffffff)
     40#define KERNEL_ADDRESS_SPACE_START_ARCH  UINT32_C(0x80000000)
     41#define KERNEL_ADDRESS_SPACE_END_ARCH    UINT32_C(0xffffffff)
     42#define USER_ADDRESS_SPACE_START_ARCH    UINT32_C(0x00000000)
     43#define USER_ADDRESS_SPACE_END_ARCH      UINT32_C(0x7fffffff)
    4444
    45 #define USTACK_ADDRESS_ARCH     (USER_ADDRESS_SPACE_END_ARCH - (PAGE_SIZE - 1))
     45#define USTACK_ADDRESS_ARCH  (USER_ADDRESS_SPACE_END_ARCH - (PAGE_SIZE - 1))
    4646
    4747typedef struct {
    … …  
    5050#include <genarch/mm/as_pt.h>
    5151
    52 #define as_constructor_arch(as, flags)          (as != as)
    53 #define as_destructor_arch(as)                  (as != as)
    54 #define as_create_arch(as, flags)               (as != as)
     52#define as_constructor_arch(as, flags)  (as != as)
     53#define as_destructor_arch(as)          (as != as)
     54#define as_create_arch(as, flags)       (as != as)
    5555#define as_install_arch(as)
    5656#define as_deinstall_arch(as)

  • kernel/arch/ia32/include/mm/asid.h

    rb50b5af2 r04803bf  
    2727 */
    2828
    29 /** @addtogroup ia32mm 
     29/** @addtogroup ia32mm
    3030 * @{
    3131 */
    … …  
    4343#define KERN_ia32_ASID_H_
    4444
    45 #include <arch/types.h>
     45#include <typedefs.h>
    4646
    4747typedef int32_t asid_t;
    4848
    49 #define ASID_MAX_ARCH           3
     49#define ASID_MAX_ARCH  3
    5050
    51 #define asid_get()              (ASID_START + 1)
     51#define asid_get()  (ASID_START + 1)
    5252#define asid_put(asid)
    5353

  • kernel/arch/ia32/include/mm/frame.h

    rb50b5af2 r04803bf  
    4242#ifndef __ASM__
    4343
    44 #include <arch/types.h>
     44#include <typedefs.h>
    4545
    4646extern uintptr_t last_frame;

  • kernel/arch/ia32/include/mm/page.h

    rb50b5af2 r04803bf  
    2727 */
    2828
    29 /** @addtogroup ia32mm 
     29/** @addtogroup ia32mm
    3030 * @{
    3131 */
    … …  
    3737
    3838#include <arch/mm/frame.h>
    39 
    40 #define PAGE_WIDTH      FRAME_WIDTH
    41 #define PAGE_SIZE       FRAME_SIZE
     39#include <trace.h>
     40
     41#define PAGE_WIDTH  FRAME_WIDTH
     42#define PAGE_SIZE   FRAME_SIZE
    4243
    4344#ifdef KERNEL
    4445
    4546#ifndef __ASM__
    46 #       define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
    47 #       define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)
    48 #else
    49 #       define KA2PA(x) ((x) - 0x80000000)
    50 #       define PA2KA(x) ((x) + 0x80000000)
    51 #endif
     47
     48#define KA2PA(x)  (((uintptr_t) (x)) - UINT32_C(0x80000000))
     49#define PA2KA(x)  (((uintptr_t) (x)) + UINT32_C(0x80000000))
     50
     51#else /* __ASM__ */
     52
     53#define KA2PA(x)  ((x) - 0x80000000)
     54#define PA2KA(x)  ((x) + 0x80000000)
     55
     56#endif /* __ASM__ */
    5257
    5358/*
    … …  
    5762
    5863/* Number of entries in each level. */
    59 #define PTL0_ENTRIES_ARCH       1024
    60 #define PTL1_ENTRIES_ARCH       0
    61 #define PTL2_ENTRIES_ARCH       0
    62 #define PTL3_ENTRIES_ARCH       1024
     64#define PTL0_ENTRIES_ARCH  1024
     65#define PTL1_ENTRIES_ARCH  0
     66#define PTL2_ENTRIES_ARCH  0
     67#define PTL3_ENTRIES_ARCH  1024
    6368
    6469/* Page table sizes for each level. */
    65 #define PTL0_SIZE_ARCH          ONE_FRAME
    66 #define PTL1_SIZE_ARCH          0
    67 #define PTL2_SIZE_ARCH          0
    68 #define PTL3_SIZE_ARCH          ONE_FRAME
     70#define PTL0_SIZE_ARCH  ONE_FRAME
     71#define PTL1_SIZE_ARCH  0
     72#define PTL2_SIZE_ARCH  0
     73#define PTL3_SIZE_ARCH  ONE_FRAME
    6974
    7075/* Macros calculating indices for each level. */
    71 #define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 22) & 0x3ff)
    72 #define PTL1_INDEX_ARCH(vaddr)  0
    73 #define PTL2_INDEX_ARCH(vaddr)  0
    74 #define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x3ff)
     76#define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 22) & 0x3ffU)
     77#define PTL1_INDEX_ARCH(vaddr)  0
     78#define PTL2_INDEX_ARCH(vaddr)  0
     79#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x3ffU)
    7580
    7681/* Get PTE address accessors for each level. */
    … …  
    105110
    106111/* Set PTE flags accessors for each level. */
    107 #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
     112#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
    108113        set_pt_flags((pte_t *) (ptl0), (size_t) (i), (x))
    109114#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
    … …  
    121126#define PTE_WRITABLE_ARCH(p) \
    122127        ((p)->writeable != 0)
    123 #define PTE_EXECUTABLE_ARCH(p)                  1
     128#define PTE_EXECUTABLE_ARCH(p)  1
    124129
    125130#ifndef __ASM__
    … …  
    127132#include <mm/mm.h>
    128133#include <arch/interrupt.h>
    129 #include <arch/types.h>
    130134#include <typedefs.h>
    131135
    … …  
    144148
    145149/** When bit on this position is 1, a reserved bit was set in page directory. */
    146 #define PFERR_CODE_RSVD         (1 << 3)       
    147 
    148 static inline int get_pt_flags(pte_t *pt, size_t i)
     150#define PFERR_CODE_RSVD         (1 << 3)
     151
     152/** Page Table Entry. */
     153typedef struct {
     154        unsigned present : 1;
     155        unsigned writeable : 1;
     156        unsigned uaccessible : 1;
     157        unsigned page_write_through : 1;
     158        unsigned page_cache_disable : 1;
     159        unsigned accessed : 1;
     160        unsigned dirty : 1;
     161        unsigned pat : 1;
     162        unsigned global : 1;
     163        unsigned soft_valid : 1;        /**< Valid content even if the present bit is not set. */
     164        unsigned avl : 2;
     165        unsigned frame_address : 20;
     166} __attribute__ ((packed)) pte_t;
     167
     168NO_TRACE static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
    149169{
    150170        pte_t *p = &pt[i];
    … …  
    159179}
    160180
    161 static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
     181NO_TRACE static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
    162182{
    163183        pte_t *p = &pt[i];
    … …  
    177197
    178198extern void page_arch_init(void);
    179 extern void page_fault(int n, istate_t *istate);
     199extern void page_fault(unsigned int, istate_t *);
    180200
    181201#endif /* __ASM__ */

  • kernel/arch/ia32/include/pm.h

    rb50b5af2 r04803bf  
    5858#endif /* CONFIG_FB */
    5959
    60 #define gdtselector(des)  ((des) << 3)
     60#define GDT_SELECTOR(des)  ((des) << 3)
    6161
    6262#define PL_KERNEL  0
    … …  
    6767#define AR_CODE       (3 << 3)
    6868#define AR_WRITABLE   (1 << 1)
    69 #define AR_INTERRUPT  (0x0e)
    70 #define AR_TSS        (0x09)
     69#define AR_INTERRUPT  (0xe)
     70#define AR_TRAP       (0xf)
     71#define AR_TSS        (0x9)
    7172
    7273#define DPL_KERNEL  (PL_KERNEL << 5)
    … …  
    7475
    7576#define TSS_BASIC_SIZE  104
    76 #define TSS_IOMAP_SIZE  (16 * 1024 + 1)  /* 16K for bitmap + 1 terminating byte for convenience */
     77#define TSS_IOMAP_SIZE  (8 * 1024 + 1)  /* 8K for bitmap + 1 terminating byte for convenience */
    7778
    7879#define IO_PORTS  (64 * 1024)
    … …  
    8081#ifndef __ASM__
    8182
    82 #include <arch/types.h>
     83#include <typedefs.h>
    8384#include <arch/context.h>
    8485
    … …  
    152153
    153154extern ptr_16_32_t gdtr;
    154 extern ptr_16_32_t bootstrap_gdtr;
    155155extern ptr_16_32_t protected_ap_gdtr;
    156156extern tss_t *tss_p;

  • kernel/arch/ia32/include/proc/task.h

    rb50b5af2 r04803bf  
    3636#define KERN_ia32_TASK_H_
    3737
    38 #include <arch/types.h>
     38#include <typedefs.h>
    3939#include <adt/bitmap.h>
    4040

  • kernel/arch/ia32/include/proc/thread.h

    rb50b5af2 r04803bf  
    3636#define KERN_ia32_THREAD_H_
    3737
    38 #include <arch/types.h>
     38#include <typedefs.h>
    3939
    4040typedef struct {
    41         unative_t tls;
     41        sysarg_t tls;
    4242} thread_arch_t;
    4343
    44 #define thr_constructor_arch(t)
    45 #define thr_destructor_arch(t)
     44#define thr_constructor_arch(thr)
     45#define thr_destructor_arch(thr)
    4646
    4747#endif

  • kernel/arch/ia32/include/smp/ap.h

    rb50b5af2 r04803bf  
    2727 */
    2828
    29 /** @addtogroup ia32   
     29/** @addtogroup ia32
    3030 * @{
    3131 */

  • kernel/arch/ia32/include/smp/apic.h

    rb50b5af2 r04803bf  
    2727 */
    2828
    29 /** @addtogroup ia32   
     29/** @addtogroup ia32
    3030 * @{
    3131 */
    … …  
    3636#define KERN_ia32_APIC_H_
    3737
    38 #include <arch/types.h>
     38#include <typedefs.h>
    3939#include <cpu.h>
    4040
    41 #define FIXED           (0<<0)
    42 #define LOPRI           (1<<0)
    43 
    44 #define APIC_ID_COUNT   16
     41#define FIXED  (0 << 0)
     42#define LOPRI  (1 << 0)
     43
     44#define APIC_ID_COUNT  16
    4545
    4646/* local APIC macros */
    47 #define IPI_INIT        0
    48 #define IPI_STARTUP     0
     47#define IPI_INIT     0
     48#define IPI_STARTUP  0
    4949
    5050/** Delivery modes. */
    51 #define DELMOD_FIXED    0x0
    52 #define DELMOD_LOWPRI   0x1
    53 #define DELMOD_SMI      0x2
     51#define DELMOD_FIXED    0x0U
     52#define DELMOD_LOWPRI   0x1U
     53#define DELMOD_SMI      0x2U
    5454/* 0x3 reserved */
    55 #define DELMOD_NMI      0x4
    56 #define DELMOD_INIT     0x5
    57 #define DELMOD_STARTUP  0x6
    58 #define DELMOD_EXTINT   0x7
     55#define DELMOD_NMI      0x4U
     56#define DELMOD_INIT     0x5U
     57#define DELMOD_STARTUP  0x6U
     58#define DELMOD_EXTINT   0x7U
    5959
    6060/** Destination modes. */
    61 #define DESTMOD_PHYS    0x0
    62 #define DESTMOD_LOGIC   0x1
     61#define DESTMOD_PHYS   0x0U
     62#define DESTMOD_LOGIC  0x1U
    6363
    6464/** Trigger Modes. */
    65 #define TRIGMOD_EDGE    0x0
    66 #define TRIGMOD_LEVEL   0x1
     65#define TRIGMOD_EDGE   0x0U
     66#define TRIGMOD_LEVEL  0x1U
    6767
    6868/** Levels. */
    69 #define LEVEL_DEASSERT  0x0
    70 #define LEVEL_ASSERT    0x1
     69#define LEVEL_DEASSERT  0x0U
     70#define LEVEL_ASSERT    0x1U
    7171
    7272/** Destination Shorthands. */
    73 #define SHORTHAND_NONE          0x0
    74 #define SHORTHAND_SELF          0x1
    75 #define SHORTHAND_ALL_INCL      0x2
    76 #define SHORTHAND_ALL_EXCL      0x3
     73#define SHORTHAND_NONE      0x0U
     74#define SHORTHAND_SELF      0x1U
     75#define SHORTHAND_ALL_INCL  0x2U
     76#define SHORTHAND_ALL_EXCL  0x3U
    7777
    7878/** Interrupt Input Pin Polarities. */
    79 #define POLARITY_HIGH   0x0
    80 #define POLARITY_LOW    0x1
     79#define POLARITY_HIGH  0x0U
     80#define POLARITY_LOW   0x1U
    8181
    8282/** Divide Values. (Bit 2 is always 0) */
    83 #define DIVIDE_2        0x0
    84 #define DIVIDE_4        0x1
    85 #define DIVIDE_8        0x2
    86 #define DIVIDE_16       0x3
    87 #define DIVIDE_32       0x8
    88 #define DIVIDE_64       0x9
    89 #define DIVIDE_128      0xa
    90 #define DIVIDE_1        0xb
     83#define DIVIDE_2    0x0U
     84#define DIVIDE_4    0x1U
     85#define DIVIDE_8    0x2U
     86#define DIVIDE_16   0x3U
     87#define DIVIDE_32   0x8U
     88#define DIVIDE_64   0x9U
     89#define DIVIDE_128  0xaU
     90#define DIVIDE_1    0xbU
    9191
    9292/** Timer Modes. */
    93 #define TIMER_ONESHOT   0x0
    94 #define TIMER_PERIODIC  0x1
     93#define TIMER_ONESHOT   0x0U
     94#define TIMER_PERIODIC  0x1U
    9595
    9696/** Delivery status. */
    97 #define DELIVS_IDLE     0x0
    98 #define DELIVS_PENDING  0x1
     97#define DELIVS_IDLE     0x0U
     98#define DELIVS_PENDING  0x1U
    9999
    100100/** Destination masks. */
    101 #define DEST_ALL        0xff
     101#define DEST_ALL  0xffU
    102102
    103103/** Dest format models. */
    104 #define MODEL_FLAT      0xf
    105 #define MODEL_CLUSTER   0x0
     104#define MODEL_FLAT     0xfU
     105#define MODEL_CLUSTER  0x0U
    106106
    107107/** Interrupt Command Register. */
    108 #define ICRlo           (0x300 / sizeof(uint32_t))
    109 #define ICRhi           (0x310 / sizeof(uint32_t))
     108#define ICRlo  (0x300U / sizeof(uint32_t))
     109#define ICRhi  (0x310U / sizeof(uint32_t))
     110
    110111typedef struct {
    111112        union {
    112113                uint32_t lo;
    113114                struct {
    114                         uint8_t vector;                 /**< Interrupt Vector. */
    115                         unsigned delmod : 3;            /**< Delivery Mode. */
    116                         unsigned destmod : 1;           /**< Destination Mode. */
    117                         unsigned delivs : 1;            /**< Delivery status (RO). */
    118                         unsigned : 1;                   /**< Reserved. */
    119                         unsigned level : 1;             /**< Level. */
    120                         unsigned trigger_mode : 1;      /**< Trigger Mode. */
    121                         unsigned : 2;                   /**< Reserved. */
    122                         unsigned shorthand : 2;         /**< Destination Shorthand. */
    123                         unsigned : 12;                  /**< Reserved. */
     115                        uint8_t vector;                 /**< Interrupt Vector. */
     116                        unsigned int delmod : 3;        /**< Delivery Mode. */
     117                        unsigned int destmod : 1;       /**< Destination Mode. */
     118                        unsigned int delivs : 1;        /**< Delivery status (RO). */
     119                        unsigned int : 1;               /**< Reserved. */
     120                        unsigned int level : 1;         /**< Level. */
     121                        unsigned int trigger_mode : 1;  /**< Trigger Mode. */
     122                        unsigned int : 2;               /**< Reserved. */
     123                        unsigned int shorthand : 2;     /**< Destination Shorthand. */
     124                        unsigned int : 12;              /**< Reserved. */
    124125                } __attribute__ ((packed));
    125126        };
    … …  
    127128                uint32_t hi;
    128129                struct {
    129                         unsigned : 24;                  /**< Reserved. */
    130                         uint8_t dest;                   /**< Destination field. */
     130                        unsigned int : 24;  /**< Reserved. */
     131                        uint8_t dest;       /**< Destination field. */
    131132                } __attribute__ ((packed));
    132133        };
    … …  
    134135
    135136/* End Of Interrupt. */
    136 #define EOI             (0x0b0 / sizeof(uint32_t))
     137#define EOI  (0x0b0U / sizeof(uint32_t))
    137138
    138139/** Error Status Register. */
    139 #define ESR             (0x280 / sizeof(uint32_t))
     140#define ESR  (0x280U / sizeof(uint32_t))
     141
    140142typedef union {
    141143        uint32_t value;
    142144        uint8_t err_bitmap;
    143145        struct {
    144                 unsigned send_checksum_error : 1;
    145                 unsigned receive_checksum_error : 1;
    146                 unsigned send_accept_error : 1;
    147                 unsigned receive_accept_error : 1;
    148                 unsigned : 1;
    149                 unsigned send_illegal_vector : 1;
    150                 unsigned received_illegal_vector : 1;
    151                 unsigned illegal_register_address : 1;
    152                 unsigned : 24;
     146                unsigned int send_checksum_error : 1;
     147                unsigned int receive_checksum_error : 1;
     148                unsigned int send_accept_error : 1;
     149                unsigned int receive_accept_error : 1;
     150                unsigned int : 1;
     151                unsigned int send_illegal_vector : 1;
     152                unsigned int received_illegal_vector : 1;
     153                unsigned int illegal_register_address : 1;
     154                unsigned int : 24;
    153155        } __attribute__ ((packed));
    154156} esr_t;
    155157
    156158/* Task Priority Register */
    157 #define TPR             (0x080 / sizeof(uint32_t))
    158 typedef union {
    159         uint32_t value;
    160         struct {
    161                 unsigned pri_sc : 4;            /**< Task Priority Sub-Class. */
    162                 unsigned pri : 4;               /**< Task Priority. */
     159#define TPR  (0x080U / sizeof(uint32_t))
     160
     161typedef union {
     162        uint32_t value;
     163        struct {
     164                unsigned int pri_sc : 4;  /**< Task Priority Sub-Class. */
     165                unsigned int pri : 4;     /**< Task Priority. */
    163166        } __attribute__ ((packed));
    164167} tpr_t;
    165168
    166169/** Spurious-Interrupt Vector Register. */
    167 #define SVR             (0x0f0 / sizeof(uint32_t))
    168 typedef union {
    169         uint32_t value;
    170         struct {
    171                 uint8_t vector;                 /**< Spurious Vector. */
    172                 unsigned lapic_enabled : 1;     /**< APIC Software Enable/Disable. */
    173                 unsigned focus_checking : 1;    /**< Focus Processor Checking. */
    174                 unsigned : 22;                  /**< Reserved. */
     170#define SVR  (0x0f0U / sizeof(uint32_t))
     171
     172typedef union {
     173        uint32_t value;
     174        struct {
     175                uint8_t vector;                   /**< Spurious Vector. */
     176                unsigned int lapic_enabled : 1;   /**< APIC Software Enable/Disable. */
     177                unsigned int focus_checking : 1;  /**< Focus Processor Checking. */
     178                unsigned int : 22;                /**< Reserved. */
    175179        } __attribute__ ((packed));
    176180} svr_t;
    177181
    178182/** Time Divide Configuration Register. */
    179 #define TDCR            (0x3e0 / sizeof(uint32_t))
    180 typedef union {
    181         uint32_t value;
    182         struct {
    183                 unsigned div_value : 4;         /**< Divide Value, bit 2 is always 0. */
    184                 unsigned : 28;                  /**< Reserved. */
     183#define TDCR  (0x3e0U / sizeof(uint32_t))
     184
     185typedef union {
     186        uint32_t value;
     187        struct {
     188                unsigned int div_value : 4;  /**< Divide Value, bit 2 is always 0. */
     189                unsigned int : 28;           /**< Reserved. */
    185190        } __attribute__ ((packed));
    186191} tdcr_t;
    187192
    188193/* Initial Count Register for Timer */
    189 #define ICRT            (0x380 / sizeof(uint32_t))
     194#define ICRT  (0x380U / sizeof(uint32_t))
    190195
    191196/* Current Count Register for Timer */
    192 #define CCRT            (0x390 / sizeof(uint32_t))
     197#define CCRT  (0x390U / sizeof(uint32_t))
    193198
    194199/** LVT Timer register. */
    195 #define LVT_Tm          (0x320 / sizeof(uint32_t))
    196 typedef union {
    197         uint32_t value;
    198         struct {
    199                 uint8_t vector;         /**< Local Timer Interrupt vector. */
    200                 unsigned : 4;           /**< Reserved. */
    201                 unsigned delivs : 1;    /**< Delivery status (RO). */
    202                 unsigned : 3;           /**< Reserved. */
    203                 unsigned masked : 1;    /**< Interrupt Mask. */
    204                 unsigned mode : 1;      /**< Timer Mode. */
    205                 unsigned : 14;          /**< Reserved. */
     200#define LVT_Tm  (0x320U / sizeof(uint32_t))
     201
     202typedef union {
     203        uint32_t value;
     204        struct {
     205                uint8_t vector;           /**< Local Timer Interrupt vector. */
     206                unsigned int : 4;         /**< Reserved. */
     207                unsigned int delivs : 1;  /**< Delivery status (RO). */
     208                unsigned int : 3;         /**< Reserved. */
     209                unsigned int masked : 1;  /**< Interrupt Mask. */
     210                unsigned int mode : 1;    /**< Timer Mode. */
     211                unsigned int : 14;        /**< Reserved. */
    206212        } __attribute__ ((packed));
    207213} lvt_tm_t;
    208214
    209215/** LVT LINT registers. */
    210 #define LVT_LINT0       (0x350 / sizeof(uint32_t))
    211 #define LVT_LINT1       (0x360 / sizeof(uint32_t))
    212 typedef union {
    213         uint32_t value;
    214         struct {
    215                 uint8_t vector;                 /**< LINT Interrupt vector. */
    216                 unsigned delmod : 3;            /**< Delivery Mode. */
    217                 unsigned : 1;                   /**< Reserved. */
    218                 unsigned delivs : 1;            /**< Delivery status (RO). */
    219                 unsigned intpol : 1;            /**< Interrupt Input Pin Polarity. */
    220                 unsigned irr : 1;               /**< Remote IRR (RO). */
    221                 unsigned trigger_mode : 1;      /**< Trigger Mode. */
    222                 unsigned masked : 1;            /**< Interrupt Mask. */
    223                 unsigned : 15;                  /**< Reserved. */
     216#define LVT_LINT0  (0x350U / sizeof(uint32_t))
     217#define LVT_LINT1  (0x360U / sizeof(uint32_t))
     218
     219typedef union {
     220        uint32_t value;
     221        struct {
     222                uint8_t vector;                 /**< LINT Interrupt vector. */
     223                unsigned int delmod : 3;        /**< Delivery Mode. */
     224                unsigned int : 1;               /**< Reserved. */
     225                unsigned int delivs : 1;        /**< Delivery status (RO). */
     226                unsigned int intpol : 1;        /**< Interrupt Input Pin Polarity. */
     227                unsigned int irr : 1;           /**< Remote IRR (RO). */
     228                unsigned int trigger_mode : 1;  /**< Trigger Mode. */
     229                unsigned int masked : 1;        /**< Interrupt Mask. */
     230                unsigned int : 15;              /**< Reserved. */
    224231        } __attribute__ ((packed));
    225232} lvt_lint_t;
    226233
    227234/** LVT Error register. */
    228 #define LVT_Err         (0x370 / sizeof(uint32_t))
    229 typedef union {
    230         uint32_t value;
    231         struct {
    232                 uint8_t vector;         /**< Local Timer Interrupt vector. */
    233                 unsigned : 4;           /**< Reserved. */
    234                 unsigned delivs : 1;    /**< Delivery status (RO). */
    235                 unsigned : 3;           /**< Reserved. */
    236                 unsigned masked : 1;    /**< Interrupt Mask. */
    237                 unsigned : 15;          /**< Reserved. */
     235#define LVT_Err  (0x370U / sizeof(uint32_t))
     236
     237typedef union {
     238        uint32_t value;
     239        struct {
     240                uint8_t vector;           /**< Local Timer Interrupt vector. */
     241                unsigned int : 4;         /**< Reserved. */
     242                unsigned int delivs : 1;  /**< Delivery status (RO). */
     243                unsigned int : 3;         /**< Reserved. */
     244                unsigned int masked : 1;  /**< Interrupt Mask. */
     245                unsigned int : 15;        /**< Reserved. */
    238246        } __attribute__ ((packed));
    239247} lvt_error_t;
    240248
    241249/** Local APIC ID Register. */
    242 #define L_APIC_ID       (0x020 / sizeof(uint32_t))
    243 typedef union {
    244         uint32_t value;
    245         struct {
    246                 unsigned : 24;          /**< Reserved. */
    247                 uint8_t apic_id;                /**< Local APIC ID. */
     250#define L_APIC_ID  (0x020U / sizeof(uint32_t))
     251
     252typedef union {
     253        uint32_t value;
     254        struct {
     255                unsigned int : 24;  /**< Reserved. */
     256                uint8_t apic_id;    /**< Local APIC ID. */
    248257        } __attribute__ ((packed));
    249258} l_apic_id_t;
    250259
    251260/** Local APIC Version Register */
    252 #define LAVR            (0x030 / sizeof(uint32_t))
    253 #define LAVR_Mask       0xff
    254 #define is_local_apic(x)        (((x) & LAVR_Mask & 0xf0) == 0x1)
    255 #define is_82489DX_apic(x)      ((((x) & LAVR_Mask & 0xf0) == 0x0))
    256 #define is_local_xapic(x)       (((x) & LAVR_Mask) == 0x14)
     261#define LAVR       (0x030U / sizeof(uint32_t))
     262#define LAVR_Mask  0xffU
     263
     264#define is_local_apic(x)    (((x) & LAVR_Mask & 0xf0U) == 0x1U)
     265#define is_82489DX_apic(x)  ((((x) & LAVR_Mask & 0xf0U) == 0x0U))
     266#define is_local_xapic(x)   (((x) & LAVR_Mask) == 0x14U)
    257267
    258268/** Logical Destination Register. */
    259 #define  LDR            (0x0d0 / sizeof(uint32_t))
    260 typedef union {
    261         uint32_t value;
    262         struct {
    263                 unsigned : 24;          /**< Reserved. */
    264                 uint8_t id;             /**< Logical APIC ID. */
     269#define  LDR  (0x0d0U / sizeof(uint32_t))
     270
     271typedef union {
     272        uint32_t value;
     273        struct {
     274                unsigned int : 24;  /**< Reserved. */
     275                uint8_t id;         /**< Logical APIC ID. */
    265276        } __attribute__ ((packed));
    266277} ldr_t;
    267278
    268279/** Destination Format Register. */
    269 #define DFR             (0x0e0 / sizeof(uint32_t))
    270 typedef union {
    271         uint32_t value;
    272         struct {
    273                 unsigned : 28;          /**< Reserved, all ones. */
    274                 unsigned model : 4;     /**< Model. */
     280#define DFR  (0x0e0U / sizeof(uint32_t))
     281
     282typedef union {
     283        uint32_t value;
     284        struct {
     285                unsigned int : 28;       /**< Reserved, all ones. */
     286                unsigned int model : 4;  /**< Model. */
    275287        } __attribute__ ((packed));
    276288} dfr_t;
    277289
    278290/* IO APIC */
    279 #define IOREGSEL        (0x00 / sizeof(uint32_t))
    280 #define IOWIN           (0x10 / sizeof(uint32_t))
    281 
    282 #define IOAPICID        0x00
    283 #define IOAPICVER       0x01
    284 #define IOAPICARB       0x02
    285 #define IOREDTBL        0x10
     291#define IOREGSEL  (0x00U / sizeof(uint32_t))
     292#define IOWIN     (0x10U / sizeof(uint32_t))
     293
     294#define IOAPICID   0x00U
     295#define IOAPICVER  0x01U
     296#define IOAPICARB  0x02U
     297#define IOREDTBL   0x10U
    286298
    287299/** I/O Register Select Register. */
    … …  
    289301        uint32_t value;
    290302        struct {
    291                 uint8_t reg_addr;               /**< APIC Register Address. */
    292                 unsigned : 24;          /**< Reserved. */
     303                uint8_t reg_addr;   /**< APIC Register Address. */
     304                unsigned int : 24;  /**< Reserved. */
    293305        } __attribute__ ((packed));
    294306} io_regsel_t;
    … …  
    299311                uint32_t lo;
    300312                struct {
    301                         uint8_t intvec;                 /**< Interrupt Vector. */
    302                         unsigned delmod : 3;            /**< Delivery Mode. */
    303                         unsigned destmod : 1;           /**< Destination mode. */
    304                         unsigned delivs : 1;            /**< Delivery status (RO). */
    305                         unsigned intpol : 1;            /**< Interrupt Input Pin Polarity. */
    306                         unsigned irr : 1;               /**< Remote IRR (RO). */
    307                         unsigned trigger_mode : 1;      /**< Trigger Mode. */
    308                         unsigned masked : 1;            /**< Interrupt Mask. */
    309                         unsigned : 15;                  /**< Reserved. */
     313                        uint8_t intvec;                 /**< Interrupt Vector. */
     314                        unsigned int delmod : 3;        /**< Delivery Mode. */
     315                        unsigned int destmod : 1;       /**< Destination mode. */
     316                        unsigned int delivs : 1;        /**< Delivery status (RO). */
     317                        unsigned int intpol : 1;        /**< Interrupt Input Pin Polarity. */
     318                        unsigned int irr : 1;           /**< Remote IRR (RO). */
     319                        unsigned int trigger_mode : 1;  /**< Trigger Mode. */
     320                        unsigned int masked : 1;        /**< Interrupt Mask. */
     321                        unsigned int : 15;              /**< Reserved. */
    310322                } __attribute__ ((packed));
    311323        };
    … …  
    313325                uint32_t hi;
    314326                struct {
    315                         unsigned : 24;                  /**< Reserved. */
    316                         uint8_t dest : 8;                       /**< Destination Field. */
     327                        unsigned int : 24;  /**< Reserved. */
     328                        uint8_t dest : 8;   /**< Destination Field. */
    317329                } __attribute__ ((packed));
    318330        };
    … …  
    325337        uint32_t value;
    326338        struct {
    327                 unsigned : 24;          /**< Reserved. */
    328                 unsigned apic_id : 4;   /**< IO APIC ID. */
    329                 unsigned : 4;           /**< Reserved. */
     339                unsigned int : 24;         /**< Reserved. */
     340                unsigned int apic_id : 4;  /**< IO APIC ID. */
     341                unsigned int : 4;          /**< Reserved. */
    330342        } __attribute__ ((packed));
    331343} io_apic_id_t;
    … …  
    335347
    336348extern uint32_t apic_id_mask;
     349extern uint8_t bsp_l_apic;
    337350
    338351extern void apic_init(void);
    … …  
    340353extern void l_apic_init(void);
    341354extern void l_apic_eoi(void);
    342 extern int l_apic_broadcast_custom_ipi(uint8_t vector);
    343 extern int l_apic_send_init_ipi(uint8_t apicid);
     355extern int l_apic_broadcast_custom_ipi(uint8_t);
     356extern int l_apic_send_init_ipi(uint8_t);
    344357extern void l_apic_debug(void);
    345 extern uint8_t l_apic_id(void);
    346 
    347 extern uint32_t io_apic_read(uint8_t address);
    348 extern void io_apic_write(uint8_t address , uint32_t x);
    349 extern void io_apic_change_ioredtbl(uint8_t pin, uint8_t dest, uint8_t v, int flags);
    350 extern void io_apic_disable_irqs(uint16_t irqmask);
    351 extern void io_apic_enable_irqs(uint16_t irqmask);
     358
     359extern uint32_t io_apic_read(uint8_t);
     360extern void io_apic_write(uint8_t, uint32_t);
     361extern void io_apic_change_ioredtbl(uint8_t pin, uint8_t dest, uint8_t v, unsigned int);
     362extern void io_apic_disable_irqs(uint16_t);
     363extern void io_apic_enable_irqs(uint16_t);
    352364
    353365#endif

  • kernel/arch/ia32/include/smp/mps.h

    rb50b5af2 r04803bf  
    2727 */
    2828
    29 /** @addtogroup ia32   
     29/** @addtogroup ia32
    3030 * @{
    3131 */
    … …  
    3636#define KERN_ia32_MPS_H_
    3737
    38 #include <arch/types.h>
     38#include <typedefs.h>
    3939#include <synch/waitq.h>
    4040#include <config.h>
    4141#include <arch/smp/smp.h>
    4242
    43 #define CT_EXT_ENTRY_TYPE               0
    44 #define CT_EXT_ENTRY_LEN                1
     43#define CT_EXT_ENTRY_TYPE  0
     44#define CT_EXT_ENTRY_LEN   1
    4545
    4646struct mps_fs {
    … …  
    7070        uint16_t ext_table_length;
    7171        uint8_t ext_table_checksum;
    72         uint8_t xxx;
     72        uint8_t reserved;
    7373        uint8_t base_table[0];
    7474} __attribute__ ((packed));
    … …  
    8181        uint8_t cpu_signature[4];
    8282        uint32_t feature_flags;
    83         uint32_t xxx[2];
     83        uint32_t reserved[2];
    8484} __attribute__ ((packed));
    8585
    … …  
    102102        uint8_t intr_type;
    103103        uint8_t poel;
    104         uint8_t xxx;
     104        uint8_t reserved;
    105105        uint8_t src_bus_id;
    106106        uint8_t src_bus_irq;
    … …  
    113113        uint8_t intr_type;
    114114        uint8_t poel;
    115         uint8_t xxx;
     115        uint8_t reserved;
    116116        uint8_t src_bus_id;
    117117        uint8_t src_bus_irq;

  • kernel/arch/ia32/include/smp/smp.h

    rb50b5af2 r04803bf  
    2727 */
    2828
    29 /** @addtogroup ia32   
     29/** @addtogroup ia32
    3030 * @{
    3131 */
    … …  
    3636#define KERN_ia32_SMP_H_
    3737
    38 #include <arch/types.h>
     38#include <typedefs.h>
    3939
    4040/** SMP config opertaions interface. */
    4141struct smp_config_operations {
    42         size_t (* cpu_count)(void);             /**< Return number of detected processors. */
    43         bool (* cpu_enabled)(size_t i); /**< Check whether the processor of index i is enabled. */
    44         bool (*cpu_bootstrap)(size_t i);        /**< Check whether the processor of index i is BSP. */
    45         uint8_t (*cpu_apic_id)(size_t i);               /**< Return APIC ID of the processor of index i. */
    46         int (*irq_to_pin)(unsigned int irq);            /**< Return mapping between irq and APIC pin. */
     42        /** Check whether a processor is enabled. */
     43        bool (* cpu_enabled)(size_t);
     44       
     45        /** Check whether a processor is BSP. */
     46        bool (*cpu_bootstrap)(size_t);
     47       
     48        /** Return APIC ID of a processor. */
     49        uint8_t (*cpu_apic_id)(size_t);
     50       
     51        /** Return mapping between IRQ and APIC pin. */
     52        int (*irq_to_pin)(unsigned int);
    4753};
    4854
    49 extern int smp_irq_to_pin(unsigned int irq);
     55extern int smp_irq_to_pin(unsigned int);
    5056
    5157#endif

  • kernel/arch/ia32/include/types.h

    rb50b5af2 r04803bf  
    2727 */
    2828
    29 /** @addtogroup ia32   
     29/** @addtogroup ia32
    3030 * @{
    3131 */
    … …  
    3636#define KERN_ia32_TYPES_H_
    3737
    38 typedef signed char int8_t;
    39 typedef signed short int16_t;
    40 typedef signed long int32_t;
    41 typedef signed long long int64_t;
    42 
    43 typedef unsigned char uint8_t;
    44 typedef unsigned short uint16_t;
    45 typedef unsigned long uint32_t;
    46 typedef unsigned long long uint64_t;
    47 
    4838typedef uint32_t size_t;
    4939
    … …  
    5343typedef uint32_t ipl_t;
    5444
    55 typedef uint32_t unative_t;
     45typedef uint32_t sysarg_t;
    5646typedef int32_t native_t;
     47typedef uint32_t atomic_count_t;
    5748
    5849typedef struct {
    5950} fncptr_t;
    6051
    61 #define PRIp "x"        /**< Format for uintptr_t. */
    62 #define PRIs "u"        /**< Format for size_t. */
     52#define INTN_C(c)   INT32_C(c)
     53#define UINTN_C(c)  UINT32_C(c)
    6354
    64 #define PRId8 "d"       /**< Format for int8_t. */
    65 #define PRId16 "d"      /**< Format for int16_t. */
    66 #define PRId32 "d"      /**< Format for int32_t. */
    67 #define PRId64 "lld"    /**< Format for int64_t. */
    68 #define PRIdn "d"       /**< Format for native_t. */
    69 
    70 #define PRIu8 "u"       /**< Format for uint8_t. */
    71 #define PRIu16 "u"      /**< Format for uint16_t. */
    72 #define PRIu32 "u"      /**< Format for uint32_t. */
    73 #define PRIu64 "llu"    /**< Format for uint64_t. */
    74 #define PRIun "u"       /**< Format for unative_t. */
    75 
    76 #define PRIx8 "x"       /**< Format for hexadecimal (u)int8_t. */
    77 #define PRIx16 "x"      /**< Format for hexadecimal (u)int16_t. */
    78 #define PRIx32 "x"      /**< Format for hexadecimal (u)uint32_t. */
    79 #define PRIx64 "llx"    /**< Format for hexadecimal (u)int64_t. */
    80 #define PRIxn "x"       /**< Format for hexadecimal (u)native_t. */
    81 
    82 /** Page Table Entry. */
    83 typedef struct {
    84         unsigned present : 1;
    85         unsigned writeable : 1;
    86         unsigned uaccessible : 1;
    87         unsigned page_write_through : 1;
    88         unsigned page_cache_disable : 1;
    89         unsigned accessed : 1;
    90         unsigned dirty : 1;
    91         unsigned pat : 1;
    92         unsigned global : 1;
    93         unsigned soft_valid : 1;        /**< Valid content even if the present bit is not set. */
    94         unsigned avl : 2;
    95         unsigned frame_address : 20;
    96 } __attribute__ ((packed)) pte_t;
     55#define PRIdn  PRId32  /**< Format for native_t. */
     56#define PRIun  PRIu32  /**< Format for sysarg_t. */
     57#define PRIxn  PRIx32  /**< Format for hexadecimal sysarg_t. */
     58#define PRIua  PRIu32  /**< Format for atomic_count_t. */
    9759
    9860#endif
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