Changeset 04803bf in mainline for kernel/arch/ia32/include/atomic.h

Timestamp:

2011-03-21T22:00:17Z (14 years ago)

Author:

Jiri Svoboda <jiri@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

143932e3

Parents:

b50b5af2 (diff), 7308e84 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge mainline changes (needs fixes).

File:

• kernel/arch/ia32/include/atomic.h (modified) (7 diffs)

kernel/arch/ia32/include/atomic.h

@@ -36 +36 @@
 #define KERN_ia32_ATOMIC_H_
 
-#include <arch/types.h>
+#include <typedefs.h>
 #include <arch/barrier.h>
 #include <preemption.h>
+#include <trace.h>
 
-static inline void atomic_inc(atomic_t *val) {
+NO_TRACE static inline void atomic_inc(atomic_t *val)
+{
 #ifdef CONFIG_SMP
         asm volatile (
@@ -54 +56 @@
 }
 
-static inline void atomic_dec(atomic_t *val) {
+NO_TRACE static inline void atomic_dec(atomic_t *val)
+{
 #ifdef CONFIG_SMP
         asm volatile (
@@ -68 +71 @@
 }
 
-static inline long atomic_postinc(atomic_t *val) 
+NO_TRACE static inline atomic_count_t atomic_postinc(atomic_t *val)
 {
-        long r = 1;
+        atomic_count_t r = 1;
         
         asm volatile (
                 "lock xaddl %[r], %[count]\n"
-                : [count] "+m" (val->count), [r] "+r" (r)
+                : [count] "+m" (val->count),
+                  [r] "+r" (r)
         );
         
@@ -80 +84 @@
 }
 
-static inline long atomic_postdec(atomic_t *val) 
+NO_TRACE static inline atomic_count_t atomic_postdec(atomic_t *val)
 {
-        long r = -1;
+        atomic_count_t r = -1;
         
         asm volatile (
                 "lock xaddl %[r], %[count]\n"
-                : [count] "+m" (val->count), [r] "+r"(r)
+                : [count] "+m" (val->count),
+                  [r] "+r" (r)
         );
         
@@ -95 +100 @@
 #define atomic_predec(val)  (atomic_postdec(val) - 1)
 
-static inline uint32_t test_and_set(atomic_t *val) {
-        uint32_t v;
+NO_TRACE static inline atomic_count_t test_and_set(atomic_t *val)
+{
+        atomic_count_t v = 1;
         
         asm volatile (
-                "movl $1, %[v]\n"
                 "xchgl %[v], %[count]\n"
-                : [v] "=r" (v), [count] "+m" (val->count)
+                : [v] "+r" (v),
+                  [count] "+m" (val->count)
         );
         
@@ -108 +114 @@
 
 /** ia32 specific fast spinlock */
-static inline void atomic_lock_arch(atomic_t *val)
+NO_TRACE static inline void atomic_lock_arch(atomic_t *val)
 {
-        uint32_t tmp;
+        atomic_count_t tmp;
         
         preemption_disable();
@@ -124 +130 @@
                 "testl %[tmp], %[tmp]\n"
                 "jnz 0b\n"
-                : [count] "+m" (val->count), [tmp] "=&r" (tmp)
+                : [count] "+m" (val->count),
+                  [tmp] "=&r" (tmp)
         );
+        
         /*
          * Prevent critical section code from bleeding out this way up.