source: mainline/uspace/lib/c/generic/device/hw_res.c@ cccd60c3

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since cccd60c3 was cccd60c3, checked in by Jiri Svoboda <jiri@…>, 8 years ago

hw_res_enable_interrupt should allow enabling individual interrupts.

  • Property mode set to 100644
File size: 3.9 KB
RevLine 
[5cd136ab]1/*
2 * Copyright (c) 2010 Lenka Trochtova
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
[0adddea]28
[5cd136ab]29 /** @addtogroup libc
30 * @{
31 */
32/** @file
33 */
[0adddea]34
[5cd136ab]35#include <device/hw_res.h>
36#include <errno.h>
37#include <async.h>
38#include <malloc.h>
39
[79ae36dd]40int hw_res_get_resource_list(async_sess_t *sess,
41 hw_resource_list_t *hw_resources)
[5cd136ab]42{
[96b02eb9]43 sysarg_t count = 0;
[cf02eaf]44
[79ae36dd]45 async_exch_t *exch = async_exchange_begin(sess);
[561c301]46
[79ae36dd]47 int rc = async_req_1_1(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
[f724e82]48 HW_RES_GET_RESOURCE_LIST, &count);
[cf02eaf]49
[79ae36dd]50 if (rc != EOK) {
51 async_exchange_end(exch);
[be942bc]52 return rc;
[79ae36dd]53 }
[cf02eaf]54
[5cd136ab]55 size_t size = count * sizeof(hw_resource_t);
[79ae36dd]56 hw_resource_t *resources = (hw_resource_t *) malloc(size);
57 if (resources == NULL) {
58 // FIXME: This is protocol violation
59 async_exchange_end(exch);
[be942bc]60 return ENOMEM;
[79ae36dd]61 }
[cf02eaf]62
[79ae36dd]63 rc = async_data_read_start(exch, resources, size);
64 async_exchange_end(exch);
[cf02eaf]65
[be942bc]66 if (rc != EOK) {
[79ae36dd]67 free(resources);
[be942bc]68 return rc;
[5cd136ab]69 }
[cf02eaf]70
[79ae36dd]71 hw_resources->resources = resources;
72 hw_resources->count = count;
[cf02eaf]73
[be942bc]74 return EOK;
[5cd136ab]75}
76
[cccd60c3]77int hw_res_enable_interrupt(async_sess_t *sess, int irq)
[5cd136ab]78{
[79ae36dd]79 async_exch_t *exch = async_exchange_begin(sess);
[561c301]80
[cccd60c3]81 int rc = async_req_2_0(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
82 HW_RES_ENABLE_INTERRUPT, irq);
[79ae36dd]83 async_exchange_end(exch);
[cf02eaf]84
[cccd60c3]85 return rc;
[5cd136ab]86}
[0adddea]87
[561c301]88/** Setup DMA channel to specified place and mode.
89 *
90 * @param channel DMA channel.
91 * @param pa Physical address of the buffer.
92 * @param size DMA buffer size.
93 * @param mode Mode of the DMA channel:
94 * - Read or Write
95 * - Allow automatic reset
96 * - Use address decrement instead of increment
97 * - Use SINGLE/BLOCK/ON DEMAND transfer mode
98 *
[a0d1d9d]99 * @return Error code.
[561c301]100 *
[a0d1d9d]101 */
[9991c47]102int hw_res_dma_channel_setup(async_sess_t *sess,
[301032a]103 unsigned channel, uint32_t pa, uint32_t size, uint8_t mode)
[9991c47]104{
105 async_exch_t *exch = async_exchange_begin(sess);
[561c301]106
[301032a]107 const uint32_t packed = (channel & 0xffff) | (mode << 16);
[a0d1d9d]108 const int ret = async_req_4_0(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
[301032a]109 HW_RES_DMA_CHANNEL_SETUP, packed, pa, size);
[561c301]110
[9991c47]111 async_exchange_end(exch);
[561c301]112
[9991c47]113 return ret;
114}
115
[561c301]116/** Query remaining bytes in the buffer.
117 *
118 * @param channel DMA channel.
119 *
120 * @return Number of bytes remaining in the buffer if positive.
121 * @return Error code if negative.
122 *
[6fd365d]123 */
124int hw_res_dma_channel_remain(async_sess_t *sess, unsigned channel)
125{
126 async_exch_t *exch = async_exchange_begin(sess);
[561c301]127
[6fd365d]128 sysarg_t remain;
129 const int ret = async_req_2_1(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
130 HW_RES_DMA_CHANNEL_REMAIN, channel, &remain);
[561c301]131
[6fd365d]132 async_exchange_end(exch);
[561c301]133
[6fd365d]134 if (ret == EOK)
135 return remain;
[561c301]136
[6fd365d]137 return ret;
138}
139
[0adddea]140/** @}
[be942bc]141 */
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