1 | /*
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2 | * Copyright (c) 2025 Jiri Svoboda
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3 | * Copyright (c) 2010 Lenka Trochtova
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4 | * All rights reserved.
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5 | *
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6 | * Redistribution and use in source and binary forms, with or without
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7 | * modification, are permitted provided that the following conditions
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8 | * are met:
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9 | *
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10 | * - Redistributions of source code must retain the above copyright
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11 | * notice, this list of conditions and the following disclaimer.
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12 | * - Redistributions in binary form must reproduce the above copyright
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13 | * notice, this list of conditions and the following disclaimer in the
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14 | * documentation and/or other materials provided with the distribution.
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15 | * - The name of the author may not be used to endorse or promote products
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16 | * derived from this software without specific prior written permission.
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17 | *
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18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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28 | */
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29 |
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30 | /** @addtogroup libc
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31 | * @{
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32 | */
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33 | /** @file
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34 | */
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35 |
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36 | #include <device/hw_res.h>
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37 | #include <errno.h>
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38 | #include <async.h>
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39 | #include <stdlib.h>
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40 |
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41 | errno_t hw_res_get_resource_list(async_sess_t *sess,
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42 | hw_resource_list_t *hw_resources)
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43 | {
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44 | sysarg_t count = 0;
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45 |
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46 | async_exch_t *exch = async_exchange_begin(sess);
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47 |
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48 | errno_t rc = async_req_1_1(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
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49 | HW_RES_GET_RESOURCE_LIST, &count);
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50 |
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51 | if (rc != EOK) {
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52 | async_exchange_end(exch);
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53 | return rc;
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54 | }
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55 |
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56 | size_t size = count * sizeof(hw_resource_t);
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57 | hw_resource_t *resources = (hw_resource_t *) malloc(size);
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58 | if (resources == NULL) {
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59 | // FIXME: This is protocol violation
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60 | async_exchange_end(exch);
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61 | return ENOMEM;
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62 | }
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63 |
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64 | rc = async_data_read_start(exch, resources, size);
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65 | async_exchange_end(exch);
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66 |
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67 | if (rc != EOK) {
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68 | free(resources);
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69 | return rc;
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70 | }
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71 |
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72 | hw_resources->resources = resources;
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73 | hw_resources->count = count;
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74 |
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75 | return EOK;
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76 | }
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77 |
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78 | errno_t hw_res_enable_interrupt(async_sess_t *sess, int irq)
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79 | {
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80 | async_exch_t *exch = async_exchange_begin(sess);
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81 |
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82 | errno_t rc = async_req_2_0(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
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83 | HW_RES_ENABLE_INTERRUPT, irq);
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84 | async_exchange_end(exch);
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85 |
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86 | return rc;
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87 | }
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88 |
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89 | errno_t hw_res_disable_interrupt(async_sess_t *sess, int irq)
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90 | {
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91 | async_exch_t *exch = async_exchange_begin(sess);
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92 |
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93 | errno_t rc = async_req_2_0(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
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94 | HW_RES_DISABLE_INTERRUPT, irq);
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95 | async_exchange_end(exch);
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96 |
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97 | return rc;
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98 | }
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99 |
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100 | errno_t hw_res_clear_interrupt(async_sess_t *sess, int irq)
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101 | {
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102 | async_exch_t *exch = async_exchange_begin(sess);
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103 |
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104 | errno_t rc = async_req_2_0(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
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105 | HW_RES_CLEAR_INTERRUPT, irq);
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106 | async_exchange_end(exch);
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107 |
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108 | return rc;
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109 | }
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110 |
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111 | /** Setup DMA channel to specified place and mode.
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112 | *
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113 | * @param channel DMA channel.
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114 | * @param pa Physical address of the buffer.
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115 | * @param size DMA buffer size.
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116 | * @param mode Mode of the DMA channel:
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117 | * - Read or Write
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118 | * - Allow automatic reset
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119 | * - Use address decrement instead of increment
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120 | * - Use SINGLE/BLOCK/ON DEMAND transfer mode
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121 | *
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122 | * @return Error code.
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123 | *
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124 | */
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125 | errno_t hw_res_dma_channel_setup(async_sess_t *sess,
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126 | unsigned channel, uint32_t pa, uint32_t size, uint8_t mode)
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127 | {
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128 | async_exch_t *exch = async_exchange_begin(sess);
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129 |
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130 | const uint32_t packed = (channel & 0xffff) | (mode << 16);
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131 | const errno_t ret = async_req_4_0(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
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132 | HW_RES_DMA_CHANNEL_SETUP, packed, pa, size);
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133 |
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134 | async_exchange_end(exch);
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135 |
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136 | return ret;
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137 | }
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138 |
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139 | /** Query remaining bytes in the buffer.
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140 | *
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141 | * @param channel DMA channel.
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142 | *
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143 | * @param[out] rem Number of bytes remaining in the buffer if positive.
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144 | *
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145 | * @return Error code.
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146 | *
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147 | */
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148 | errno_t hw_res_dma_channel_remain(async_sess_t *sess, unsigned channel, size_t *rem)
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149 | {
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150 | async_exch_t *exch = async_exchange_begin(sess);
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151 |
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152 | sysarg_t remain;
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153 | const errno_t ret = async_req_2_1(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
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154 | HW_RES_DMA_CHANNEL_REMAIN, channel, &remain);
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155 |
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156 | async_exchange_end(exch);
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157 |
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158 | if (ret == EOK)
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159 | *rem = remain;
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160 |
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161 | return ret;
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162 | }
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163 |
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164 | /** Query legacy IO claims.
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165 | *
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166 | * @param sess HW res session
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167 | * @param rclaims Place to store the claims
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168 | *
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169 | * @return Error code.
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170 | *
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171 | */
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172 | errno_t hw_res_query_legacy_io(async_sess_t *sess, hw_res_claims_t *rclaims)
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173 | {
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174 | async_exch_t *exch = async_exchange_begin(sess);
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175 |
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176 | sysarg_t claims;
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177 | const errno_t ret = async_req_1_1(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
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178 | HW_RES_QUERY_LEGACY_IO, &claims);
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179 |
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180 | async_exchange_end(exch);
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181 |
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182 | if (ret == EOK)
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183 | *rclaims = claims;
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184 |
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185 | return ret;
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186 | }
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187 |
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188 | /** Claim legacy IO devices.
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189 | *
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190 | * @param sess HW res session
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191 | * @param claims Claims
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192 | *
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193 | * @return Error code.
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194 | *
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195 | */
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196 | errno_t hw_res_claim_legacy_io(async_sess_t *sess, hw_res_claims_t claims)
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197 | {
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198 | async_exch_t *exch = async_exchange_begin(sess);
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199 |
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200 | const errno_t ret = async_req_2_0(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
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201 | HW_RES_CLAIM_LEGACY_IO, claims);
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202 |
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203 | async_exchange_end(exch);
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204 |
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205 | return ret;
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206 | }
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207 |
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208 | /** @}
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209 | */
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