source: mainline/uspace/lib/c/generic/device/hw_res.c

Last change on this file was 832cbe7, checked in by Jiri Svoboda <jiri@…>, 5 months ago

Add proper IDE PCI to ISA fallback mechanism.

To determine if legacy IDE I/O ports are free, isa-ide asks isa,
who asks pciintel. pciintel waits for bus enumeration to complete,
then waits for all functions except the one who is asking
(which is ISA bus) to stabilize. During attach pci-ide will claim
the legacy IDE ports. Thus, if at this point legacy IDE ports
are unclaimed, pciintel tells ISA they are free, which tells isa-ide,
which continues to attach. If they are not free, isa-ide will not
attach.

This works for all use cases, including system without PCI bus,
system with PCI bus, but no (or disabled) PCI IDE, system with PCI
IDE with unrecognized VID/PID (which we will handle in legacy ISA mode).

  • Property mode set to 100644
File size: 5.3 KB
Line 
1/*
2 * Copyright (c) 2025 Jiri Svoboda
3 * Copyright (c) 2010 Lenka Trochtova
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/** @addtogroup libc
31 * @{
32 */
33/** @file
34 */
35
36#include <device/hw_res.h>
37#include <errno.h>
38#include <async.h>
39#include <stdlib.h>
40
41errno_t hw_res_get_resource_list(async_sess_t *sess,
42 hw_resource_list_t *hw_resources)
43{
44 sysarg_t count = 0;
45
46 async_exch_t *exch = async_exchange_begin(sess);
47
48 errno_t rc = async_req_1_1(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
49 HW_RES_GET_RESOURCE_LIST, &count);
50
51 if (rc != EOK) {
52 async_exchange_end(exch);
53 return rc;
54 }
55
56 size_t size = count * sizeof(hw_resource_t);
57 hw_resource_t *resources = (hw_resource_t *) malloc(size);
58 if (resources == NULL) {
59 // FIXME: This is protocol violation
60 async_exchange_end(exch);
61 return ENOMEM;
62 }
63
64 rc = async_data_read_start(exch, resources, size);
65 async_exchange_end(exch);
66
67 if (rc != EOK) {
68 free(resources);
69 return rc;
70 }
71
72 hw_resources->resources = resources;
73 hw_resources->count = count;
74
75 return EOK;
76}
77
78errno_t hw_res_enable_interrupt(async_sess_t *sess, int irq)
79{
80 async_exch_t *exch = async_exchange_begin(sess);
81
82 errno_t rc = async_req_2_0(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
83 HW_RES_ENABLE_INTERRUPT, irq);
84 async_exchange_end(exch);
85
86 return rc;
87}
88
89errno_t hw_res_disable_interrupt(async_sess_t *sess, int irq)
90{
91 async_exch_t *exch = async_exchange_begin(sess);
92
93 errno_t rc = async_req_2_0(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
94 HW_RES_DISABLE_INTERRUPT, irq);
95 async_exchange_end(exch);
96
97 return rc;
98}
99
100errno_t hw_res_clear_interrupt(async_sess_t *sess, int irq)
101{
102 async_exch_t *exch = async_exchange_begin(sess);
103
104 errno_t rc = async_req_2_0(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
105 HW_RES_CLEAR_INTERRUPT, irq);
106 async_exchange_end(exch);
107
108 return rc;
109}
110
111/** Setup DMA channel to specified place and mode.
112 *
113 * @param channel DMA channel.
114 * @param pa Physical address of the buffer.
115 * @param size DMA buffer size.
116 * @param mode Mode of the DMA channel:
117 * - Read or Write
118 * - Allow automatic reset
119 * - Use address decrement instead of increment
120 * - Use SINGLE/BLOCK/ON DEMAND transfer mode
121 *
122 * @return Error code.
123 *
124 */
125errno_t hw_res_dma_channel_setup(async_sess_t *sess,
126 unsigned channel, uint32_t pa, uint32_t size, uint8_t mode)
127{
128 async_exch_t *exch = async_exchange_begin(sess);
129
130 const uint32_t packed = (channel & 0xffff) | (mode << 16);
131 const errno_t ret = async_req_4_0(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
132 HW_RES_DMA_CHANNEL_SETUP, packed, pa, size);
133
134 async_exchange_end(exch);
135
136 return ret;
137}
138
139/** Query remaining bytes in the buffer.
140 *
141 * @param channel DMA channel.
142 *
143 * @param[out] rem Number of bytes remaining in the buffer if positive.
144 *
145 * @return Error code.
146 *
147 */
148errno_t hw_res_dma_channel_remain(async_sess_t *sess, unsigned channel, size_t *rem)
149{
150 async_exch_t *exch = async_exchange_begin(sess);
151
152 sysarg_t remain;
153 const errno_t ret = async_req_2_1(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
154 HW_RES_DMA_CHANNEL_REMAIN, channel, &remain);
155
156 async_exchange_end(exch);
157
158 if (ret == EOK)
159 *rem = remain;
160
161 return ret;
162}
163
164/** Query legacy IO claims.
165 *
166 * @param sess HW res session
167 * @param rclaims Place to store the claims
168 *
169 * @return Error code.
170 *
171 */
172errno_t hw_res_query_legacy_io(async_sess_t *sess, hw_res_claims_t *rclaims)
173{
174 async_exch_t *exch = async_exchange_begin(sess);
175
176 sysarg_t claims;
177 const errno_t ret = async_req_1_1(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
178 HW_RES_QUERY_LEGACY_IO, &claims);
179
180 async_exchange_end(exch);
181
182 if (ret == EOK)
183 *rclaims = claims;
184
185 return ret;
186}
187
188/** Claim legacy IO devices.
189 *
190 * @param sess HW res session
191 * @param claims Claims
192 *
193 * @return Error code.
194 *
195 */
196errno_t hw_res_claim_legacy_io(async_sess_t *sess, hw_res_claims_t claims)
197{
198 async_exch_t *exch = async_exchange_begin(sess);
199
200 const errno_t ret = async_req_2_0(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
201 HW_RES_CLAIM_LEGACY_IO, claims);
202
203 async_exchange_end(exch);
204
205 return ret;
206}
207
208/** @}
209 */
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