source: mainline/uspace/drv/nic/e1k/e1k.c@ a270026

Last change on this file since a270026 was a270026, checked in by Nataliia Korop <n.corop08@…>, 10 months ago

small typos and ccheck
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1/*
2 * Copyright (c) 2011 Zdenek Bouska
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @file e1k.c
30 *
31 * Driver for Intel Pro/1000 8254x Family of Gigabit Ethernet Controllers
32 *
33 */
34
35#include <async.h>
36#include <assert.h>
37#include <stdio.h>
38#include <errno.h>
39#include <adt/list.h>
40#include <align.h>
41#include <byteorder.h>
42#include <as.h>
43#include <ddi.h>
44#include <ddf/log.h>
45#include <ddf/interrupt.h>
46#include <device/hw_res.h>
47#include <device/hw_res_parsed.h>
48#include <pci_dev_iface.h>
49#include <nic.h>
50#include <ops/nic.h>
51#include "e1k.h"
52
53#include "pcapdump_iface.h"
54#include "pcap_iface.h"
55#define NAME "e1k"
56
57#define E1000_DEFAULT_INTERRUPT_INTERVAL_USEC 250
58
59/* Must be power of 8 */
60#define E1000_RX_FRAME_COUNT 128
61#define E1000_TX_FRAME_COUNT 128
62
63#define E1000_RECEIVE_ADDRESS 16
64
65/** Maximum sending frame size */
66#define E1000_MAX_SEND_FRAME_SIZE 2048
67/** Maximum receiving frame size */
68#define E1000_MAX_RECEIVE_FRAME_SIZE 2048
69
70/** nic_driver_data_t* -> e1000_t* cast */
71#define DRIVER_DATA_NIC(nic) \
72 ((e1000_t *) nic_get_specific(nic))
73
74/** ddf_fun_t * -> nic_driver_data_t* cast */
75#define NIC_DATA_FUN(fun) \
76 ((nic_t *) ddf_dev_data_get(ddf_fun_get_dev(fun)))
77
78/** ddf_dev_t * -> nic_driver_data_t* cast */
79#define NIC_DATA_DEV(dev) \
80 ((nic_t *) ddf_dev_data_get(dev))
81
82/** ddf_dev_t * -> e1000_t* cast */
83#define DRIVER_DATA_DEV(dev) \
84 (DRIVER_DATA_NIC(NIC_DATA_DEV(dev)))
85
86/** ddf_fun_t * -> e1000_t* cast */
87#define DRIVER_DATA_FUN(fun) \
88 (DRIVER_DATA_NIC(NIC_DATA_FUN(fun)))
89
90/** Cast pointer to uint64_t
91 *
92 * @param ptr Pointer to cast
93 *
94 * @return The uint64_t pointer representation.
95 *
96 */
97#define PTR_TO_U64(ptr) ((uint64_t) ((uintptr_t) (ptr)))
98
99/** Cast the memaddr part to the void*
100 *
101 * @param memaddr The memaddr value
102 *
103 */
104#define MEMADDR_TO_PTR(memaddr) ((void *) ((size_t) (memaddr)))
105
106#define E1000_REG_BASE(e1000) \
107 ((e1000)->reg_base_virt)
108
109#define E1000_REG_ADDR(e1000, reg) \
110 ((uint32_t *) (E1000_REG_BASE(e1000) + reg))
111
112#define E1000_REG_READ(e1000, reg) \
113 (pio_read_32(E1000_REG_ADDR(e1000, reg)))
114
115#define E1000_REG_WRITE(e1000, reg, value) \
116 (pio_write_32(E1000_REG_ADDR(e1000, reg), value))
117
118/** E1000 device data */
119typedef struct {
120 /** DDF device */
121 ddf_dev_t *dev;
122 /** Parent session */
123 async_sess_t *parent_sess;
124 /** Device configuration */
125 e1000_info_t info;
126
127 /** Physical registers base address */
128 void *reg_base_phys;
129 /** Virtual registers base address */
130 void *reg_base_virt;
131
132 /** Physical tx ring address */
133 uintptr_t tx_ring_phys;
134 /** Virtual tx ring address */
135 void *tx_ring_virt;
136
137 /** Ring of TX frames, physical address */
138 uintptr_t *tx_frame_phys;
139 /** Ring of TX frames, virtual address */
140 void **tx_frame_virt;
141
142 /** Physical rx ring address */
143 uintptr_t rx_ring_phys;
144 /** Virtual rx ring address */
145 void *rx_ring_virt;
146
147 /** Ring of RX frames, physical address */
148 uintptr_t *rx_frame_phys;
149 /** Ring of RX frames, virtual address */
150 void **rx_frame_virt;
151
152 /** VLAN tag */
153 uint16_t vlan_tag;
154
155 /** Add VLAN tag to frame */
156 bool vlan_tag_add;
157
158 /** Used unicast Receive Address count */
159 unsigned int unicast_ra_count;
160
161 /** Used milticast Receive addrress count */
162 unsigned int multicast_ra_count;
163
164 /** The irq assigned */
165 int irq;
166
167 /** Lock for CTRL register */
168 fibril_mutex_t ctrl_lock;
169
170 /** Lock for receiver */
171 fibril_mutex_t rx_lock;
172
173 /** Lock for transmitter */
174 fibril_mutex_t tx_lock;
175
176 /** Lock for EEPROM access */
177 fibril_mutex_t eeprom_lock;
178
179} e1000_t;
180
181/** Global mutex for work with shared irq structure */
182FIBRIL_MUTEX_INITIALIZE(irq_reg_mutex);
183
184static errno_t e1000_get_address(e1000_t *, nic_address_t *);
185static void e1000_eeprom_get_address(e1000_t *, nic_address_t *);
186static errno_t e1000_set_addr(ddf_fun_t *, const nic_address_t *);
187
188static errno_t e1000_defective_get_mode(ddf_fun_t *, uint32_t *);
189static errno_t e1000_defective_set_mode(ddf_fun_t *, uint32_t);
190
191static errno_t e1000_get_cable_state(ddf_fun_t *, nic_cable_state_t *);
192static errno_t e1000_get_device_info(ddf_fun_t *, nic_device_info_t *);
193static errno_t e1000_get_operation_mode(ddf_fun_t *, int *,
194 nic_channel_mode_t *, nic_role_t *);
195static errno_t e1000_set_operation_mode(ddf_fun_t *, int,
196 nic_channel_mode_t, nic_role_t);
197static errno_t e1000_autoneg_enable(ddf_fun_t *, uint32_t);
198static errno_t e1000_autoneg_disable(ddf_fun_t *);
199static errno_t e1000_autoneg_restart(ddf_fun_t *);
200
201static errno_t e1000_vlan_set_tag(ddf_fun_t *, uint16_t, bool, bool);
202
203/** Network interface options for E1000 card driver */
204static nic_iface_t e1000_nic_iface;
205
206/** Network interface options for E1000 card driver */
207static nic_iface_t e1000_nic_iface = {
208 .set_address = &e1000_set_addr,
209 .get_device_info = &e1000_get_device_info,
210 .get_cable_state = &e1000_get_cable_state,
211 .get_operation_mode = &e1000_get_operation_mode,
212 .set_operation_mode = &e1000_set_operation_mode,
213 .autoneg_enable = &e1000_autoneg_enable,
214 .autoneg_disable = &e1000_autoneg_disable,
215 .autoneg_restart = &e1000_autoneg_restart,
216 .vlan_set_tag = &e1000_vlan_set_tag,
217 .defective_get_mode = &e1000_defective_get_mode,
218 .defective_set_mode = &e1000_defective_set_mode,
219};
220
221/** Basic device operations for E1000 driver */
222static ddf_dev_ops_t e1000_dev_ops;
223
224static errno_t e1000_dev_add(ddf_dev_t *);
225
226/** Basic driver operations for E1000 driver */
227static driver_ops_t e1000_driver_ops = {
228 .dev_add = e1000_dev_add
229};
230
231/** Driver structure for E1000 driver */
232static driver_t e1000_driver = {
233 .name = NAME,
234 .driver_ops = &e1000_driver_ops
235};
236
237/* The default implementation callbacks */
238static errno_t e1000_on_activating(nic_t *);
239static errno_t e1000_on_stopping(nic_t *);
240static void e1000_send_frame(nic_t *, void *, size_t);
241
242/** PIO ranges used in the IRQ code. */
243irq_pio_range_t e1000_irq_pio_ranges[] = {
244 {
245 .base = 0,
246 .size = PAGE_SIZE, /* XXX */
247 }
248};
249
250/** Commands to deal with interrupt
251 *
252 */
253irq_cmd_t e1000_irq_commands[] = {
254 {
255 /* Get the interrupt status */
256 .cmd = CMD_PIO_READ_32,
257 .addr = NULL,
258 .dstarg = 2
259 },
260 {
261 .cmd = CMD_AND,
262 .value = ICR_RXT0,
263 .srcarg = 2,
264 .dstarg = 1
265 },
266 {
267 .cmd = CMD_PREDICATE,
268 .value = 2,
269 .srcarg = 1
270 },
271 {
272 /* Disable interrupts until interrupt routine is finished */
273 .cmd = CMD_PIO_WRITE_32,
274 .addr = NULL,
275 .value = 0xffffffff
276 },
277 {
278 .cmd = CMD_ACCEPT
279 }
280};
281
282/** Interrupt code definition */
283irq_code_t e1000_irq_code = {
284 .rangecount = sizeof(e1000_irq_pio_ranges) /
285 sizeof(irq_pio_range_t),
286 .ranges = e1000_irq_pio_ranges,
287 .cmdcount = sizeof(e1000_irq_commands) / sizeof(irq_cmd_t),
288 .cmds = e1000_irq_commands
289};
290
291/** Get the device information
292 *
293 * @param dev NIC device
294 * @param info Information to fill
295 *
296 * @return EOK
297 *
298 */
299static errno_t e1000_get_device_info(ddf_fun_t *dev, nic_device_info_t *info)
300{
301 assert(dev);
302 assert(info);
303
304 memset(info, 0, sizeof(nic_device_info_t));
305
306 info->vendor_id = 0x8086;
307 str_cpy(info->vendor_name, NIC_VENDOR_MAX_LENGTH,
308 "Intel Corporation");
309 str_cpy(info->model_name, NIC_MODEL_MAX_LENGTH,
310 "Intel Pro");
311
312 info->ethernet_support[ETH_10M] = ETH_10BASE_T;
313 info->ethernet_support[ETH_100M] = ETH_100BASE_TX;
314 info->ethernet_support[ETH_1000M] = ETH_1000BASE_T;
315
316 return EOK;
317}
318
319/** Check the cable state
320 *
321 * @param[in] dev device
322 * @param[out] state state to fill
323 *
324 * @return EOK
325 *
326 */
327static errno_t e1000_get_cable_state(ddf_fun_t *fun, nic_cable_state_t *state)
328{
329 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
330 if (E1000_REG_READ(e1000, E1000_STATUS) & (STATUS_LU))
331 *state = NIC_CS_PLUGGED;
332 else
333 *state = NIC_CS_UNPLUGGED;
334
335 return EOK;
336}
337
338static uint16_t e1000_calculate_itr_interval_from_usecs(usec_t useconds)
339{
340 return useconds * 4;
341}
342
343/** Get operation mode of the device
344 *
345 */
346static errno_t e1000_get_operation_mode(ddf_fun_t *fun, int *speed,
347 nic_channel_mode_t *duplex, nic_role_t *role)
348{
349 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
350 uint32_t status = E1000_REG_READ(e1000, E1000_STATUS);
351
352 if (status & STATUS_FD)
353 *duplex = NIC_CM_FULL_DUPLEX;
354 else
355 *duplex = NIC_CM_HALF_DUPLEX;
356
357 uint32_t speed_bits =
358 (status >> STATUS_SPEED_SHIFT) & STATUS_SPEED_ALL;
359
360 if (speed_bits == STATUS_SPEED_10)
361 *speed = 10;
362 else if (speed_bits == STATUS_SPEED_100)
363 *speed = 100;
364 else if ((speed_bits == STATUS_SPEED_1000A) ||
365 (speed_bits == STATUS_SPEED_1000B))
366 *speed = 1000;
367
368 *role = NIC_ROLE_UNKNOWN;
369 return EOK;
370}
371
372static void e1000_link_restart(e1000_t *e1000)
373{
374 fibril_mutex_lock(&e1000->ctrl_lock);
375
376 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
377
378 if (ctrl & CTRL_SLU) {
379 ctrl &= ~(CTRL_SLU);
380 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
381 fibril_mutex_unlock(&e1000->ctrl_lock);
382
383 fibril_usleep(10);
384
385 fibril_mutex_lock(&e1000->ctrl_lock);
386 ctrl = E1000_REG_READ(e1000, E1000_CTRL);
387 ctrl |= CTRL_SLU;
388 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
389 }
390
391 fibril_mutex_unlock(&e1000->ctrl_lock);
392}
393
394/** Set operation mode of the device
395 *
396 */
397static errno_t e1000_set_operation_mode(ddf_fun_t *fun, int speed,
398 nic_channel_mode_t duplex, nic_role_t role)
399{
400 if ((speed != 10) && (speed != 100) && (speed != 1000))
401 return EINVAL;
402
403 if ((duplex != NIC_CM_HALF_DUPLEX) && (duplex != NIC_CM_FULL_DUPLEX))
404 return EINVAL;
405
406 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
407
408 fibril_mutex_lock(&e1000->ctrl_lock);
409 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
410
411 ctrl |= CTRL_FRCSPD;
412 ctrl |= CTRL_FRCDPLX;
413 ctrl &= ~(CTRL_ASDE);
414
415 if (duplex == NIC_CM_FULL_DUPLEX)
416 ctrl |= CTRL_FD;
417 else
418 ctrl &= ~(CTRL_FD);
419
420 ctrl &= ~(CTRL_SPEED_MASK);
421 if (speed == 1000)
422 ctrl |= CTRL_SPEED_1000 << CTRL_SPEED_SHIFT;
423 else if (speed == 100)
424 ctrl |= CTRL_SPEED_100 << CTRL_SPEED_SHIFT;
425 else
426 ctrl |= CTRL_SPEED_10 << CTRL_SPEED_SHIFT;
427
428 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
429
430 fibril_mutex_unlock(&e1000->ctrl_lock);
431
432 e1000_link_restart(e1000);
433
434 return EOK;
435}
436
437/** Enable auto-negotiation
438 *
439 * @param dev Device to update
440 * @param advertisement Ignored on E1000
441 *
442 * @return EOK if advertisement mode set successfully
443 *
444 */
445static errno_t e1000_autoneg_enable(ddf_fun_t *fun, uint32_t advertisement)
446{
447 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
448
449 fibril_mutex_lock(&e1000->ctrl_lock);
450
451 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
452
453 ctrl &= ~(CTRL_FRCSPD);
454 ctrl &= ~(CTRL_FRCDPLX);
455 ctrl |= CTRL_ASDE;
456
457 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
458
459 fibril_mutex_unlock(&e1000->ctrl_lock);
460
461 e1000_link_restart(e1000);
462
463 return EOK;
464}
465
466/** Disable auto-negotiation
467 *
468 * @param dev Device to update
469 *
470 * @return EOK
471 *
472 */
473static errno_t e1000_autoneg_disable(ddf_fun_t *fun)
474{
475 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
476
477 fibril_mutex_lock(&e1000->ctrl_lock);
478
479 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
480
481 ctrl |= CTRL_FRCSPD;
482 ctrl |= CTRL_FRCDPLX;
483 ctrl &= ~(CTRL_ASDE);
484
485 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
486
487 fibril_mutex_unlock(&e1000->ctrl_lock);
488
489 e1000_link_restart(e1000);
490
491 return EOK;
492}
493
494/** Restart auto-negotiation
495 *
496 * @param dev Device to update
497 *
498 * @return EOK if advertisement mode set successfully
499 *
500 */
501static errno_t e1000_autoneg_restart(ddf_fun_t *dev)
502{
503 return e1000_autoneg_enable(dev, 0);
504}
505
506/** Get state of acceptance of weird frames
507 *
508 * @param device Device to check
509 * @param[out] mode Current mode
510 *
511 */
512static errno_t e1000_defective_get_mode(ddf_fun_t *fun, uint32_t *mode)
513{
514 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
515
516 *mode = 0;
517 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
518 if (rctl & RCTL_SBP)
519 *mode = NIC_DEFECTIVE_BAD_CRC | NIC_DEFECTIVE_SHORT;
520
521 return EOK;
522}
523
524/** Set acceptance of weird frames
525 *
526 * @param device Device to update
527 * @param mode Mode to set
528 *
529 * @return ENOTSUP if the mode is not supported
530 * @return EOK of mode was set
531 *
532 */
533static errno_t e1000_defective_set_mode(ddf_fun_t *fun, uint32_t mode)
534{
535 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
536 errno_t rc = EOK;
537
538 fibril_mutex_lock(&e1000->rx_lock);
539
540 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
541 bool short_mode = (mode & NIC_DEFECTIVE_SHORT ? true : false);
542 bool bad_mode = (mode & NIC_DEFECTIVE_BAD_CRC ? true : false);
543
544 if (short_mode && bad_mode)
545 rctl |= RCTL_SBP;
546 else if ((!short_mode) && (!bad_mode))
547 rctl &= ~RCTL_SBP;
548 else
549 rc = ENOTSUP;
550
551 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
552
553 fibril_mutex_unlock(&e1000->rx_lock);
554 return rc;
555}
556
557/** Write receive address to RA registr
558 *
559 * @param e1000 E1000 data structure
560 * @param position RA register position
561 * @param address Ethernet address
562 * @param set_av_bit Set the Addtess Valid bit
563 *
564 */
565static void e1000_write_receive_address(e1000_t *e1000, unsigned int position,
566 const nic_address_t *address, bool set_av_bit)
567{
568 uint8_t *mac0 = (uint8_t *) address->address;
569 uint8_t *mac1 = (uint8_t *) address->address + 1;
570 uint8_t *mac2 = (uint8_t *) address->address + 2;
571 uint8_t *mac3 = (uint8_t *) address->address + 3;
572 uint8_t *mac4 = (uint8_t *) address->address + 4;
573 uint8_t *mac5 = (uint8_t *) address->address + 5;
574
575 uint32_t rah;
576 uint32_t ral;
577
578 ral = ((*mac3) << 24) | ((*mac2) << 16) | ((*mac1) << 8) | (*mac0);
579 rah = ((*mac5) << 8) | ((*mac4));
580
581 if (set_av_bit)
582 rah |= RAH_AV;
583 else
584 rah |= E1000_REG_READ(e1000, E1000_RAH_ARRAY(position)) & RAH_AV;
585
586 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(position), rah);
587 E1000_REG_WRITE(e1000, E1000_RAL_ARRAY(position), ral);
588}
589
590/** Disable receive address in RA registr
591 *
592 * Clear Address Valid bit
593 *
594 * @param e1000 E1000 data structure
595 * @param position RA register position
596 *
597 */
598static void e1000_disable_receive_address(e1000_t *e1000, unsigned int position)
599{
600 uint32_t rah = E1000_REG_READ(e1000, E1000_RAH_ARRAY(position));
601 rah = rah & ~RAH_AV;
602 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(position), rah);
603}
604
605/** Clear all unicast addresses from RA registers
606 *
607 * @param e1000 E1000 data structure
608 *
609 */
610static void e1000_clear_unicast_receive_addresses(e1000_t *e1000)
611{
612 for (unsigned int ra_num = 1;
613 ra_num <= e1000->unicast_ra_count;
614 ra_num++)
615 e1000_disable_receive_address(e1000, ra_num);
616
617 e1000->unicast_ra_count = 0;
618}
619
620/** Clear all multicast addresses from RA registers
621 *
622 * @param e1000 E1000 data structure
623 *
624 */
625static void e1000_clear_multicast_receive_addresses(e1000_t *e1000)
626{
627 unsigned int first_multicast_ra_num =
628 E1000_RECEIVE_ADDRESS - e1000->multicast_ra_count;
629
630 for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1;
631 ra_num >= first_multicast_ra_num;
632 ra_num--)
633 e1000_disable_receive_address(e1000, ra_num);
634
635 e1000->multicast_ra_count = 0;
636}
637
638/** Return receive address filter positions count usable for unicast
639 *
640 * @param e1000 E1000 data structure
641 *
642 * @return receive address filter positions count usable for unicast
643 *
644 */
645static unsigned int get_free_unicast_address_count(e1000_t *e1000)
646{
647 return E1000_RECEIVE_ADDRESS - 1 - e1000->multicast_ra_count;
648}
649
650/** Return receive address filter positions count usable for multicast
651 *
652 * @param e1000 E1000 data structure
653 *
654 * @return receive address filter positions count usable for multicast
655 *
656 */
657static unsigned int get_free_multicast_address_count(e1000_t *e1000)
658{
659 return E1000_RECEIVE_ADDRESS - 1 - e1000->unicast_ra_count;
660}
661
662/** Write unicast receive addresses to receive address filter registers
663 *
664 * @param e1000 E1000 data structure
665 * @param addr Pointer to address array
666 * @param addr_cnt Address array count
667 *
668 */
669static void e1000_add_unicast_receive_addresses(e1000_t *e1000,
670 const nic_address_t *addr, size_t addr_cnt)
671{
672 assert(addr_cnt <= get_free_unicast_address_count(e1000));
673
674 nic_address_t *addr_iterator = (nic_address_t *) addr;
675
676 /* ra_num = 0 is primary address */
677 for (unsigned int ra_num = 1;
678 ra_num <= addr_cnt;
679 ra_num++) {
680 e1000_write_receive_address(e1000, ra_num, addr_iterator, true);
681 addr_iterator++;
682 }
683}
684
685/** Write multicast receive addresses to receive address filter registers
686 *
687 * @param e1000 E1000 data structure
688 * @param addr Pointer to address array
689 * @param addr_cnt Address array count
690 *
691 */
692static void e1000_add_multicast_receive_addresses(e1000_t *e1000,
693 const nic_address_t *addr, size_t addr_cnt)
694{
695 assert(addr_cnt <= get_free_multicast_address_count(e1000));
696
697 nic_address_t *addr_iterator = (nic_address_t *) addr;
698
699 unsigned int first_multicast_ra_num = E1000_RECEIVE_ADDRESS - addr_cnt;
700 for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1;
701 ra_num >= first_multicast_ra_num;
702 ra_num--) {
703 e1000_write_receive_address(e1000, ra_num, addr_iterator, true);
704 addr_iterator++;
705 }
706}
707
708/** Disable receiving frames for default address
709 *
710 * @param e1000 E1000 data structure
711 *
712 */
713static void disable_ra0_address_filter(e1000_t *e1000)
714{
715 uint32_t rah0 = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
716 rah0 = rah0 & ~RAH_AV;
717 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(0), rah0);
718}
719
720/** Enable receiving frames for default address
721 *
722 * @param e1000 E1000 data structure
723 *
724 */
725static void enable_ra0_address_filter(e1000_t *e1000)
726{
727 uint32_t rah0 = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
728 rah0 = rah0 | RAH_AV;
729 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(0), rah0);
730}
731
732/** Disable unicast promiscuous mode
733 *
734 * @param e1000 E1000 data structure
735 *
736 */
737static void e1000_disable_unicast_promisc(e1000_t *e1000)
738{
739 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
740 rctl = rctl & ~RCTL_UPE;
741 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
742}
743
744/** Enable unicast promiscuous mode
745 *
746 * @param e1000 E1000 data structure
747 *
748 */
749static void e1000_enable_unicast_promisc(e1000_t *e1000)
750{
751 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
752 rctl = rctl | RCTL_UPE;
753 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
754}
755
756/** Disable multicast promiscuous mode
757 *
758 * @param e1000 E1000 data structure
759 *
760 */
761static void e1000_disable_multicast_promisc(e1000_t *e1000)
762{
763 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
764 rctl = rctl & ~RCTL_MPE;
765 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
766}
767
768/** Enable multicast promiscuous mode
769 *
770 * @param e1000 E1000 data structure
771 *
772 */
773static void e1000_enable_multicast_promisc(e1000_t *e1000)
774{
775 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
776 rctl = rctl | RCTL_MPE;
777 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
778}
779
780/** Enable accepting of broadcast frames
781 *
782 * @param e1000 E1000 data structure
783 *
784 */
785static void e1000_enable_broadcast_accept(e1000_t *e1000)
786{
787 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
788 rctl = rctl | RCTL_BAM;
789 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
790}
791
792/** Disable accepting of broadcast frames
793 *
794 * @param e1000 E1000 data structure
795 *
796 */
797static void e1000_disable_broadcast_accept(e1000_t *e1000)
798{
799 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
800 rctl = rctl & ~RCTL_BAM;
801 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
802}
803
804/** Enable VLAN filtering according to VFTA registers
805 *
806 * @param e1000 E1000 data structure
807 *
808 */
809static void e1000_enable_vlan_filter(e1000_t *e1000)
810{
811 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
812 rctl = rctl | RCTL_VFE;
813 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
814}
815
816/** Disable VLAN filtering
817 *
818 * @param e1000 E1000 data structure
819 *
820 */
821static void e1000_disable_vlan_filter(e1000_t *e1000)
822{
823 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
824 rctl = rctl & ~RCTL_VFE;
825 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
826}
827
828/** Set multicast frames acceptance mode
829 *
830 * @param nic NIC device to update
831 * @param mode Mode to set
832 * @param addr Address list (used in mode = NIC_MULTICAST_LIST)
833 * @param addr_cnt Length of address list (used in mode = NIC_MULTICAST_LIST)
834 *
835 * @return EOK
836 *
837 */
838static errno_t e1000_on_multicast_mode_change(nic_t *nic, nic_multicast_mode_t mode,
839 const nic_address_t *addr, size_t addr_cnt)
840{
841 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
842 errno_t rc = EOK;
843
844 fibril_mutex_lock(&e1000->rx_lock);
845
846 switch (mode) {
847 case NIC_MULTICAST_BLOCKED:
848 e1000_clear_multicast_receive_addresses(e1000);
849 e1000_disable_multicast_promisc(e1000);
850 nic_report_hw_filtering(nic, -1, 1, -1);
851 break;
852 case NIC_MULTICAST_LIST:
853 e1000_clear_multicast_receive_addresses(e1000);
854 if (addr_cnt > get_free_multicast_address_count(e1000)) {
855 /*
856 * Future work: fill MTA table
857 * Not strictly neccessary, it only saves some compares
858 * in the NIC library.
859 */
860 e1000_enable_multicast_promisc(e1000);
861 nic_report_hw_filtering(nic, -1, 0, -1);
862 } else {
863 e1000_disable_multicast_promisc(e1000);
864 e1000_add_multicast_receive_addresses(e1000, addr, addr_cnt);
865 nic_report_hw_filtering(nic, -1, 1, -1);
866 }
867 break;
868 case NIC_MULTICAST_PROMISC:
869 e1000_enable_multicast_promisc(e1000);
870 e1000_clear_multicast_receive_addresses(e1000);
871 nic_report_hw_filtering(nic, -1, 1, -1);
872 break;
873 default:
874 rc = ENOTSUP;
875 break;
876 }
877
878 fibril_mutex_unlock(&e1000->rx_lock);
879 return rc;
880}
881
882/** Set unicast frames acceptance mode
883 *
884 * @param nic NIC device to update
885 * @param mode Mode to set
886 * @param addr Address list (used in mode = NIC_MULTICAST_LIST)
887 * @param addr_cnt Length of address list (used in mode = NIC_MULTICAST_LIST)
888 *
889 * @return EOK
890 *
891 */
892static errno_t e1000_on_unicast_mode_change(nic_t *nic, nic_unicast_mode_t mode,
893 const nic_address_t *addr, size_t addr_cnt)
894{
895 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
896 errno_t rc = EOK;
897
898 fibril_mutex_lock(&e1000->rx_lock);
899
900 switch (mode) {
901 case NIC_UNICAST_BLOCKED:
902 disable_ra0_address_filter(e1000);
903 e1000_clear_unicast_receive_addresses(e1000);
904 e1000_disable_unicast_promisc(e1000);
905 nic_report_hw_filtering(nic, 1, -1, -1);
906 break;
907 case NIC_UNICAST_DEFAULT:
908 enable_ra0_address_filter(e1000);
909 e1000_clear_unicast_receive_addresses(e1000);
910 e1000_disable_unicast_promisc(e1000);
911 nic_report_hw_filtering(nic, 1, -1, -1);
912 break;
913 case NIC_UNICAST_LIST:
914 enable_ra0_address_filter(e1000);
915 e1000_clear_unicast_receive_addresses(e1000);
916 if (addr_cnt > get_free_unicast_address_count(e1000)) {
917 e1000_enable_unicast_promisc(e1000);
918 nic_report_hw_filtering(nic, 0, -1, -1);
919 } else {
920 e1000_disable_unicast_promisc(e1000);
921 e1000_add_unicast_receive_addresses(e1000, addr, addr_cnt);
922 nic_report_hw_filtering(nic, 1, -1, -1);
923 }
924 break;
925 case NIC_UNICAST_PROMISC:
926 e1000_enable_unicast_promisc(e1000);
927 enable_ra0_address_filter(e1000);
928 e1000_clear_unicast_receive_addresses(e1000);
929 nic_report_hw_filtering(nic, 1, -1, -1);
930 break;
931 default:
932 rc = ENOTSUP;
933 break;
934 }
935
936 fibril_mutex_unlock(&e1000->rx_lock);
937 return rc;
938}
939
940/** Set broadcast frames acceptance mode
941 *
942 * @param nic NIC device to update
943 * @param mode Mode to set
944 *
945 * @return EOK
946 *
947 */
948static errno_t e1000_on_broadcast_mode_change(nic_t *nic, nic_broadcast_mode_t mode)
949{
950 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
951 errno_t rc = EOK;
952
953 fibril_mutex_lock(&e1000->rx_lock);
954
955 switch (mode) {
956 case NIC_BROADCAST_BLOCKED:
957 e1000_disable_broadcast_accept(e1000);
958 break;
959 case NIC_BROADCAST_ACCEPTED:
960 e1000_enable_broadcast_accept(e1000);
961 break;
962 default:
963 rc = ENOTSUP;
964 break;
965 }
966
967 fibril_mutex_unlock(&e1000->rx_lock);
968 return rc;
969}
970
971/** Check if receiving is enabled
972 *
973 * @param e1000 E1000 data structure
974 *
975 * @return true if receiving is enabled
976 *
977 */
978static bool e1000_is_rx_enabled(e1000_t *e1000)
979{
980 if (E1000_REG_READ(e1000, E1000_RCTL) & (RCTL_EN))
981 return true;
982
983 return false;
984}
985
986/** Enable receiving
987 *
988 * @param e1000 E1000 data structure
989 *
990 */
991static void e1000_enable_rx(e1000_t *e1000)
992{
993 /* Set Receive Enable Bit */
994 E1000_REG_WRITE(e1000, E1000_RCTL,
995 E1000_REG_READ(e1000, E1000_RCTL) | (RCTL_EN));
996}
997
998/** Disable receiving
999 *
1000 * @param e1000 E1000 data structure
1001 *
1002 */
1003static void e1000_disable_rx(e1000_t *e1000)
1004{
1005 /* Clear Receive Enable Bit */
1006 E1000_REG_WRITE(e1000, E1000_RCTL,
1007 E1000_REG_READ(e1000, E1000_RCTL) & ~(RCTL_EN));
1008}
1009
1010/** Set VLAN mask
1011 *
1012 * @param nic NIC device to update
1013 * @param vlan_mask VLAN mask
1014 *
1015 */
1016static void e1000_on_vlan_mask_change(nic_t *nic,
1017 const nic_vlan_mask_t *vlan_mask)
1018{
1019 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1020
1021 fibril_mutex_lock(&e1000->rx_lock);
1022
1023 if (vlan_mask) {
1024 /*
1025 * Disable receiving, so that frame matching
1026 * partially written VLAN is not received.
1027 */
1028 bool rx_enabled = e1000_is_rx_enabled(e1000);
1029 if (rx_enabled)
1030 e1000_disable_rx(e1000);
1031
1032 for (unsigned int i = 0; i < NIC_VLAN_BITMAP_SIZE; i += 4) {
1033 uint32_t bitmap_part =
1034 ((uint32_t) vlan_mask->bitmap[i]) |
1035 (((uint32_t) vlan_mask->bitmap[i + 1]) << 8) |
1036 (((uint32_t) vlan_mask->bitmap[i + 2]) << 16) |
1037 (((uint32_t) vlan_mask->bitmap[i + 3]) << 24);
1038 E1000_REG_WRITE(e1000, E1000_VFTA_ARRAY(i / 4), bitmap_part);
1039 }
1040
1041 e1000_enable_vlan_filter(e1000);
1042 if (rx_enabled)
1043 e1000_enable_rx(e1000);
1044 } else
1045 e1000_disable_vlan_filter(e1000);
1046
1047 fibril_mutex_unlock(&e1000->rx_lock);
1048}
1049
1050/** Set VLAN mask
1051 *
1052 * @param device E1000 device
1053 * @param tag VLAN tag
1054 *
1055 * @return EOK
1056 * @return ENOTSUP
1057 *
1058 */
1059static errno_t e1000_vlan_set_tag(ddf_fun_t *fun, uint16_t tag, bool add,
1060 bool strip)
1061{
1062 /* VLAN CFI bit cannot be set */
1063 if (tag & VLANTAG_CFI)
1064 return ENOTSUP;
1065
1066 /*
1067 * CTRL.VME is neccessary for both strip and add
1068 * but CTRL.VME means stripping tags on receive.
1069 */
1070 if (!strip && add)
1071 return ENOTSUP;
1072
1073 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
1074
1075 e1000->vlan_tag = tag;
1076 e1000->vlan_tag_add = add;
1077
1078 fibril_mutex_lock(&e1000->ctrl_lock);
1079
1080 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1081 if (strip)
1082 ctrl |= CTRL_VME;
1083 else
1084 ctrl &= ~CTRL_VME;
1085
1086 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1087
1088 fibril_mutex_unlock(&e1000->ctrl_lock);
1089 return EOK;
1090}
1091
1092/** Fill receive descriptor with new empty buffer
1093 *
1094 * Store frame in e1000->rx_frame_phys
1095 *
1096 * @param nic NIC data stricture
1097 * @param offset Receive descriptor offset
1098 *
1099 */
1100static void e1000_fill_new_rx_descriptor(nic_t *nic, size_t offset)
1101{
1102 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1103
1104 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1105 (e1000->rx_ring_virt + offset * sizeof(e1000_rx_descriptor_t));
1106
1107 rx_descriptor->phys_addr = PTR_TO_U64(e1000->rx_frame_phys[offset]);
1108 rx_descriptor->length = 0;
1109 rx_descriptor->checksum = 0;
1110 rx_descriptor->status = 0;
1111 rx_descriptor->errors = 0;
1112 rx_descriptor->special = 0;
1113}
1114
1115/** Clear receive descriptor
1116 *
1117 * @param e1000 E1000 data
1118 * @param offset Receive descriptor offset
1119 *
1120 */
1121static void e1000_clear_rx_descriptor(e1000_t *e1000, unsigned int offset)
1122{
1123 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1124 (e1000->rx_ring_virt + offset * sizeof(e1000_rx_descriptor_t));
1125
1126 rx_descriptor->length = 0;
1127 rx_descriptor->checksum = 0;
1128 rx_descriptor->status = 0;
1129 rx_descriptor->errors = 0;
1130 rx_descriptor->special = 0;
1131}
1132
1133/** Clear receive descriptor
1134 *
1135 * @param nic NIC data
1136 * @param offset Receive descriptor offset
1137 *
1138 */
1139static void e1000_clear_tx_descriptor(nic_t *nic, unsigned int offset)
1140{
1141 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1142
1143 e1000_tx_descriptor_t *tx_descriptor = (e1000_tx_descriptor_t *)
1144 (e1000->tx_ring_virt + offset * sizeof(e1000_tx_descriptor_t));
1145
1146 tx_descriptor->phys_addr = 0;
1147 tx_descriptor->length = 0;
1148 tx_descriptor->checksum_offset = 0;
1149 tx_descriptor->command = 0;
1150 tx_descriptor->status = 0;
1151 tx_descriptor->checksum_start_field = 0;
1152 tx_descriptor->special = 0;
1153}
1154
1155/** Increment tail pointer for receive or transmit ring
1156 *
1157 * @param tail Old Tail
1158 * @param descriptors_count Ring length
1159 *
1160 * @return New tail
1161 *
1162 */
1163static uint32_t e1000_inc_tail(uint32_t tail, uint32_t descriptors_count)
1164{
1165 if (tail + 1 == descriptors_count)
1166 return 0;
1167 else
1168 return tail + 1;
1169}
1170
1171/** Receive frames
1172 *
1173 * @param nic NIC data
1174 *
1175 */
1176static void e1000_receive_frames(nic_t *nic)
1177{
1178 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1179
1180 fibril_mutex_lock(&e1000->rx_lock);
1181
1182 uint32_t *tail_addr = E1000_REG_ADDR(e1000, E1000_RDT);
1183 uint32_t next_tail = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1184
1185 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1186 (e1000->rx_ring_virt + next_tail * sizeof(e1000_rx_descriptor_t));
1187
1188 while (rx_descriptor->status & 0x01) {
1189 uint32_t frame_size = rx_descriptor->length - E1000_CRC_SIZE;
1190
1191 nic_frame_t *frame = nic_alloc_frame(nic, frame_size);
1192 if (frame != NULL) {
1193 memcpy(frame->data, e1000->rx_frame_virt[next_tail], frame_size);
1194 pcapdump_packet(nic_get_pcap_iface(nic), frame->data, frame->size);
1195
1196 nic_received_frame(nic, frame);
1197 } else {
1198 ddf_msg(LVL_ERROR, "Memory allocation failed. Frame dropped.");
1199 }
1200
1201 e1000_fill_new_rx_descriptor(nic, next_tail);
1202
1203 *tail_addr = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1204 next_tail = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1205
1206 rx_descriptor = (e1000_rx_descriptor_t *)
1207 (e1000->rx_ring_virt + next_tail * sizeof(e1000_rx_descriptor_t));
1208 }
1209
1210 fibril_mutex_unlock(&e1000->rx_lock);
1211}
1212
1213/** Enable E1000 interupts
1214 *
1215 * @param e1000 E1000 data structure
1216 *
1217 */
1218static void e1000_enable_interrupts(e1000_t *e1000)
1219{
1220 E1000_REG_WRITE(e1000, E1000_IMS, ICR_RXT0);
1221}
1222
1223/** Disable E1000 interupts
1224 *
1225 * @param e1000 E1000 data structure
1226 *
1227 */
1228static void e1000_disable_interrupts(e1000_t *e1000)
1229{
1230 E1000_REG_WRITE(e1000, E1000_IMS, 0);
1231}
1232
1233/** Interrupt handler implementation
1234 *
1235 * This function is called from e1000_interrupt_handler()
1236 * and e1000_poll()
1237 *
1238 * @param nic NIC data
1239 * @param icr ICR register value
1240 *
1241 */
1242static void e1000_interrupt_handler_impl(nic_t *nic, uint32_t icr)
1243{
1244 if (icr & ICR_RXT0)
1245 e1000_receive_frames(nic);
1246}
1247
1248/** Handle device interrupt
1249 *
1250 * @param icall IPC call structure
1251 * @param arg Argument (nic_t *)
1252 *
1253 */
1254static void e1000_interrupt_handler(ipc_call_t *icall, void *arg)
1255{
1256 uint32_t icr = (uint32_t) ipc_get_arg2(icall);
1257 nic_t *nic = (nic_t *)arg;
1258 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1259
1260 e1000_interrupt_handler_impl(nic, icr);
1261 e1000_enable_interrupts(e1000);
1262}
1263
1264/** Register interrupt handler for the card in the system
1265 *
1266 * Note: The global irq_reg_mutex is locked because of work with global
1267 * structure.
1268 *
1269 * @param nic Driver data
1270 *
1271 * @param[out] handle IRQ capability handle if the handler was registered
1272 *
1273 * @return An error code otherwise
1274 *
1275 */
1276inline static errno_t e1000_register_int_handler(nic_t *nic,
1277 cap_irq_handle_t *handle)
1278{
1279 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1280
1281 /* Lock the mutex in whole driver while working with global structure */
1282 fibril_mutex_lock(&irq_reg_mutex);
1283
1284 e1000_irq_code.ranges[0].base = (uintptr_t) e1000->reg_base_phys;
1285 e1000_irq_code.cmds[0].addr = e1000->reg_base_phys + E1000_ICR;
1286 e1000_irq_code.cmds[3].addr = e1000->reg_base_phys + E1000_IMC;
1287
1288 errno_t rc = register_interrupt_handler(nic_get_ddf_dev(nic), e1000->irq,
1289 e1000_interrupt_handler, (void *)nic, &e1000_irq_code, handle);
1290
1291 fibril_mutex_unlock(&irq_reg_mutex);
1292 return rc;
1293}
1294
1295/** Force receiving all frames in the receive buffer
1296 *
1297 * @param nic NIC data
1298 *
1299 */
1300static void e1000_poll(nic_t *nic)
1301{
1302 assert(nic);
1303
1304 e1000_t *e1000 = nic_get_specific(nic);
1305 assert(e1000);
1306
1307 uint32_t icr = E1000_REG_READ(e1000, E1000_ICR);
1308 e1000_interrupt_handler_impl(nic, icr);
1309}
1310
1311/** Calculates ITR register interrupt from timespec structure
1312 *
1313 * @param period Period
1314 *
1315 */
1316static uint16_t e1000_calculate_itr_interval(const struct timespec *period)
1317{
1318 // TODO: use also tv_sec
1319 return e1000_calculate_itr_interval_from_usecs(NSEC2USEC(period->tv_nsec));
1320}
1321
1322/** Set polling mode
1323 *
1324 * @param device Device to set
1325 * @param mode Mode to set
1326 * @param period Period for NIC_POLL_PERIODIC
1327 *
1328 * @return EOK if succeed
1329 * @return ENOTSUP if the mode is not supported
1330 *
1331 */
1332static errno_t e1000_poll_mode_change(nic_t *nic, nic_poll_mode_t mode,
1333 const struct timespec *period)
1334{
1335 assert(nic);
1336
1337 e1000_t *e1000 = nic_get_specific(nic);
1338 assert(e1000);
1339
1340 switch (mode) {
1341 case NIC_POLL_IMMEDIATE:
1342 E1000_REG_WRITE(e1000, E1000_ITR, 0);
1343 e1000_enable_interrupts(e1000);
1344 break;
1345 case NIC_POLL_ON_DEMAND:
1346 e1000_disable_interrupts(e1000);
1347 break;
1348 case NIC_POLL_PERIODIC:
1349 assert(period);
1350 uint16_t itr_interval = e1000_calculate_itr_interval(period);
1351 E1000_REG_WRITE(e1000, E1000_ITR, (uint32_t) itr_interval);
1352 e1000_enable_interrupts(e1000);
1353 break;
1354 default:
1355 return ENOTSUP;
1356 }
1357
1358 return EOK;
1359}
1360
1361/** Initialize receive registers
1362 *
1363 * @param e1000 E1000 data structure
1364 *
1365 */
1366static void e1000_initialize_rx_registers(e1000_t *e1000)
1367{
1368 E1000_REG_WRITE(e1000, E1000_RDLEN, E1000_RX_FRAME_COUNT * 16);
1369 E1000_REG_WRITE(e1000, E1000_RDH, 0);
1370
1371 /* It is not posible to let HW use all descriptors */
1372 E1000_REG_WRITE(e1000, E1000_RDT, E1000_RX_FRAME_COUNT - 1);
1373
1374 /* Set Broadcast Enable Bit */
1375 E1000_REG_WRITE(e1000, E1000_RCTL, RCTL_BAM);
1376}
1377
1378/** Initialize receive structure
1379 *
1380 * @param nic NIC data
1381 *
1382 * @return EOK if succeed
1383 * @return An error code otherwise
1384 *
1385 */
1386static errno_t e1000_initialize_rx_structure(nic_t *nic)
1387{
1388 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1389 fibril_mutex_lock(&e1000->rx_lock);
1390
1391 e1000->rx_ring_virt = AS_AREA_ANY;
1392 errno_t rc = dmamem_map_anonymous(
1393 E1000_RX_FRAME_COUNT * sizeof(e1000_rx_descriptor_t),
1394 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0,
1395 &e1000->rx_ring_phys, &e1000->rx_ring_virt);
1396 if (rc != EOK)
1397 return rc;
1398
1399 E1000_REG_WRITE(e1000, E1000_RDBAH,
1400 (uint32_t) (PTR_TO_U64(e1000->rx_ring_phys) >> 32));
1401 E1000_REG_WRITE(e1000, E1000_RDBAL,
1402 (uint32_t) PTR_TO_U64(e1000->rx_ring_phys));
1403
1404 e1000->rx_frame_phys = (uintptr_t *)
1405 calloc(E1000_RX_FRAME_COUNT, sizeof(uintptr_t));
1406 e1000->rx_frame_virt =
1407 calloc(E1000_RX_FRAME_COUNT, sizeof(void *));
1408 if ((e1000->rx_frame_phys == NULL) || (e1000->rx_frame_virt == NULL)) {
1409 rc = ENOMEM;
1410 goto error;
1411 }
1412
1413 for (size_t i = 0; i < E1000_RX_FRAME_COUNT; i++) {
1414 uintptr_t frame_phys;
1415 void *frame_virt = AS_AREA_ANY;
1416
1417 rc = dmamem_map_anonymous(E1000_MAX_SEND_FRAME_SIZE,
1418 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0,
1419 &frame_phys, &frame_virt);
1420 if (rc != EOK)
1421 goto error;
1422
1423 e1000->rx_frame_phys[i] = frame_phys;
1424 e1000->rx_frame_virt[i] = frame_virt;
1425 }
1426
1427 /* Write descriptor */
1428 for (size_t i = 0; i < E1000_RX_FRAME_COUNT; i++)
1429 e1000_fill_new_rx_descriptor(nic, i);
1430
1431 e1000_initialize_rx_registers(e1000);
1432
1433 fibril_mutex_unlock(&e1000->rx_lock);
1434 return EOK;
1435
1436error:
1437 for (size_t i = 0; i < E1000_RX_FRAME_COUNT; i++) {
1438 if (e1000->rx_frame_virt[i] != NULL) {
1439 dmamem_unmap_anonymous(e1000->rx_frame_virt[i]);
1440 e1000->rx_frame_phys[i] = 0;
1441 e1000->rx_frame_virt[i] = NULL;
1442 }
1443 }
1444
1445 if (e1000->rx_frame_phys != NULL) {
1446 free(e1000->rx_frame_phys);
1447 e1000->rx_frame_phys = NULL;
1448 }
1449
1450 if (e1000->rx_frame_virt != NULL) {
1451 free(e1000->rx_frame_virt);
1452 e1000->rx_frame_virt = NULL;
1453 }
1454
1455 return rc;
1456}
1457
1458/** Uninitialize receive structure
1459 *
1460 * @param nic NIC data
1461 *
1462 */
1463static void e1000_uninitialize_rx_structure(nic_t *nic)
1464{
1465 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1466
1467 /* Write descriptor */
1468 for (unsigned int offset = 0; offset < E1000_RX_FRAME_COUNT; offset++) {
1469 dmamem_unmap_anonymous(e1000->rx_frame_virt[offset]);
1470 e1000->rx_frame_phys[offset] = 0;
1471 e1000->rx_frame_virt[offset] = NULL;
1472 }
1473
1474 free(e1000->rx_frame_virt);
1475
1476 e1000->rx_frame_phys = NULL;
1477 e1000->rx_frame_virt = NULL;
1478
1479 dmamem_unmap_anonymous(e1000->rx_ring_virt);
1480}
1481
1482/** Clear receive descriptor ring
1483 *
1484 * @param e1000 E1000 data
1485 *
1486 */
1487static void e1000_clear_rx_ring(e1000_t *e1000)
1488{
1489 /* Write descriptor */
1490 for (unsigned int offset = 0;
1491 offset < E1000_RX_FRAME_COUNT;
1492 offset++)
1493 e1000_clear_rx_descriptor(e1000, offset);
1494}
1495
1496/** Initialize filters
1497 *
1498 * @param e1000 E1000 data
1499 *
1500 */
1501static void e1000_initialize_filters(e1000_t *e1000)
1502{
1503 /* Initialize address filter */
1504 e1000->unicast_ra_count = 0;
1505 e1000->multicast_ra_count = 0;
1506 e1000_clear_unicast_receive_addresses(e1000);
1507}
1508
1509/** Initialize VLAN
1510 *
1511 * @param e1000 E1000 data
1512 *
1513 */
1514static void e1000_initialize_vlan(e1000_t *e1000)
1515{
1516 e1000->vlan_tag_add = false;
1517}
1518
1519/** Fill MAC address from EEPROM to RA[0] register
1520 *
1521 * @param e1000 E1000 data
1522 *
1523 */
1524static void e1000_fill_mac_from_eeprom(e1000_t *e1000)
1525{
1526 /* MAC address from eeprom to RA[0] */
1527 nic_address_t address;
1528 e1000_eeprom_get_address(e1000, &address);
1529 e1000_write_receive_address(e1000, 0, &address, true);
1530}
1531
1532/** Initialize other registers
1533 *
1534 * @param dev E1000 data.
1535 *
1536 * @return EOK if succeed
1537 * @return An error code otherwise
1538 *
1539 */
1540static void e1000_initialize_registers(e1000_t *e1000)
1541{
1542 E1000_REG_WRITE(e1000, E1000_ITR,
1543 e1000_calculate_itr_interval_from_usecs(
1544 E1000_DEFAULT_INTERRUPT_INTERVAL_USEC));
1545 E1000_REG_WRITE(e1000, E1000_FCAH, 0);
1546 E1000_REG_WRITE(e1000, E1000_FCAL, 0);
1547 E1000_REG_WRITE(e1000, E1000_FCT, 0);
1548 E1000_REG_WRITE(e1000, E1000_FCTTV, 0);
1549 E1000_REG_WRITE(e1000, E1000_VET, VET_VALUE);
1550 E1000_REG_WRITE(e1000, E1000_CTRL, CTRL_ASDE);
1551}
1552
1553/** Initialize transmit registers
1554 *
1555 * @param e1000 E1000 data.
1556 *
1557 */
1558static void e1000_initialize_tx_registers(e1000_t *e1000)
1559{
1560 E1000_REG_WRITE(e1000, E1000_TDLEN, E1000_TX_FRAME_COUNT * 16);
1561 E1000_REG_WRITE(e1000, E1000_TDH, 0);
1562 E1000_REG_WRITE(e1000, E1000_TDT, 0);
1563
1564 E1000_REG_WRITE(e1000, E1000_TIPG,
1565 10 << TIPG_IPGT_SHIFT |
1566 8 << TIPG_IPGR1_SHIFT |
1567 6 << TIPG_IPGR2_SHIFT);
1568
1569 E1000_REG_WRITE(e1000, E1000_TCTL,
1570 0x0F << TCTL_CT_SHIFT /* Collision Threshold */ |
1571 0x40 << TCTL_COLD_SHIFT /* Collision Distance */ |
1572 TCTL_PSP /* Pad Short Packets */);
1573}
1574
1575/** Initialize transmit structure
1576 *
1577 * @param e1000 E1000 data.
1578 *
1579 */
1580static errno_t e1000_initialize_tx_structure(e1000_t *e1000)
1581{
1582 size_t i;
1583
1584 fibril_mutex_lock(&e1000->tx_lock);
1585
1586 e1000->tx_ring_phys = 0;
1587 e1000->tx_ring_virt = AS_AREA_ANY;
1588
1589 e1000->tx_frame_phys = NULL;
1590 e1000->tx_frame_virt = NULL;
1591
1592 errno_t rc = dmamem_map_anonymous(
1593 E1000_TX_FRAME_COUNT * sizeof(e1000_tx_descriptor_t),
1594 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0,
1595 &e1000->tx_ring_phys, &e1000->tx_ring_virt);
1596 if (rc != EOK)
1597 goto error;
1598
1599 memset(e1000->tx_ring_virt, 0,
1600 E1000_TX_FRAME_COUNT * sizeof(e1000_tx_descriptor_t));
1601
1602 e1000->tx_frame_phys = (uintptr_t *)
1603 calloc(E1000_TX_FRAME_COUNT, sizeof(uintptr_t));
1604 e1000->tx_frame_virt =
1605 calloc(E1000_TX_FRAME_COUNT, sizeof(void *));
1606
1607 if ((e1000->tx_frame_phys == NULL) || (e1000->tx_frame_virt == NULL)) {
1608 rc = ENOMEM;
1609 goto error;
1610 }
1611
1612 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1613 e1000->tx_frame_virt[i] = AS_AREA_ANY;
1614 rc = dmamem_map_anonymous(E1000_MAX_SEND_FRAME_SIZE,
1615 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE,
1616 0, &e1000->tx_frame_phys[i], &e1000->tx_frame_virt[i]);
1617 if (rc != EOK)
1618 goto error;
1619 }
1620
1621 E1000_REG_WRITE(e1000, E1000_TDBAH,
1622 (uint32_t) (PTR_TO_U64(e1000->tx_ring_phys) >> 32));
1623 E1000_REG_WRITE(e1000, E1000_TDBAL,
1624 (uint32_t) PTR_TO_U64(e1000->tx_ring_phys));
1625
1626 e1000_initialize_tx_registers(e1000);
1627
1628 fibril_mutex_unlock(&e1000->tx_lock);
1629 return EOK;
1630
1631error:
1632 if (e1000->tx_ring_virt != NULL) {
1633 dmamem_unmap_anonymous(e1000->tx_ring_virt);
1634 e1000->tx_ring_virt = NULL;
1635 }
1636
1637 if ((e1000->tx_frame_phys != NULL) && (e1000->tx_frame_virt != NULL)) {
1638 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1639 if (e1000->tx_frame_virt[i] != NULL) {
1640 dmamem_unmap_anonymous(e1000->tx_frame_virt[i]);
1641 e1000->tx_frame_phys[i] = 0;
1642 e1000->tx_frame_virt[i] = NULL;
1643 }
1644 }
1645 }
1646
1647 if (e1000->tx_frame_phys != NULL) {
1648 free(e1000->tx_frame_phys);
1649 e1000->tx_frame_phys = NULL;
1650 }
1651
1652 if (e1000->tx_frame_virt != NULL) {
1653 free(e1000->tx_frame_virt);
1654 e1000->tx_frame_virt = NULL;
1655 }
1656
1657 return rc;
1658}
1659
1660/** Uninitialize transmit structure
1661 *
1662 * @param nic NIC data
1663 *
1664 */
1665static void e1000_uninitialize_tx_structure(e1000_t *e1000)
1666{
1667 size_t i;
1668
1669 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1670 dmamem_unmap_anonymous(e1000->tx_frame_virt[i]);
1671 e1000->tx_frame_phys[i] = 0;
1672 e1000->tx_frame_virt[i] = NULL;
1673 }
1674
1675 if (e1000->tx_frame_phys != NULL) {
1676 free(e1000->tx_frame_phys);
1677 e1000->tx_frame_phys = NULL;
1678 }
1679
1680 if (e1000->tx_frame_virt != NULL) {
1681 free(e1000->tx_frame_virt);
1682 e1000->tx_frame_virt = NULL;
1683 }
1684
1685 dmamem_unmap_anonymous(e1000->tx_ring_virt);
1686}
1687
1688/** Clear transmit descriptor ring
1689 *
1690 * @param nic NIC data
1691 *
1692 */
1693static void e1000_clear_tx_ring(nic_t *nic)
1694{
1695 /* Write descriptor */
1696 for (unsigned int offset = 0;
1697 offset < E1000_TX_FRAME_COUNT;
1698 offset++)
1699 e1000_clear_tx_descriptor(nic, offset);
1700}
1701
1702/** Enable transmit
1703 *
1704 * @param e1000 E1000 data
1705 *
1706 */
1707static void e1000_enable_tx(e1000_t *e1000)
1708{
1709 /* Set Transmit Enable Bit */
1710 E1000_REG_WRITE(e1000, E1000_TCTL,
1711 E1000_REG_READ(e1000, E1000_TCTL) | (TCTL_EN));
1712}
1713
1714/** Disable transmit
1715 *
1716 * @param e1000 E1000 data
1717 *
1718 */
1719static void e1000_disable_tx(e1000_t *e1000)
1720{
1721 /* Clear Transmit Enable Bit */
1722 E1000_REG_WRITE(e1000, E1000_TCTL,
1723 E1000_REG_READ(e1000, E1000_TCTL) & ~(TCTL_EN));
1724}
1725
1726/** Reset E1000 device
1727 *
1728 * @param e1000 The E1000 data
1729 *
1730 */
1731static errno_t e1000_reset(nic_t *nic)
1732{
1733 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1734
1735 E1000_REG_WRITE(e1000, E1000_CTRL, CTRL_RST);
1736
1737 /* Wait for the reset */
1738 fibril_usleep(20);
1739
1740 /* check if RST_BIT cleared */
1741 if (E1000_REG_READ(e1000, E1000_CTRL) & (CTRL_RST))
1742 return EINVAL;
1743
1744 e1000_initialize_registers(e1000);
1745 e1000_initialize_rx_registers(e1000);
1746 e1000_initialize_tx_registers(e1000);
1747 e1000_fill_mac_from_eeprom(e1000);
1748 e1000_initialize_filters(e1000);
1749 e1000_initialize_vlan(e1000);
1750
1751 return EOK;
1752}
1753
1754/** Activate the device to receive and transmit frames
1755 *
1756 * @param nic NIC driver data
1757 *
1758 * @return EOK if activated successfully
1759 * @return Error code otherwise
1760 *
1761 */
1762static errno_t e1000_on_activating(nic_t *nic)
1763{
1764 assert(nic);
1765
1766 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1767
1768 fibril_mutex_lock(&e1000->rx_lock);
1769 fibril_mutex_lock(&e1000->tx_lock);
1770 fibril_mutex_lock(&e1000->ctrl_lock);
1771
1772 e1000_enable_interrupts(e1000);
1773
1774 errno_t rc = hw_res_enable_interrupt(e1000->parent_sess, e1000->irq);
1775 if (rc != EOK) {
1776 e1000_disable_interrupts(e1000);
1777 fibril_mutex_unlock(&e1000->ctrl_lock);
1778 fibril_mutex_unlock(&e1000->tx_lock);
1779 fibril_mutex_unlock(&e1000->rx_lock);
1780 return rc;
1781 }
1782
1783 e1000_clear_rx_ring(e1000);
1784 e1000_enable_rx(e1000);
1785
1786 e1000_clear_tx_ring(nic);
1787 e1000_enable_tx(e1000);
1788
1789 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1790 ctrl |= CTRL_SLU;
1791 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1792
1793 fibril_mutex_unlock(&e1000->ctrl_lock);
1794 fibril_mutex_unlock(&e1000->tx_lock);
1795 fibril_mutex_unlock(&e1000->rx_lock);
1796
1797 return EOK;
1798}
1799
1800/** Callback for NIC_STATE_DOWN change
1801 *
1802 * @param nic NIC driver data
1803 *
1804 * @return EOK if succeed
1805 * @return Error code otherwise
1806 *
1807 */
1808static errno_t e1000_on_down_unlocked(nic_t *nic)
1809{
1810 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1811
1812 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1813 ctrl &= ~CTRL_SLU;
1814 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1815
1816 e1000_disable_tx(e1000);
1817 e1000_disable_rx(e1000);
1818
1819 hw_res_disable_interrupt(e1000->parent_sess, e1000->irq);
1820 e1000_disable_interrupts(e1000);
1821
1822 /*
1823 * Wait for the for the end of all data
1824 * transfers to descriptors.
1825 */
1826 fibril_usleep(100);
1827
1828 return EOK;
1829}
1830
1831/** Callback for NIC_STATE_DOWN change
1832 *
1833 * @param nic NIC driver data
1834 *
1835 * @return EOK if succeed
1836 * @return Error code otherwise
1837 *
1838 */
1839static errno_t e1000_on_down(nic_t *nic)
1840{
1841 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1842
1843 fibril_mutex_lock(&e1000->rx_lock);
1844 fibril_mutex_lock(&e1000->tx_lock);
1845 fibril_mutex_lock(&e1000->ctrl_lock);
1846
1847 errno_t rc = e1000_on_down_unlocked(nic);
1848
1849 fibril_mutex_unlock(&e1000->ctrl_lock);
1850 fibril_mutex_unlock(&e1000->tx_lock);
1851 fibril_mutex_unlock(&e1000->rx_lock);
1852
1853 return rc;
1854}
1855
1856/** Callback for NIC_STATE_STOPPED change
1857 *
1858 * @param nic NIC driver data
1859 *
1860 * @return EOK if succeed
1861 * @return Error code otherwise
1862 *
1863 */
1864static errno_t e1000_on_stopping(nic_t *nic)
1865{
1866 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1867
1868 fibril_mutex_lock(&e1000->rx_lock);
1869 fibril_mutex_lock(&e1000->tx_lock);
1870 fibril_mutex_lock(&e1000->ctrl_lock);
1871
1872 errno_t rc = e1000_on_down_unlocked(nic);
1873 if (rc == EOK)
1874 rc = e1000_reset(nic);
1875
1876 fibril_mutex_unlock(&e1000->ctrl_lock);
1877 fibril_mutex_unlock(&e1000->tx_lock);
1878 fibril_mutex_unlock(&e1000->rx_lock);
1879
1880 return rc;
1881}
1882
1883/** Create driver data structure
1884 *
1885 * @return Intialized device data structure or NULL
1886 *
1887 */
1888static e1000_t *e1000_create_dev_data(ddf_dev_t *dev)
1889{
1890 nic_t *nic = nic_create_and_bind(dev);
1891 if (!nic)
1892 return NULL;
1893
1894 e1000_t *e1000 = malloc(sizeof(e1000_t));
1895 if (!e1000) {
1896 nic_unbind_and_destroy(dev);
1897 return NULL;
1898 }
1899
1900 memset(e1000, 0, sizeof(e1000_t));
1901 e1000->dev = dev;
1902
1903 nic_set_specific(nic, e1000);
1904 nic_set_send_frame_handler(nic, e1000_send_frame);
1905 nic_set_state_change_handlers(nic, e1000_on_activating,
1906 e1000_on_down, e1000_on_stopping);
1907 nic_set_filtering_change_handlers(nic,
1908 e1000_on_unicast_mode_change, e1000_on_multicast_mode_change,
1909 e1000_on_broadcast_mode_change, NULL, e1000_on_vlan_mask_change);
1910 nic_set_poll_handlers(nic, e1000_poll_mode_change, e1000_poll);
1911
1912 fibril_mutex_initialize(&e1000->ctrl_lock);
1913 fibril_mutex_initialize(&e1000->rx_lock);
1914 fibril_mutex_initialize(&e1000->tx_lock);
1915 fibril_mutex_initialize(&e1000->eeprom_lock);
1916
1917 return e1000;
1918}
1919
1920/** Delete driver data structure
1921 *
1922 * @param data E1000 device data structure
1923 *
1924 */
1925inline static void e1000_delete_dev_data(ddf_dev_t *dev)
1926{
1927 assert(dev);
1928
1929 if (ddf_dev_data_get(dev) != NULL)
1930 nic_unbind_and_destroy(dev);
1931}
1932
1933/** Clean up the E1000 device structure.
1934 *
1935 * @param dev Device structure.
1936 *
1937 */
1938static void e1000_dev_cleanup(ddf_dev_t *dev)
1939{
1940 assert(dev);
1941
1942 e1000_delete_dev_data(dev);
1943}
1944
1945/** Fill the irq and io_addr part of device data structure
1946 *
1947 * The hw_resources must be obtained before calling this function
1948 *
1949 * @param dev Device structure
1950 * @param hw_resources Hardware resources obtained from the parent device
1951 *
1952 * @return EOK if succeed
1953 * @return An error code otherwise
1954 *
1955 */
1956static errno_t e1000_fill_resource_info(ddf_dev_t *dev,
1957 const hw_res_list_parsed_t *hw_resources)
1958{
1959 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
1960
1961 if (hw_resources->irqs.count != 1)
1962 return EINVAL;
1963
1964 e1000->irq = hw_resources->irqs.irqs[0];
1965 e1000->reg_base_phys =
1966 MEMADDR_TO_PTR(RNGABS(hw_resources->mem_ranges.ranges[0]));
1967
1968 return EOK;
1969}
1970
1971/** Obtain information about hardware resources of the device
1972 *
1973 * The device must be connected to the parent
1974 *
1975 * @param dev Device structure
1976 *
1977 * @return EOK if succeed
1978 * @return An error code otherwise
1979 *
1980 */
1981static errno_t e1000_get_resource_info(ddf_dev_t *dev)
1982{
1983 assert(dev != NULL);
1984 assert(NIC_DATA_DEV(dev) != NULL);
1985
1986 hw_res_list_parsed_t hw_res_parsed;
1987 hw_res_list_parsed_init(&hw_res_parsed);
1988
1989 /* Get hw resources form parent driver */
1990 errno_t rc = nic_get_resources(NIC_DATA_DEV(dev), &hw_res_parsed);
1991 if (rc != EOK)
1992 return rc;
1993
1994 /* Fill resources information to the device */
1995 rc = e1000_fill_resource_info(dev, &hw_res_parsed);
1996 hw_res_list_parsed_clean(&hw_res_parsed);
1997
1998 return rc;
1999}
2000
2001/** Initialize the E1000 device structure
2002 *
2003 * @param dev Device information
2004 *
2005 * @return EOK if succeed
2006 * @return An error code otherwise
2007 *
2008 */
2009static errno_t e1000_device_initialize(ddf_dev_t *dev)
2010{
2011 /* Allocate driver data for the device. */
2012 e1000_t *e1000 = e1000_create_dev_data(dev);
2013 if (e1000 == NULL) {
2014 ddf_msg(LVL_ERROR, "Unable to allocate device softstate");
2015 return ENOMEM;
2016 }
2017
2018 e1000->parent_sess = ddf_dev_parent_sess_get(dev);
2019 if (e1000->parent_sess == NULL) {
2020 ddf_msg(LVL_ERROR, "Failed connecting parent device.");
2021 return EIO;
2022 }
2023
2024 /* Obtain and fill hardware resources info */
2025 errno_t rc = e1000_get_resource_info(dev);
2026 if (rc != EOK) {
2027 ddf_msg(LVL_ERROR, "Cannot obtain hardware resources");
2028 e1000_dev_cleanup(dev);
2029 return rc;
2030 }
2031
2032 uint16_t device_id;
2033 rc = pci_config_space_read_16(ddf_dev_parent_sess_get(dev), PCI_DEVICE_ID,
2034 &device_id);
2035 if (rc != EOK) {
2036 ddf_msg(LVL_ERROR, "Cannot access PCI configuration space");
2037 e1000_dev_cleanup(dev);
2038 return rc;
2039 }
2040
2041 e1000_board_t board;
2042 switch (device_id) {
2043 case 0x100e:
2044 case 0x1015:
2045 case 0x1016:
2046 case 0x1017:
2047 board = E1000_82540;
2048 break;
2049 case 0x1013:
2050 case 0x1018:
2051 case 0x1078:
2052 board = E1000_82541;
2053 break;
2054 case 0x1076:
2055 case 0x1077:
2056 case 0x107c:
2057 board = E1000_82541REV2;
2058 break;
2059 case 0x100f:
2060 case 0x1011:
2061 case 0x1026:
2062 case 0x1027:
2063 case 0x1028:
2064 board = E1000_82545;
2065 break;
2066 case 0x1010:
2067 case 0x1012:
2068 case 0x101d:
2069 case 0x1079:
2070 case 0x107a:
2071 case 0x107b:
2072 board = E1000_82546;
2073 break;
2074 case 0x1019:
2075 case 0x101a:
2076 board = E1000_82547;
2077 break;
2078 case 0x10b9:
2079 board = E1000_82572;
2080 break;
2081 case 0x1096:
2082 board = E1000_80003ES2;
2083 break;
2084 default:
2085 ddf_msg(LVL_ERROR, "Device not supported (%#" PRIx16 ")",
2086 device_id);
2087 e1000_dev_cleanup(dev);
2088 return ENOTSUP;
2089 }
2090
2091 switch (board) {
2092 case E1000_82540:
2093 case E1000_82541:
2094 case E1000_82541REV2:
2095 case E1000_82545:
2096 case E1000_82546:
2097 e1000->info.eerd_start = 0x01;
2098 e1000->info.eerd_done = 0x10;
2099 e1000->info.eerd_address_offset = 8;
2100 e1000->info.eerd_data_offset = 16;
2101 break;
2102 case E1000_82547:
2103 case E1000_82572:
2104 case E1000_80003ES2:
2105 e1000->info.eerd_start = 0x01;
2106 e1000->info.eerd_done = 0x02;
2107 e1000->info.eerd_address_offset = 2;
2108 e1000->info.eerd_data_offset = 16;
2109 break;
2110 }
2111
2112 return EOK;
2113}
2114
2115/** Enable the I/O ports of the device.
2116 *
2117 * @param dev E1000 device.
2118 *
2119 * @return EOK if successed
2120 * @return An error code otherwise
2121 *
2122 */
2123static errno_t e1000_pio_enable(ddf_dev_t *dev)
2124{
2125 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
2126
2127 errno_t rc = pio_enable(e1000->reg_base_phys, 8 * PAGE_SIZE,
2128 &e1000->reg_base_virt);
2129 if (rc != EOK)
2130 return EADDRNOTAVAIL;
2131
2132 return EOK;
2133}
2134
2135/** Probe and initialize the newly added device.
2136 *
2137 * @param dev E1000 device.
2138 *
2139 */
2140errno_t e1000_dev_add(ddf_dev_t *dev)
2141{
2142 ddf_fun_t *fun;
2143
2144 /* Initialize device structure for E1000 */
2145 errno_t rc = e1000_device_initialize(dev);
2146 if (rc != EOK)
2147 return rc;
2148
2149 /* Device initialization */
2150 nic_t *nic = ddf_dev_data_get(dev);
2151 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2152
2153 /* Map registers */
2154 rc = e1000_pio_enable(dev);
2155 if (rc != EOK)
2156 goto err_destroy;
2157
2158 e1000_initialize_registers(e1000);
2159 rc = e1000_initialize_tx_structure(e1000);
2160 if (rc != EOK)
2161 goto err_pio;
2162
2163 fibril_mutex_lock(&e1000->rx_lock);
2164
2165 e1000_fill_mac_from_eeprom(e1000);
2166 e1000_initialize_filters(e1000);
2167
2168 fibril_mutex_unlock(&e1000->rx_lock);
2169
2170 e1000_initialize_vlan(e1000);
2171
2172 fun = ddf_fun_create(nic_get_ddf_dev(nic), fun_exposed, "port0");
2173 if (fun == NULL)
2174 goto err_tx_structure;
2175 nic_set_ddf_fun(nic, fun);
2176 ddf_fun_set_ops(fun, &e1000_dev_ops);
2177
2178 cap_irq_handle_t irq_handle;
2179 rc = e1000_register_int_handler(nic, &irq_handle);
2180 if (rc != EOK) {
2181 goto err_fun_create;
2182 }
2183
2184 rc = e1000_initialize_rx_structure(nic);
2185 if (rc != EOK)
2186 goto err_irq;
2187
2188 nic_address_t e1000_address;
2189 e1000_get_address(e1000, &e1000_address);
2190 rc = nic_report_address(nic, &e1000_address);
2191 if (rc != EOK)
2192 goto err_rx_structure;
2193
2194 struct timespec period;
2195 period.tv_sec = 0;
2196 period.tv_nsec = USEC2NSEC(E1000_DEFAULT_INTERRUPT_INTERVAL_USEC);
2197 rc = nic_report_poll_mode(nic, NIC_POLL_PERIODIC, &period);
2198 if (rc != EOK)
2199 goto err_rx_structure;
2200
2201 rc = ddf_fun_bind(fun);
2202 if (rc != EOK)
2203 goto err_fun_bind;
2204
2205 rc = ddf_fun_add_to_category(fun, DEVICE_CATEGORY_NIC);
2206 if (rc != EOK)
2207 goto err_add_to_cat;
2208
2209 errno_t pcap_rc = pcapdump_init(nic_get_pcap_iface(nic));
2210
2211 if (pcap_rc != EOK) {
2212 printf("Failed creating pcapdump port\n");
2213 }
2214 rc = ddf_fun_add_to_category(fun, "pcap");
2215 if (rc != EOK)
2216 goto err_add_to_cat;
2217
2218 return EOK;
2219
2220err_add_to_cat:
2221 ddf_fun_unbind(fun);
2222err_fun_bind:
2223err_rx_structure:
2224 e1000_uninitialize_rx_structure(nic);
2225err_irq:
2226 unregister_interrupt_handler(dev, irq_handle);
2227err_fun_create:
2228 ddf_fun_destroy(fun);
2229 nic_set_ddf_fun(nic, NULL);
2230err_tx_structure:
2231 e1000_uninitialize_tx_structure(e1000);
2232err_pio:
2233 // TODO: e1000_pio_disable(dev);
2234err_destroy:
2235 e1000_dev_cleanup(dev);
2236 return rc;
2237}
2238
2239/** Read 16-bit value from EEPROM of E1000 adapter
2240 *
2241 * Read using the EERD register.
2242 *
2243 * @param device E1000 device
2244 * @param eeprom_address 8-bit EEPROM address
2245 *
2246 * @return 16-bit value from EEPROM
2247 *
2248 */
2249static uint16_t e1000_eeprom_read(e1000_t *e1000, uint8_t eeprom_address)
2250{
2251 fibril_mutex_lock(&e1000->eeprom_lock);
2252
2253 /* Write address and START bit to EERD register */
2254 uint32_t write_data = e1000->info.eerd_start |
2255 (((uint32_t) eeprom_address) <<
2256 e1000->info.eerd_address_offset);
2257 E1000_REG_WRITE(e1000, E1000_EERD, write_data);
2258
2259 uint32_t eerd = E1000_REG_READ(e1000, E1000_EERD);
2260 while ((eerd & e1000->info.eerd_done) == 0) {
2261 fibril_usleep(1);
2262 eerd = E1000_REG_READ(e1000, E1000_EERD);
2263 }
2264
2265 fibril_mutex_unlock(&e1000->eeprom_lock);
2266
2267 return (uint16_t) (eerd >> e1000->info.eerd_data_offset);
2268}
2269
2270/** Get MAC address of the E1000 adapter
2271 *
2272 * @param device E1000 device
2273 * @param address Place to store the address
2274 * @param max_len Maximal addresss length to store
2275 *
2276 * @return EOK if succeed
2277 * @return An error code otherwise
2278 *
2279 */
2280static errno_t e1000_get_address(e1000_t *e1000, nic_address_t *address)
2281{
2282 fibril_mutex_lock(&e1000->rx_lock);
2283
2284 uint8_t *mac0_dest = (uint8_t *) address->address;
2285 uint8_t *mac1_dest = (uint8_t *) address->address + 1;
2286 uint8_t *mac2_dest = (uint8_t *) address->address + 2;
2287 uint8_t *mac3_dest = (uint8_t *) address->address + 3;
2288 uint8_t *mac4_dest = (uint8_t *) address->address + 4;
2289 uint8_t *mac5_dest = (uint8_t *) address->address + 5;
2290
2291 uint32_t rah = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
2292 uint32_t ral = E1000_REG_READ(e1000, E1000_RAL_ARRAY(0));
2293
2294 *mac0_dest = (uint8_t) ral;
2295 *mac1_dest = (uint8_t) (ral >> 8);
2296 *mac2_dest = (uint8_t) (ral >> 16);
2297 *mac3_dest = (uint8_t) (ral >> 24);
2298 *mac4_dest = (uint8_t) rah;
2299 *mac5_dest = (uint8_t) (rah >> 8);
2300
2301 fibril_mutex_unlock(&e1000->rx_lock);
2302 return EOK;
2303}
2304
2305/** Set card MAC address
2306 *
2307 * @param device E1000 device
2308 * @param address Address
2309 *
2310 * @return EOK if succeed
2311 * @return An error code otherwise
2312 */
2313static errno_t e1000_set_addr(ddf_fun_t *fun, const nic_address_t *addr)
2314{
2315 nic_t *nic = NIC_DATA_FUN(fun);
2316 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2317
2318 fibril_mutex_lock(&e1000->rx_lock);
2319 fibril_mutex_lock(&e1000->tx_lock);
2320
2321 errno_t rc = nic_report_address(nic, addr);
2322 if (rc == EOK)
2323 e1000_write_receive_address(e1000, 0, addr, false);
2324
2325 fibril_mutex_unlock(&e1000->tx_lock);
2326 fibril_mutex_unlock(&e1000->rx_lock);
2327
2328 return rc;
2329}
2330
2331static void e1000_eeprom_get_address(e1000_t *e1000,
2332 nic_address_t *address)
2333{
2334 uint16_t *mac0_dest = (uint16_t *) address->address;
2335 uint16_t *mac2_dest = (uint16_t *) (address->address + 2);
2336 uint16_t *mac4_dest = (uint16_t *) (address->address + 4);
2337
2338 *mac0_dest = e1000_eeprom_read(e1000, 0);
2339 *mac2_dest = e1000_eeprom_read(e1000, 1);
2340 *mac4_dest = e1000_eeprom_read(e1000, 2);
2341}
2342
2343/** Send frame
2344 *
2345 * @param nic NIC driver data structure
2346 * @param data Frame data
2347 * @param size Frame size in bytes
2348 *
2349 * @return EOK if succeed
2350 * @return Error code in the case of error
2351 *
2352 */
2353static void e1000_send_frame(nic_t *nic, void *data, size_t size)
2354{
2355 assert(nic);
2356
2357 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2358 fibril_mutex_lock(&e1000->tx_lock);
2359
2360 uint32_t tdt = E1000_REG_READ(e1000, E1000_TDT);
2361 e1000_tx_descriptor_t *tx_descriptor_addr = (e1000_tx_descriptor_t *)
2362 (e1000->tx_ring_virt + tdt * sizeof(e1000_tx_descriptor_t));
2363
2364 bool descriptor_available = false;
2365
2366 /* Descriptor never used */
2367 if (tx_descriptor_addr->length == 0)
2368 descriptor_available = true;
2369
2370 /* Descriptor done */
2371 if (tx_descriptor_addr->status & TXDESCRIPTOR_STATUS_DD)
2372 descriptor_available = true;
2373
2374 if (!descriptor_available) {
2375 /* Frame lost */
2376 fibril_mutex_unlock(&e1000->tx_lock);
2377 return;
2378 }
2379
2380 memcpy(e1000->tx_frame_virt[tdt], data, size);
2381 pcapdump_packet(nic_get_pcap_iface(nic), data, size);
2382 tx_descriptor_addr->phys_addr = PTR_TO_U64(e1000->tx_frame_phys[tdt]);
2383 tx_descriptor_addr->length = size;
2384
2385 /*
2386 * Report status to STATUS.DD (descriptor done),
2387 * add ethernet CRC, end of packet.
2388 */
2389 tx_descriptor_addr->command = TXDESCRIPTOR_COMMAND_RS |
2390 TXDESCRIPTOR_COMMAND_IFCS |
2391 TXDESCRIPTOR_COMMAND_EOP;
2392
2393 tx_descriptor_addr->checksum_offset = 0;
2394 tx_descriptor_addr->status = 0;
2395 if (e1000->vlan_tag_add) {
2396 tx_descriptor_addr->special = e1000->vlan_tag;
2397 tx_descriptor_addr->command |= TXDESCRIPTOR_COMMAND_VLE;
2398 } else
2399 tx_descriptor_addr->special = 0;
2400
2401 tx_descriptor_addr->checksum_start_field = 0;
2402
2403 tdt++;
2404 if (tdt == E1000_TX_FRAME_COUNT)
2405 tdt = 0;
2406
2407 E1000_REG_WRITE(e1000, E1000_TDT, tdt);
2408
2409 fibril_mutex_unlock(&e1000->tx_lock);
2410}
2411
2412int main(void)
2413{
2414 printf("%s: HelenOS E1000 network adapter driver\n", NAME);
2415
2416 if (nic_driver_init(NAME) != EOK)
2417 return 1;
2418
2419 nic_driver_implement(&e1000_driver_ops, &e1000_dev_ops,
2420 &e1000_nic_iface);
2421
2422 ddf_log_init(NAME);
2423 return ddf_driver_main(&e1000_driver);
2424}
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