source: mainline/uspace/drv/nic/e1k/e1k.c

Last change on this file was 3a4c6d9, checked in by Jiri Svoboda <jiri@…>, 4 weeks ago

Packet capture (thx Nataliia Korop)
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File size: 56.8 KB
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1/*
2 * Copyright (c) 2025 Jiri Svoboda
3 * Copyright (c) 2011 Zdenek Bouska
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/** @file e1k.c
31 *
32 * Driver for Intel Pro/1000 8254x Family of Gigabit Ethernet Controllers
33 *
34 */
35
36#include <async.h>
37#include <assert.h>
38#include <stdio.h>
39#include <errno.h>
40#include <adt/list.h>
41#include <align.h>
42#include <byteorder.h>
43#include <as.h>
44#include <ddi.h>
45#include <ddf/log.h>
46#include <ddf/interrupt.h>
47#include <device/hw_res.h>
48#include <device/hw_res_parsed.h>
49#include <pci_dev_iface.h>
50#include <nic.h>
51#include <ops/nic.h>
52#include "e1k.h"
53
54#define NAME "e1k"
55
56#define E1000_DEFAULT_INTERRUPT_INTERVAL_USEC 250
57
58/* Must be power of 8 */
59#define E1000_RX_FRAME_COUNT 128
60#define E1000_TX_FRAME_COUNT 128
61
62#define E1000_RECEIVE_ADDRESS 16
63
64/** Maximum sending frame size */
65#define E1000_MAX_SEND_FRAME_SIZE 2048
66/** Maximum receiving frame size */
67#define E1000_MAX_RECEIVE_FRAME_SIZE 2048
68
69/** nic_driver_data_t* -> e1000_t* cast */
70#define DRIVER_DATA_NIC(nic) \
71 ((e1000_t *) nic_get_specific(nic))
72
73/** ddf_fun_t * -> nic_driver_data_t* cast */
74#define NIC_DATA_FUN(fun) \
75 ((nic_t *) ddf_dev_data_get(ddf_fun_get_dev(fun)))
76
77/** ddf_dev_t * -> nic_driver_data_t* cast */
78#define NIC_DATA_DEV(dev) \
79 ((nic_t *) ddf_dev_data_get(dev))
80
81/** ddf_dev_t * -> e1000_t* cast */
82#define DRIVER_DATA_DEV(dev) \
83 (DRIVER_DATA_NIC(NIC_DATA_DEV(dev)))
84
85/** ddf_fun_t * -> e1000_t* cast */
86#define DRIVER_DATA_FUN(fun) \
87 (DRIVER_DATA_NIC(NIC_DATA_FUN(fun)))
88
89/** Cast pointer to uint64_t
90 *
91 * @param ptr Pointer to cast
92 *
93 * @return The uint64_t pointer representation.
94 *
95 */
96#define PTR_TO_U64(ptr) ((uint64_t) ((uintptr_t) (ptr)))
97
98/** Cast the memaddr part to the void*
99 *
100 * @param memaddr The memaddr value
101 *
102 */
103#define MEMADDR_TO_PTR(memaddr) ((void *) ((size_t) (memaddr)))
104
105#define E1000_REG_BASE(e1000) \
106 ((e1000)->reg_base_virt)
107
108#define E1000_REG_ADDR(e1000, reg) \
109 ((uint32_t *) (E1000_REG_BASE(e1000) + reg))
110
111#define E1000_REG_READ(e1000, reg) \
112 (pio_read_32(E1000_REG_ADDR(e1000, reg)))
113
114#define E1000_REG_WRITE(e1000, reg, value) \
115 (pio_write_32(E1000_REG_ADDR(e1000, reg), value))
116
117/** E1000 device data */
118typedef struct {
119 /** DDF device */
120 ddf_dev_t *dev;
121 /** Parent session */
122 async_sess_t *parent_sess;
123 /** Device configuration */
124 e1000_info_t info;
125
126 /** Physical registers base address */
127 void *reg_base_phys;
128 /** Virtual registers base address */
129 void *reg_base_virt;
130
131 /** Physical tx ring address */
132 uintptr_t tx_ring_phys;
133 /** Virtual tx ring address */
134 void *tx_ring_virt;
135
136 /** Ring of TX frames, physical address */
137 uintptr_t *tx_frame_phys;
138 /** Ring of TX frames, virtual address */
139 void **tx_frame_virt;
140
141 /** Physical rx ring address */
142 uintptr_t rx_ring_phys;
143 /** Virtual rx ring address */
144 void *rx_ring_virt;
145
146 /** Ring of RX frames, physical address */
147 uintptr_t *rx_frame_phys;
148 /** Ring of RX frames, virtual address */
149 void **rx_frame_virt;
150
151 /** VLAN tag */
152 uint16_t vlan_tag;
153
154 /** Add VLAN tag to frame */
155 bool vlan_tag_add;
156
157 /** Used unicast Receive Address count */
158 unsigned int unicast_ra_count;
159
160 /** Used milticast Receive addrress count */
161 unsigned int multicast_ra_count;
162
163 /** The irq assigned */
164 int irq;
165
166 /** Lock for CTRL register */
167 fibril_mutex_t ctrl_lock;
168
169 /** Lock for receiver */
170 fibril_mutex_t rx_lock;
171
172 /** Lock for transmitter */
173 fibril_mutex_t tx_lock;
174
175 /** Lock for EEPROM access */
176 fibril_mutex_t eeprom_lock;
177
178} e1000_t;
179
180/** Global mutex for work with shared irq structure */
181FIBRIL_MUTEX_INITIALIZE(irq_reg_mutex);
182
183static errno_t e1000_get_address(e1000_t *, nic_address_t *);
184static void e1000_eeprom_get_address(e1000_t *, nic_address_t *);
185static errno_t e1000_set_addr(ddf_fun_t *, const nic_address_t *);
186
187static errno_t e1000_defective_get_mode(ddf_fun_t *, uint32_t *);
188static errno_t e1000_defective_set_mode(ddf_fun_t *, uint32_t);
189
190static errno_t e1000_get_cable_state(ddf_fun_t *, nic_cable_state_t *);
191static errno_t e1000_get_device_info(ddf_fun_t *, nic_device_info_t *);
192static errno_t e1000_get_operation_mode(ddf_fun_t *, int *,
193 nic_channel_mode_t *, nic_role_t *);
194static errno_t e1000_set_operation_mode(ddf_fun_t *, int,
195 nic_channel_mode_t, nic_role_t);
196static errno_t e1000_autoneg_enable(ddf_fun_t *, uint32_t);
197static errno_t e1000_autoneg_disable(ddf_fun_t *);
198static errno_t e1000_autoneg_restart(ddf_fun_t *);
199
200static errno_t e1000_vlan_set_tag(ddf_fun_t *, uint16_t, bool, bool);
201
202/** Network interface options for E1000 card driver */
203static nic_iface_t e1000_nic_iface;
204
205/** Network interface options for E1000 card driver */
206static nic_iface_t e1000_nic_iface = {
207 .set_address = &e1000_set_addr,
208 .get_device_info = &e1000_get_device_info,
209 .get_cable_state = &e1000_get_cable_state,
210 .get_operation_mode = &e1000_get_operation_mode,
211 .set_operation_mode = &e1000_set_operation_mode,
212 .autoneg_enable = &e1000_autoneg_enable,
213 .autoneg_disable = &e1000_autoneg_disable,
214 .autoneg_restart = &e1000_autoneg_restart,
215 .vlan_set_tag = &e1000_vlan_set_tag,
216 .defective_get_mode = &e1000_defective_get_mode,
217 .defective_set_mode = &e1000_defective_set_mode,
218};
219
220/** Basic device operations for E1000 driver */
221static ddf_dev_ops_t e1000_dev_ops;
222
223static errno_t e1000_dev_add(ddf_dev_t *);
224static errno_t e1000_dev_quiesce(ddf_dev_t *);
225
226/** Basic driver operations for E1000 driver */
227static driver_ops_t e1000_driver_ops = {
228 .dev_add = e1000_dev_add,
229 .dev_quiesce = e1000_dev_quiesce
230};
231
232/** Driver structure for E1000 driver */
233static driver_t e1000_driver = {
234 .name = NAME,
235 .driver_ops = &e1000_driver_ops
236};
237
238/* The default implementation callbacks */
239static errno_t e1000_on_activating(nic_t *);
240static errno_t e1000_on_stopping(nic_t *);
241static void e1000_send_frame(nic_t *, void *, size_t);
242
243/** PIO ranges used in the IRQ code. */
244irq_pio_range_t e1000_irq_pio_ranges[] = {
245 {
246 .base = 0,
247 .size = PAGE_SIZE, /* XXX */
248 }
249};
250
251/** Commands to deal with interrupt
252 *
253 */
254irq_cmd_t e1000_irq_commands[] = {
255 {
256 /* Get the interrupt status */
257 .cmd = CMD_PIO_READ_32,
258 .addr = NULL,
259 .dstarg = 2
260 },
261 {
262 .cmd = CMD_AND,
263 .value = ICR_RXT0,
264 .srcarg = 2,
265 .dstarg = 1
266 },
267 {
268 .cmd = CMD_PREDICATE,
269 .value = 2,
270 .srcarg = 1
271 },
272 {
273 /* Disable interrupts until interrupt routine is finished */
274 .cmd = CMD_PIO_WRITE_32,
275 .addr = NULL,
276 .value = 0xffffffff
277 },
278 {
279 .cmd = CMD_ACCEPT
280 }
281};
282
283/** Interrupt code definition */
284irq_code_t e1000_irq_code = {
285 .rangecount = sizeof(e1000_irq_pio_ranges) /
286 sizeof(irq_pio_range_t),
287 .ranges = e1000_irq_pio_ranges,
288 .cmdcount = sizeof(e1000_irq_commands) / sizeof(irq_cmd_t),
289 .cmds = e1000_irq_commands
290};
291
292/** Get the device information
293 *
294 * @param dev NIC device
295 * @param info Information to fill
296 *
297 * @return EOK
298 *
299 */
300static errno_t e1000_get_device_info(ddf_fun_t *dev, nic_device_info_t *info)
301{
302 assert(dev);
303 assert(info);
304
305 memset(info, 0, sizeof(nic_device_info_t));
306
307 info->vendor_id = 0x8086;
308 str_cpy(info->vendor_name, NIC_VENDOR_MAX_LENGTH,
309 "Intel Corporation");
310 str_cpy(info->model_name, NIC_MODEL_MAX_LENGTH,
311 "Intel Pro");
312
313 info->ethernet_support[ETH_10M] = ETH_10BASE_T;
314 info->ethernet_support[ETH_100M] = ETH_100BASE_TX;
315 info->ethernet_support[ETH_1000M] = ETH_1000BASE_T;
316
317 return EOK;
318}
319
320/** Check the cable state
321 *
322 * @param[in] dev device
323 * @param[out] state state to fill
324 *
325 * @return EOK
326 *
327 */
328static errno_t e1000_get_cable_state(ddf_fun_t *fun, nic_cable_state_t *state)
329{
330 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
331 if (E1000_REG_READ(e1000, E1000_STATUS) & (STATUS_LU))
332 *state = NIC_CS_PLUGGED;
333 else
334 *state = NIC_CS_UNPLUGGED;
335
336 return EOK;
337}
338
339static uint16_t e1000_calculate_itr_interval_from_usecs(usec_t useconds)
340{
341 return useconds * 4;
342}
343
344/** Get operation mode of the device
345 *
346 */
347static errno_t e1000_get_operation_mode(ddf_fun_t *fun, int *speed,
348 nic_channel_mode_t *duplex, nic_role_t *role)
349{
350 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
351 uint32_t status = E1000_REG_READ(e1000, E1000_STATUS);
352
353 if (status & STATUS_FD)
354 *duplex = NIC_CM_FULL_DUPLEX;
355 else
356 *duplex = NIC_CM_HALF_DUPLEX;
357
358 uint32_t speed_bits =
359 (status >> STATUS_SPEED_SHIFT) & STATUS_SPEED_ALL;
360
361 if (speed_bits == STATUS_SPEED_10)
362 *speed = 10;
363 else if (speed_bits == STATUS_SPEED_100)
364 *speed = 100;
365 else if ((speed_bits == STATUS_SPEED_1000A) ||
366 (speed_bits == STATUS_SPEED_1000B))
367 *speed = 1000;
368
369 *role = NIC_ROLE_UNKNOWN;
370 return EOK;
371}
372
373static void e1000_link_restart(e1000_t *e1000)
374{
375 fibril_mutex_lock(&e1000->ctrl_lock);
376
377 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
378
379 if (ctrl & CTRL_SLU) {
380 ctrl &= ~(CTRL_SLU);
381 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
382 fibril_mutex_unlock(&e1000->ctrl_lock);
383
384 fibril_usleep(10);
385
386 fibril_mutex_lock(&e1000->ctrl_lock);
387 ctrl = E1000_REG_READ(e1000, E1000_CTRL);
388 ctrl |= CTRL_SLU;
389 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
390 }
391
392 fibril_mutex_unlock(&e1000->ctrl_lock);
393}
394
395/** Set operation mode of the device
396 *
397 */
398static errno_t e1000_set_operation_mode(ddf_fun_t *fun, int speed,
399 nic_channel_mode_t duplex, nic_role_t role)
400{
401 if ((speed != 10) && (speed != 100) && (speed != 1000))
402 return EINVAL;
403
404 if ((duplex != NIC_CM_HALF_DUPLEX) && (duplex != NIC_CM_FULL_DUPLEX))
405 return EINVAL;
406
407 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
408
409 fibril_mutex_lock(&e1000->ctrl_lock);
410 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
411
412 ctrl |= CTRL_FRCSPD;
413 ctrl |= CTRL_FRCDPLX;
414 ctrl &= ~(CTRL_ASDE);
415
416 if (duplex == NIC_CM_FULL_DUPLEX)
417 ctrl |= CTRL_FD;
418 else
419 ctrl &= ~(CTRL_FD);
420
421 ctrl &= ~(CTRL_SPEED_MASK);
422 if (speed == 1000)
423 ctrl |= CTRL_SPEED_1000 << CTRL_SPEED_SHIFT;
424 else if (speed == 100)
425 ctrl |= CTRL_SPEED_100 << CTRL_SPEED_SHIFT;
426 else
427 ctrl |= CTRL_SPEED_10 << CTRL_SPEED_SHIFT;
428
429 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
430
431 fibril_mutex_unlock(&e1000->ctrl_lock);
432
433 e1000_link_restart(e1000);
434
435 return EOK;
436}
437
438/** Enable auto-negotiation
439 *
440 * @param dev Device to update
441 * @param advertisement Ignored on E1000
442 *
443 * @return EOK if advertisement mode set successfully
444 *
445 */
446static errno_t e1000_autoneg_enable(ddf_fun_t *fun, uint32_t advertisement)
447{
448 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
449
450 fibril_mutex_lock(&e1000->ctrl_lock);
451
452 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
453
454 ctrl &= ~(CTRL_FRCSPD);
455 ctrl &= ~(CTRL_FRCDPLX);
456 ctrl |= CTRL_ASDE;
457
458 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
459
460 fibril_mutex_unlock(&e1000->ctrl_lock);
461
462 e1000_link_restart(e1000);
463
464 return EOK;
465}
466
467/** Disable auto-negotiation
468 *
469 * @param dev Device to update
470 *
471 * @return EOK
472 *
473 */
474static errno_t e1000_autoneg_disable(ddf_fun_t *fun)
475{
476 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
477
478 fibril_mutex_lock(&e1000->ctrl_lock);
479
480 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
481
482 ctrl |= CTRL_FRCSPD;
483 ctrl |= CTRL_FRCDPLX;
484 ctrl &= ~(CTRL_ASDE);
485
486 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
487
488 fibril_mutex_unlock(&e1000->ctrl_lock);
489
490 e1000_link_restart(e1000);
491
492 return EOK;
493}
494
495/** Restart auto-negotiation
496 *
497 * @param dev Device to update
498 *
499 * @return EOK if advertisement mode set successfully
500 *
501 */
502static errno_t e1000_autoneg_restart(ddf_fun_t *dev)
503{
504 return e1000_autoneg_enable(dev, 0);
505}
506
507/** Get state of acceptance of weird frames
508 *
509 * @param device Device to check
510 * @param[out] mode Current mode
511 *
512 */
513static errno_t e1000_defective_get_mode(ddf_fun_t *fun, uint32_t *mode)
514{
515 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
516
517 *mode = 0;
518 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
519 if (rctl & RCTL_SBP)
520 *mode = NIC_DEFECTIVE_BAD_CRC | NIC_DEFECTIVE_SHORT;
521
522 return EOK;
523}
524
525/** Set acceptance of weird frames
526 *
527 * @param device Device to update
528 * @param mode Mode to set
529 *
530 * @return ENOTSUP if the mode is not supported
531 * @return EOK of mode was set
532 *
533 */
534static errno_t e1000_defective_set_mode(ddf_fun_t *fun, uint32_t mode)
535{
536 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
537 errno_t rc = EOK;
538
539 fibril_mutex_lock(&e1000->rx_lock);
540
541 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
542 bool short_mode = (mode & NIC_DEFECTIVE_SHORT ? true : false);
543 bool bad_mode = (mode & NIC_DEFECTIVE_BAD_CRC ? true : false);
544
545 if (short_mode && bad_mode)
546 rctl |= RCTL_SBP;
547 else if ((!short_mode) && (!bad_mode))
548 rctl &= ~RCTL_SBP;
549 else
550 rc = ENOTSUP;
551
552 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
553
554 fibril_mutex_unlock(&e1000->rx_lock);
555 return rc;
556}
557
558/** Write receive address to RA registr
559 *
560 * @param e1000 E1000 data structure
561 * @param position RA register position
562 * @param address Ethernet address
563 * @param set_av_bit Set the Addtess Valid bit
564 *
565 */
566static void e1000_write_receive_address(e1000_t *e1000, unsigned int position,
567 const nic_address_t *address, bool set_av_bit)
568{
569 uint8_t *mac0 = (uint8_t *) address->address;
570 uint8_t *mac1 = (uint8_t *) address->address + 1;
571 uint8_t *mac2 = (uint8_t *) address->address + 2;
572 uint8_t *mac3 = (uint8_t *) address->address + 3;
573 uint8_t *mac4 = (uint8_t *) address->address + 4;
574 uint8_t *mac5 = (uint8_t *) address->address + 5;
575
576 uint32_t rah;
577 uint32_t ral;
578
579 ral = ((*mac3) << 24) | ((*mac2) << 16) | ((*mac1) << 8) | (*mac0);
580 rah = ((*mac5) << 8) | ((*mac4));
581
582 if (set_av_bit)
583 rah |= RAH_AV;
584 else
585 rah |= E1000_REG_READ(e1000, E1000_RAH_ARRAY(position)) & RAH_AV;
586
587 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(position), rah);
588 E1000_REG_WRITE(e1000, E1000_RAL_ARRAY(position), ral);
589}
590
591/** Disable receive address in RA registr
592 *
593 * Clear Address Valid bit
594 *
595 * @param e1000 E1000 data structure
596 * @param position RA register position
597 *
598 */
599static void e1000_disable_receive_address(e1000_t *e1000, unsigned int position)
600{
601 uint32_t rah = E1000_REG_READ(e1000, E1000_RAH_ARRAY(position));
602 rah = rah & ~RAH_AV;
603 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(position), rah);
604}
605
606/** Clear all unicast addresses from RA registers
607 *
608 * @param e1000 E1000 data structure
609 *
610 */
611static void e1000_clear_unicast_receive_addresses(e1000_t *e1000)
612{
613 for (unsigned int ra_num = 1;
614 ra_num <= e1000->unicast_ra_count;
615 ra_num++)
616 e1000_disable_receive_address(e1000, ra_num);
617
618 e1000->unicast_ra_count = 0;
619}
620
621/** Clear all multicast addresses from RA registers
622 *
623 * @param e1000 E1000 data structure
624 *
625 */
626static void e1000_clear_multicast_receive_addresses(e1000_t *e1000)
627{
628 unsigned int first_multicast_ra_num =
629 E1000_RECEIVE_ADDRESS - e1000->multicast_ra_count;
630
631 for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1;
632 ra_num >= first_multicast_ra_num;
633 ra_num--)
634 e1000_disable_receive_address(e1000, ra_num);
635
636 e1000->multicast_ra_count = 0;
637}
638
639/** Return receive address filter positions count usable for unicast
640 *
641 * @param e1000 E1000 data structure
642 *
643 * @return receive address filter positions count usable for unicast
644 *
645 */
646static unsigned int get_free_unicast_address_count(e1000_t *e1000)
647{
648 return E1000_RECEIVE_ADDRESS - 1 - e1000->multicast_ra_count;
649}
650
651/** Return receive address filter positions count usable for multicast
652 *
653 * @param e1000 E1000 data structure
654 *
655 * @return receive address filter positions count usable for multicast
656 *
657 */
658static unsigned int get_free_multicast_address_count(e1000_t *e1000)
659{
660 return E1000_RECEIVE_ADDRESS - 1 - e1000->unicast_ra_count;
661}
662
663/** Write unicast receive addresses to receive address filter registers
664 *
665 * @param e1000 E1000 data structure
666 * @param addr Pointer to address array
667 * @param addr_cnt Address array count
668 *
669 */
670static void e1000_add_unicast_receive_addresses(e1000_t *e1000,
671 const nic_address_t *addr, size_t addr_cnt)
672{
673 assert(addr_cnt <= get_free_unicast_address_count(e1000));
674
675 nic_address_t *addr_iterator = (nic_address_t *) addr;
676
677 /* ra_num = 0 is primary address */
678 for (unsigned int ra_num = 1;
679 ra_num <= addr_cnt;
680 ra_num++) {
681 e1000_write_receive_address(e1000, ra_num, addr_iterator, true);
682 addr_iterator++;
683 }
684}
685
686/** Write multicast receive addresses to receive address filter registers
687 *
688 * @param e1000 E1000 data structure
689 * @param addr Pointer to address array
690 * @param addr_cnt Address array count
691 *
692 */
693static void e1000_add_multicast_receive_addresses(e1000_t *e1000,
694 const nic_address_t *addr, size_t addr_cnt)
695{
696 assert(addr_cnt <= get_free_multicast_address_count(e1000));
697
698 nic_address_t *addr_iterator = (nic_address_t *) addr;
699
700 unsigned int first_multicast_ra_num = E1000_RECEIVE_ADDRESS - addr_cnt;
701 for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1;
702 ra_num >= first_multicast_ra_num;
703 ra_num--) {
704 e1000_write_receive_address(e1000, ra_num, addr_iterator, true);
705 addr_iterator++;
706 }
707}
708
709/** Disable receiving frames for default address
710 *
711 * @param e1000 E1000 data structure
712 *
713 */
714static void disable_ra0_address_filter(e1000_t *e1000)
715{
716 uint32_t rah0 = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
717 rah0 = rah0 & ~RAH_AV;
718 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(0), rah0);
719}
720
721/** Enable receiving frames for default address
722 *
723 * @param e1000 E1000 data structure
724 *
725 */
726static void enable_ra0_address_filter(e1000_t *e1000)
727{
728 uint32_t rah0 = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
729 rah0 = rah0 | RAH_AV;
730 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(0), rah0);
731}
732
733/** Disable unicast promiscuous mode
734 *
735 * @param e1000 E1000 data structure
736 *
737 */
738static void e1000_disable_unicast_promisc(e1000_t *e1000)
739{
740 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
741 rctl = rctl & ~RCTL_UPE;
742 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
743}
744
745/** Enable unicast promiscuous mode
746 *
747 * @param e1000 E1000 data structure
748 *
749 */
750static void e1000_enable_unicast_promisc(e1000_t *e1000)
751{
752 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
753 rctl = rctl | RCTL_UPE;
754 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
755}
756
757/** Disable multicast promiscuous mode
758 *
759 * @param e1000 E1000 data structure
760 *
761 */
762static void e1000_disable_multicast_promisc(e1000_t *e1000)
763{
764 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
765 rctl = rctl & ~RCTL_MPE;
766 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
767}
768
769/** Enable multicast promiscuous mode
770 *
771 * @param e1000 E1000 data structure
772 *
773 */
774static void e1000_enable_multicast_promisc(e1000_t *e1000)
775{
776 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
777 rctl = rctl | RCTL_MPE;
778 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
779}
780
781/** Enable accepting of broadcast frames
782 *
783 * @param e1000 E1000 data structure
784 *
785 */
786static void e1000_enable_broadcast_accept(e1000_t *e1000)
787{
788 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
789 rctl = rctl | RCTL_BAM;
790 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
791}
792
793/** Disable accepting of broadcast frames
794 *
795 * @param e1000 E1000 data structure
796 *
797 */
798static void e1000_disable_broadcast_accept(e1000_t *e1000)
799{
800 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
801 rctl = rctl & ~RCTL_BAM;
802 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
803}
804
805/** Enable VLAN filtering according to VFTA registers
806 *
807 * @param e1000 E1000 data structure
808 *
809 */
810static void e1000_enable_vlan_filter(e1000_t *e1000)
811{
812 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
813 rctl = rctl | RCTL_VFE;
814 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
815}
816
817/** Disable VLAN filtering
818 *
819 * @param e1000 E1000 data structure
820 *
821 */
822static void e1000_disable_vlan_filter(e1000_t *e1000)
823{
824 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
825 rctl = rctl & ~RCTL_VFE;
826 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
827}
828
829/** Set multicast frames acceptance mode
830 *
831 * @param nic NIC device to update
832 * @param mode Mode to set
833 * @param addr Address list (used in mode = NIC_MULTICAST_LIST)
834 * @param addr_cnt Length of address list (used in mode = NIC_MULTICAST_LIST)
835 *
836 * @return EOK
837 *
838 */
839static errno_t e1000_on_multicast_mode_change(nic_t *nic, nic_multicast_mode_t mode,
840 const nic_address_t *addr, size_t addr_cnt)
841{
842 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
843 errno_t rc = EOK;
844
845 fibril_mutex_lock(&e1000->rx_lock);
846
847 switch (mode) {
848 case NIC_MULTICAST_BLOCKED:
849 e1000_clear_multicast_receive_addresses(e1000);
850 e1000_disable_multicast_promisc(e1000);
851 nic_report_hw_filtering(nic, -1, 1, -1);
852 break;
853 case NIC_MULTICAST_LIST:
854 e1000_clear_multicast_receive_addresses(e1000);
855 if (addr_cnt > get_free_multicast_address_count(e1000)) {
856 /*
857 * Future work: fill MTA table
858 * Not strictly neccessary, it only saves some compares
859 * in the NIC library.
860 */
861 e1000_enable_multicast_promisc(e1000);
862 nic_report_hw_filtering(nic, -1, 0, -1);
863 } else {
864 e1000_disable_multicast_promisc(e1000);
865 e1000_add_multicast_receive_addresses(e1000, addr, addr_cnt);
866 nic_report_hw_filtering(nic, -1, 1, -1);
867 }
868 break;
869 case NIC_MULTICAST_PROMISC:
870 e1000_enable_multicast_promisc(e1000);
871 e1000_clear_multicast_receive_addresses(e1000);
872 nic_report_hw_filtering(nic, -1, 1, -1);
873 break;
874 default:
875 rc = ENOTSUP;
876 break;
877 }
878
879 fibril_mutex_unlock(&e1000->rx_lock);
880 return rc;
881}
882
883/** Set unicast frames acceptance mode
884 *
885 * @param nic NIC device to update
886 * @param mode Mode to set
887 * @param addr Address list (used in mode = NIC_MULTICAST_LIST)
888 * @param addr_cnt Length of address list (used in mode = NIC_MULTICAST_LIST)
889 *
890 * @return EOK
891 *
892 */
893static errno_t e1000_on_unicast_mode_change(nic_t *nic, nic_unicast_mode_t mode,
894 const nic_address_t *addr, size_t addr_cnt)
895{
896 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
897 errno_t rc = EOK;
898
899 fibril_mutex_lock(&e1000->rx_lock);
900
901 switch (mode) {
902 case NIC_UNICAST_BLOCKED:
903 disable_ra0_address_filter(e1000);
904 e1000_clear_unicast_receive_addresses(e1000);
905 e1000_disable_unicast_promisc(e1000);
906 nic_report_hw_filtering(nic, 1, -1, -1);
907 break;
908 case NIC_UNICAST_DEFAULT:
909 enable_ra0_address_filter(e1000);
910 e1000_clear_unicast_receive_addresses(e1000);
911 e1000_disable_unicast_promisc(e1000);
912 nic_report_hw_filtering(nic, 1, -1, -1);
913 break;
914 case NIC_UNICAST_LIST:
915 enable_ra0_address_filter(e1000);
916 e1000_clear_unicast_receive_addresses(e1000);
917 if (addr_cnt > get_free_unicast_address_count(e1000)) {
918 e1000_enable_unicast_promisc(e1000);
919 nic_report_hw_filtering(nic, 0, -1, -1);
920 } else {
921 e1000_disable_unicast_promisc(e1000);
922 e1000_add_unicast_receive_addresses(e1000, addr, addr_cnt);
923 nic_report_hw_filtering(nic, 1, -1, -1);
924 }
925 break;
926 case NIC_UNICAST_PROMISC:
927 e1000_enable_unicast_promisc(e1000);
928 enable_ra0_address_filter(e1000);
929 e1000_clear_unicast_receive_addresses(e1000);
930 nic_report_hw_filtering(nic, 1, -1, -1);
931 break;
932 default:
933 rc = ENOTSUP;
934 break;
935 }
936
937 fibril_mutex_unlock(&e1000->rx_lock);
938 return rc;
939}
940
941/** Set broadcast frames acceptance mode
942 *
943 * @param nic NIC device to update
944 * @param mode Mode to set
945 *
946 * @return EOK
947 *
948 */
949static errno_t e1000_on_broadcast_mode_change(nic_t *nic, nic_broadcast_mode_t mode)
950{
951 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
952 errno_t rc = EOK;
953
954 fibril_mutex_lock(&e1000->rx_lock);
955
956 switch (mode) {
957 case NIC_BROADCAST_BLOCKED:
958 e1000_disable_broadcast_accept(e1000);
959 break;
960 case NIC_BROADCAST_ACCEPTED:
961 e1000_enable_broadcast_accept(e1000);
962 break;
963 default:
964 rc = ENOTSUP;
965 break;
966 }
967
968 fibril_mutex_unlock(&e1000->rx_lock);
969 return rc;
970}
971
972/** Check if receiving is enabled
973 *
974 * @param e1000 E1000 data structure
975 *
976 * @return true if receiving is enabled
977 *
978 */
979static bool e1000_is_rx_enabled(e1000_t *e1000)
980{
981 if (E1000_REG_READ(e1000, E1000_RCTL) & (RCTL_EN))
982 return true;
983
984 return false;
985}
986
987/** Enable receiving
988 *
989 * @param e1000 E1000 data structure
990 *
991 */
992static void e1000_enable_rx(e1000_t *e1000)
993{
994 /* Set Receive Enable Bit */
995 E1000_REG_WRITE(e1000, E1000_RCTL,
996 E1000_REG_READ(e1000, E1000_RCTL) | (RCTL_EN));
997}
998
999/** Disable receiving
1000 *
1001 * @param e1000 E1000 data structure
1002 *
1003 */
1004static void e1000_disable_rx(e1000_t *e1000)
1005{
1006 /* Clear Receive Enable Bit */
1007 E1000_REG_WRITE(e1000, E1000_RCTL,
1008 E1000_REG_READ(e1000, E1000_RCTL) & ~(RCTL_EN));
1009}
1010
1011/** Set VLAN mask
1012 *
1013 * @param nic NIC device to update
1014 * @param vlan_mask VLAN mask
1015 *
1016 */
1017static void e1000_on_vlan_mask_change(nic_t *nic,
1018 const nic_vlan_mask_t *vlan_mask)
1019{
1020 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1021
1022 fibril_mutex_lock(&e1000->rx_lock);
1023
1024 if (vlan_mask) {
1025 /*
1026 * Disable receiving, so that frame matching
1027 * partially written VLAN is not received.
1028 */
1029 bool rx_enabled = e1000_is_rx_enabled(e1000);
1030 if (rx_enabled)
1031 e1000_disable_rx(e1000);
1032
1033 for (unsigned int i = 0; i < NIC_VLAN_BITMAP_SIZE; i += 4) {
1034 uint32_t bitmap_part =
1035 ((uint32_t) vlan_mask->bitmap[i]) |
1036 (((uint32_t) vlan_mask->bitmap[i + 1]) << 8) |
1037 (((uint32_t) vlan_mask->bitmap[i + 2]) << 16) |
1038 (((uint32_t) vlan_mask->bitmap[i + 3]) << 24);
1039 E1000_REG_WRITE(e1000, E1000_VFTA_ARRAY(i / 4), bitmap_part);
1040 }
1041
1042 e1000_enable_vlan_filter(e1000);
1043 if (rx_enabled)
1044 e1000_enable_rx(e1000);
1045 } else
1046 e1000_disable_vlan_filter(e1000);
1047
1048 fibril_mutex_unlock(&e1000->rx_lock);
1049}
1050
1051/** Set VLAN mask
1052 *
1053 * @param device E1000 device
1054 * @param tag VLAN tag
1055 *
1056 * @return EOK
1057 * @return ENOTSUP
1058 *
1059 */
1060static errno_t e1000_vlan_set_tag(ddf_fun_t *fun, uint16_t tag, bool add,
1061 bool strip)
1062{
1063 /* VLAN CFI bit cannot be set */
1064 if (tag & VLANTAG_CFI)
1065 return ENOTSUP;
1066
1067 /*
1068 * CTRL.VME is neccessary for both strip and add
1069 * but CTRL.VME means stripping tags on receive.
1070 */
1071 if (!strip && add)
1072 return ENOTSUP;
1073
1074 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
1075
1076 e1000->vlan_tag = tag;
1077 e1000->vlan_tag_add = add;
1078
1079 fibril_mutex_lock(&e1000->ctrl_lock);
1080
1081 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1082 if (strip)
1083 ctrl |= CTRL_VME;
1084 else
1085 ctrl &= ~CTRL_VME;
1086
1087 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1088
1089 fibril_mutex_unlock(&e1000->ctrl_lock);
1090 return EOK;
1091}
1092
1093/** Fill receive descriptor with new empty buffer
1094 *
1095 * Store frame in e1000->rx_frame_phys
1096 *
1097 * @param nic NIC data stricture
1098 * @param offset Receive descriptor offset
1099 *
1100 */
1101static void e1000_fill_new_rx_descriptor(nic_t *nic, size_t offset)
1102{
1103 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1104
1105 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1106 (e1000->rx_ring_virt + offset * sizeof(e1000_rx_descriptor_t));
1107
1108 rx_descriptor->phys_addr = PTR_TO_U64(e1000->rx_frame_phys[offset]);
1109 rx_descriptor->length = 0;
1110 rx_descriptor->checksum = 0;
1111 rx_descriptor->status = 0;
1112 rx_descriptor->errors = 0;
1113 rx_descriptor->special = 0;
1114}
1115
1116/** Clear receive descriptor
1117 *
1118 * @param e1000 E1000 data
1119 * @param offset Receive descriptor offset
1120 *
1121 */
1122static void e1000_clear_rx_descriptor(e1000_t *e1000, unsigned int offset)
1123{
1124 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1125 (e1000->rx_ring_virt + offset * sizeof(e1000_rx_descriptor_t));
1126
1127 rx_descriptor->length = 0;
1128 rx_descriptor->checksum = 0;
1129 rx_descriptor->status = 0;
1130 rx_descriptor->errors = 0;
1131 rx_descriptor->special = 0;
1132}
1133
1134/** Clear receive descriptor
1135 *
1136 * @param nic NIC data
1137 * @param offset Receive descriptor offset
1138 *
1139 */
1140static void e1000_clear_tx_descriptor(nic_t *nic, unsigned int offset)
1141{
1142 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1143
1144 e1000_tx_descriptor_t *tx_descriptor = (e1000_tx_descriptor_t *)
1145 (e1000->tx_ring_virt + offset * sizeof(e1000_tx_descriptor_t));
1146
1147 tx_descriptor->phys_addr = 0;
1148 tx_descriptor->length = 0;
1149 tx_descriptor->checksum_offset = 0;
1150 tx_descriptor->command = 0;
1151 tx_descriptor->status = 0;
1152 tx_descriptor->checksum_start_field = 0;
1153 tx_descriptor->special = 0;
1154}
1155
1156/** Increment tail pointer for receive or transmit ring
1157 *
1158 * @param tail Old Tail
1159 * @param descriptors_count Ring length
1160 *
1161 * @return New tail
1162 *
1163 */
1164static uint32_t e1000_inc_tail(uint32_t tail, uint32_t descriptors_count)
1165{
1166 if (tail + 1 == descriptors_count)
1167 return 0;
1168 else
1169 return tail + 1;
1170}
1171
1172/** Receive frames
1173 *
1174 * @param nic NIC data
1175 *
1176 */
1177static void e1000_receive_frames(nic_t *nic)
1178{
1179 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1180
1181 fibril_mutex_lock(&e1000->rx_lock);
1182
1183 uint32_t *tail_addr = E1000_REG_ADDR(e1000, E1000_RDT);
1184 uint32_t next_tail = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1185
1186 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1187 (e1000->rx_ring_virt + next_tail * sizeof(e1000_rx_descriptor_t));
1188
1189 while (rx_descriptor->status & 0x01) {
1190 uint32_t frame_size = rx_descriptor->length - E1000_CRC_SIZE;
1191
1192 nic_frame_t *frame = nic_alloc_frame(nic, frame_size);
1193 if (frame != NULL) {
1194 memcpy(frame->data, e1000->rx_frame_virt[next_tail], frame_size);
1195
1196 nic_received_frame(nic, frame);
1197 } else {
1198 ddf_msg(LVL_ERROR, "Memory allocation failed. Frame dropped.");
1199 }
1200
1201 e1000_fill_new_rx_descriptor(nic, next_tail);
1202
1203 *tail_addr = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1204 next_tail = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1205
1206 rx_descriptor = (e1000_rx_descriptor_t *)
1207 (e1000->rx_ring_virt + next_tail * sizeof(e1000_rx_descriptor_t));
1208 }
1209
1210 fibril_mutex_unlock(&e1000->rx_lock);
1211}
1212
1213/** Enable E1000 interupts
1214 *
1215 * @param e1000 E1000 data structure
1216 *
1217 */
1218static void e1000_enable_interrupts(e1000_t *e1000)
1219{
1220 E1000_REG_WRITE(e1000, E1000_IMS, ICR_RXT0);
1221}
1222
1223/** Disable E1000 interupts
1224 *
1225 * @param e1000 E1000 data structure
1226 *
1227 */
1228static void e1000_disable_interrupts(e1000_t *e1000)
1229{
1230 E1000_REG_WRITE(e1000, E1000_IMS, 0);
1231}
1232
1233/** Interrupt handler implementation
1234 *
1235 * This function is called from e1000_interrupt_handler()
1236 * and e1000_poll()
1237 *
1238 * @param nic NIC data
1239 * @param icr ICR register value
1240 *
1241 */
1242static void e1000_interrupt_handler_impl(nic_t *nic, uint32_t icr)
1243{
1244 if (icr & ICR_RXT0)
1245 e1000_receive_frames(nic);
1246}
1247
1248/** Handle device interrupt
1249 *
1250 * @param icall IPC call structure
1251 * @param arg Argument (nic_t *)
1252 *
1253 */
1254static void e1000_interrupt_handler(ipc_call_t *icall, void *arg)
1255{
1256 uint32_t icr = (uint32_t) ipc_get_arg2(icall);
1257 nic_t *nic = (nic_t *)arg;
1258 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1259
1260 e1000_interrupt_handler_impl(nic, icr);
1261 e1000_enable_interrupts(e1000);
1262}
1263
1264/** Register interrupt handler for the card in the system
1265 *
1266 * Note: The global irq_reg_mutex is locked because of work with global
1267 * structure.
1268 *
1269 * @param nic Driver data
1270 *
1271 * @param[out] handle IRQ capability handle if the handler was registered
1272 *
1273 * @return An error code otherwise
1274 *
1275 */
1276static errno_t e1000_register_int_handler(nic_t *nic,
1277 cap_irq_handle_t *handle)
1278{
1279 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1280
1281 /* Lock the mutex in whole driver while working with global structure */
1282 fibril_mutex_lock(&irq_reg_mutex);
1283
1284 e1000_irq_code.ranges[0].base = (uintptr_t) e1000->reg_base_phys;
1285 e1000_irq_code.cmds[0].addr = e1000->reg_base_phys + E1000_ICR;
1286 e1000_irq_code.cmds[3].addr = e1000->reg_base_phys + E1000_IMC;
1287
1288 errno_t rc = register_interrupt_handler(nic_get_ddf_dev(nic), e1000->irq,
1289 e1000_interrupt_handler, (void *)nic, &e1000_irq_code, handle);
1290
1291 fibril_mutex_unlock(&irq_reg_mutex);
1292 return rc;
1293}
1294
1295/** Force receiving all frames in the receive buffer
1296 *
1297 * @param nic NIC data
1298 *
1299 */
1300static void e1000_poll(nic_t *nic)
1301{
1302 assert(nic);
1303
1304 e1000_t *e1000 = nic_get_specific(nic);
1305 assert(e1000);
1306
1307 uint32_t icr = E1000_REG_READ(e1000, E1000_ICR);
1308 e1000_interrupt_handler_impl(nic, icr);
1309}
1310
1311/** Calculates ITR register interrupt from timespec structure
1312 *
1313 * @param period Period
1314 *
1315 */
1316static uint16_t e1000_calculate_itr_interval(const struct timespec *period)
1317{
1318 // TODO: use also tv_sec
1319 return e1000_calculate_itr_interval_from_usecs(NSEC2USEC(period->tv_nsec));
1320}
1321
1322/** Set polling mode
1323 *
1324 * @param device Device to set
1325 * @param mode Mode to set
1326 * @param period Period for NIC_POLL_PERIODIC
1327 *
1328 * @return EOK if succeed
1329 * @return ENOTSUP if the mode is not supported
1330 *
1331 */
1332static errno_t e1000_poll_mode_change(nic_t *nic, nic_poll_mode_t mode,
1333 const struct timespec *period)
1334{
1335 assert(nic);
1336
1337 e1000_t *e1000 = nic_get_specific(nic);
1338 assert(e1000);
1339
1340 switch (mode) {
1341 case NIC_POLL_IMMEDIATE:
1342 E1000_REG_WRITE(e1000, E1000_ITR, 0);
1343 e1000_enable_interrupts(e1000);
1344 break;
1345 case NIC_POLL_ON_DEMAND:
1346 e1000_disable_interrupts(e1000);
1347 break;
1348 case NIC_POLL_PERIODIC:
1349 assert(period);
1350 uint16_t itr_interval = e1000_calculate_itr_interval(period);
1351 E1000_REG_WRITE(e1000, E1000_ITR, (uint32_t) itr_interval);
1352 e1000_enable_interrupts(e1000);
1353 break;
1354 default:
1355 return ENOTSUP;
1356 }
1357
1358 return EOK;
1359}
1360
1361/** Initialize receive registers
1362 *
1363 * @param e1000 E1000 data structure
1364 *
1365 */
1366static void e1000_initialize_rx_registers(e1000_t *e1000)
1367{
1368 E1000_REG_WRITE(e1000, E1000_RDLEN, E1000_RX_FRAME_COUNT * 16);
1369 E1000_REG_WRITE(e1000, E1000_RDH, 0);
1370
1371 /* It is not posible to let HW use all descriptors */
1372 E1000_REG_WRITE(e1000, E1000_RDT, E1000_RX_FRAME_COUNT - 1);
1373
1374 /* Set Broadcast Enable Bit */
1375 E1000_REG_WRITE(e1000, E1000_RCTL, RCTL_BAM);
1376}
1377
1378/** Initialize receive structure
1379 *
1380 * @param nic NIC data
1381 *
1382 * @return EOK if succeed
1383 * @return An error code otherwise
1384 *
1385 */
1386static errno_t e1000_initialize_rx_structure(nic_t *nic)
1387{
1388 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1389 fibril_mutex_lock(&e1000->rx_lock);
1390
1391 e1000->rx_ring_virt = AS_AREA_ANY;
1392 errno_t rc = dmamem_map_anonymous(
1393 E1000_RX_FRAME_COUNT * sizeof(e1000_rx_descriptor_t),
1394 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0,
1395 &e1000->rx_ring_phys, &e1000->rx_ring_virt);
1396 if (rc != EOK)
1397 return rc;
1398
1399 E1000_REG_WRITE(e1000, E1000_RDBAH,
1400 (uint32_t) (PTR_TO_U64(e1000->rx_ring_phys) >> 32));
1401 E1000_REG_WRITE(e1000, E1000_RDBAL,
1402 (uint32_t) PTR_TO_U64(e1000->rx_ring_phys));
1403
1404 e1000->rx_frame_phys = (uintptr_t *)
1405 calloc(E1000_RX_FRAME_COUNT, sizeof(uintptr_t));
1406 e1000->rx_frame_virt =
1407 calloc(E1000_RX_FRAME_COUNT, sizeof(void *));
1408 if ((e1000->rx_frame_phys == NULL) || (e1000->rx_frame_virt == NULL)) {
1409 rc = ENOMEM;
1410 goto error;
1411 }
1412
1413 for (size_t i = 0; i < E1000_RX_FRAME_COUNT; i++) {
1414 uintptr_t frame_phys;
1415 void *frame_virt = AS_AREA_ANY;
1416
1417 rc = dmamem_map_anonymous(E1000_MAX_SEND_FRAME_SIZE,
1418 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0,
1419 &frame_phys, &frame_virt);
1420 if (rc != EOK)
1421 goto error;
1422
1423 e1000->rx_frame_phys[i] = frame_phys;
1424 e1000->rx_frame_virt[i] = frame_virt;
1425 }
1426
1427 /* Write descriptor */
1428 for (size_t i = 0; i < E1000_RX_FRAME_COUNT; i++)
1429 e1000_fill_new_rx_descriptor(nic, i);
1430
1431 e1000_initialize_rx_registers(e1000);
1432
1433 fibril_mutex_unlock(&e1000->rx_lock);
1434 return EOK;
1435
1436error:
1437 for (size_t i = 0; i < E1000_RX_FRAME_COUNT; i++) {
1438 if (e1000->rx_frame_virt[i] != NULL) {
1439 dmamem_unmap_anonymous(e1000->rx_frame_virt[i]);
1440 e1000->rx_frame_phys[i] = 0;
1441 e1000->rx_frame_virt[i] = NULL;
1442 }
1443 }
1444
1445 if (e1000->rx_frame_phys != NULL) {
1446 free(e1000->rx_frame_phys);
1447 e1000->rx_frame_phys = NULL;
1448 }
1449
1450 if (e1000->rx_frame_virt != NULL) {
1451 free(e1000->rx_frame_virt);
1452 e1000->rx_frame_virt = NULL;
1453 }
1454
1455 return rc;
1456}
1457
1458/** Uninitialize receive structure
1459 *
1460 * @param nic NIC data
1461 *
1462 */
1463static void e1000_uninitialize_rx_structure(nic_t *nic)
1464{
1465 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1466
1467 /* Write descriptor */
1468 for (unsigned int offset = 0; offset < E1000_RX_FRAME_COUNT; offset++) {
1469 dmamem_unmap_anonymous(e1000->rx_frame_virt[offset]);
1470 e1000->rx_frame_phys[offset] = 0;
1471 e1000->rx_frame_virt[offset] = NULL;
1472 }
1473
1474 free(e1000->rx_frame_virt);
1475
1476 e1000->rx_frame_phys = NULL;
1477 e1000->rx_frame_virt = NULL;
1478
1479 dmamem_unmap_anonymous(e1000->rx_ring_virt);
1480}
1481
1482/** Clear receive descriptor ring
1483 *
1484 * @param e1000 E1000 data
1485 *
1486 */
1487static void e1000_clear_rx_ring(e1000_t *e1000)
1488{
1489 /* Write descriptor */
1490 for (unsigned int offset = 0;
1491 offset < E1000_RX_FRAME_COUNT;
1492 offset++)
1493 e1000_clear_rx_descriptor(e1000, offset);
1494}
1495
1496/** Initialize filters
1497 *
1498 * @param e1000 E1000 data
1499 *
1500 */
1501static void e1000_initialize_filters(e1000_t *e1000)
1502{
1503 /* Initialize address filter */
1504 e1000->unicast_ra_count = 0;
1505 e1000->multicast_ra_count = 0;
1506 e1000_clear_unicast_receive_addresses(e1000);
1507}
1508
1509/** Initialize VLAN
1510 *
1511 * @param e1000 E1000 data
1512 *
1513 */
1514static void e1000_initialize_vlan(e1000_t *e1000)
1515{
1516 e1000->vlan_tag_add = false;
1517}
1518
1519/** Fill MAC address from EEPROM to RA[0] register
1520 *
1521 * @param e1000 E1000 data
1522 *
1523 */
1524static void e1000_fill_mac_from_eeprom(e1000_t *e1000)
1525{
1526 /* MAC address from eeprom to RA[0] */
1527 nic_address_t address;
1528 e1000_eeprom_get_address(e1000, &address);
1529 e1000_write_receive_address(e1000, 0, &address, true);
1530}
1531
1532/** Initialize other registers
1533 *
1534 * @param dev E1000 data.
1535 *
1536 * @return EOK if succeed
1537 * @return An error code otherwise
1538 *
1539 */
1540static void e1000_initialize_registers(e1000_t *e1000)
1541{
1542 E1000_REG_WRITE(e1000, E1000_ITR,
1543 e1000_calculate_itr_interval_from_usecs(
1544 E1000_DEFAULT_INTERRUPT_INTERVAL_USEC));
1545 E1000_REG_WRITE(e1000, E1000_FCAH, 0);
1546 E1000_REG_WRITE(e1000, E1000_FCAL, 0);
1547 E1000_REG_WRITE(e1000, E1000_FCT, 0);
1548 E1000_REG_WRITE(e1000, E1000_FCTTV, 0);
1549 E1000_REG_WRITE(e1000, E1000_VET, VET_VALUE);
1550 E1000_REG_WRITE(e1000, E1000_CTRL, CTRL_ASDE);
1551}
1552
1553/** Initialize transmit registers
1554 *
1555 * @param e1000 E1000 data.
1556 *
1557 */
1558static void e1000_initialize_tx_registers(e1000_t *e1000)
1559{
1560 E1000_REG_WRITE(e1000, E1000_TDLEN, E1000_TX_FRAME_COUNT * 16);
1561 E1000_REG_WRITE(e1000, E1000_TDH, 0);
1562 E1000_REG_WRITE(e1000, E1000_TDT, 0);
1563
1564 E1000_REG_WRITE(e1000, E1000_TIPG,
1565 10 << TIPG_IPGT_SHIFT |
1566 8 << TIPG_IPGR1_SHIFT |
1567 6 << TIPG_IPGR2_SHIFT);
1568
1569 E1000_REG_WRITE(e1000, E1000_TCTL,
1570 0x0F << TCTL_CT_SHIFT /* Collision Threshold */ |
1571 0x40 << TCTL_COLD_SHIFT /* Collision Distance */ |
1572 TCTL_PSP /* Pad Short Packets */);
1573}
1574
1575/** Initialize transmit structure
1576 *
1577 * @param e1000 E1000 data.
1578 *
1579 */
1580static errno_t e1000_initialize_tx_structure(e1000_t *e1000)
1581{
1582 size_t i;
1583
1584 fibril_mutex_lock(&e1000->tx_lock);
1585
1586 e1000->tx_ring_phys = 0;
1587 e1000->tx_ring_virt = AS_AREA_ANY;
1588
1589 e1000->tx_frame_phys = NULL;
1590 e1000->tx_frame_virt = NULL;
1591
1592 errno_t rc = dmamem_map_anonymous(
1593 E1000_TX_FRAME_COUNT * sizeof(e1000_tx_descriptor_t),
1594 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0,
1595 &e1000->tx_ring_phys, &e1000->tx_ring_virt);
1596 if (rc != EOK)
1597 goto error;
1598
1599 memset(e1000->tx_ring_virt, 0,
1600 E1000_TX_FRAME_COUNT * sizeof(e1000_tx_descriptor_t));
1601
1602 e1000->tx_frame_phys = (uintptr_t *)
1603 calloc(E1000_TX_FRAME_COUNT, sizeof(uintptr_t));
1604 e1000->tx_frame_virt =
1605 calloc(E1000_TX_FRAME_COUNT, sizeof(void *));
1606
1607 if ((e1000->tx_frame_phys == NULL) || (e1000->tx_frame_virt == NULL)) {
1608 rc = ENOMEM;
1609 goto error;
1610 }
1611
1612 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1613 e1000->tx_frame_virt[i] = AS_AREA_ANY;
1614 rc = dmamem_map_anonymous(E1000_MAX_SEND_FRAME_SIZE,
1615 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE,
1616 0, &e1000->tx_frame_phys[i], &e1000->tx_frame_virt[i]);
1617 if (rc != EOK)
1618 goto error;
1619 }
1620
1621 E1000_REG_WRITE(e1000, E1000_TDBAH,
1622 (uint32_t) (PTR_TO_U64(e1000->tx_ring_phys) >> 32));
1623 E1000_REG_WRITE(e1000, E1000_TDBAL,
1624 (uint32_t) PTR_TO_U64(e1000->tx_ring_phys));
1625
1626 e1000_initialize_tx_registers(e1000);
1627
1628 fibril_mutex_unlock(&e1000->tx_lock);
1629 return EOK;
1630
1631error:
1632 if (e1000->tx_ring_virt != NULL) {
1633 dmamem_unmap_anonymous(e1000->tx_ring_virt);
1634 e1000->tx_ring_virt = NULL;
1635 }
1636
1637 if ((e1000->tx_frame_phys != NULL) && (e1000->tx_frame_virt != NULL)) {
1638 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1639 if (e1000->tx_frame_virt[i] != NULL) {
1640 dmamem_unmap_anonymous(e1000->tx_frame_virt[i]);
1641 e1000->tx_frame_phys[i] = 0;
1642 e1000->tx_frame_virt[i] = NULL;
1643 }
1644 }
1645 }
1646
1647 if (e1000->tx_frame_phys != NULL) {
1648 free(e1000->tx_frame_phys);
1649 e1000->tx_frame_phys = NULL;
1650 }
1651
1652 if (e1000->tx_frame_virt != NULL) {
1653 free(e1000->tx_frame_virt);
1654 e1000->tx_frame_virt = NULL;
1655 }
1656
1657 return rc;
1658}
1659
1660/** Uninitialize transmit structure
1661 *
1662 * @param nic NIC data
1663 *
1664 */
1665static void e1000_uninitialize_tx_structure(e1000_t *e1000)
1666{
1667 size_t i;
1668
1669 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1670 dmamem_unmap_anonymous(e1000->tx_frame_virt[i]);
1671 e1000->tx_frame_phys[i] = 0;
1672 e1000->tx_frame_virt[i] = NULL;
1673 }
1674
1675 if (e1000->tx_frame_phys != NULL) {
1676 free(e1000->tx_frame_phys);
1677 e1000->tx_frame_phys = NULL;
1678 }
1679
1680 if (e1000->tx_frame_virt != NULL) {
1681 free(e1000->tx_frame_virt);
1682 e1000->tx_frame_virt = NULL;
1683 }
1684
1685 dmamem_unmap_anonymous(e1000->tx_ring_virt);
1686}
1687
1688/** Clear transmit descriptor ring
1689 *
1690 * @param nic NIC data
1691 *
1692 */
1693static void e1000_clear_tx_ring(nic_t *nic)
1694{
1695 /* Write descriptor */
1696 for (unsigned int offset = 0;
1697 offset < E1000_TX_FRAME_COUNT;
1698 offset++)
1699 e1000_clear_tx_descriptor(nic, offset);
1700}
1701
1702/** Enable transmit
1703 *
1704 * @param e1000 E1000 data
1705 *
1706 */
1707static void e1000_enable_tx(e1000_t *e1000)
1708{
1709 /* Set Transmit Enable Bit */
1710 E1000_REG_WRITE(e1000, E1000_TCTL,
1711 E1000_REG_READ(e1000, E1000_TCTL) | (TCTL_EN));
1712}
1713
1714/** Disable transmit
1715 *
1716 * @param e1000 E1000 data
1717 *
1718 */
1719static void e1000_disable_tx(e1000_t *e1000)
1720{
1721 /* Clear Transmit Enable Bit */
1722 E1000_REG_WRITE(e1000, E1000_TCTL,
1723 E1000_REG_READ(e1000, E1000_TCTL) & ~(TCTL_EN));
1724}
1725
1726/** Reset E1000 device
1727 *
1728 * @param e1000 The E1000 data
1729 *
1730 */
1731static errno_t e1000_reset(nic_t *nic)
1732{
1733 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1734
1735 E1000_REG_WRITE(e1000, E1000_CTRL, CTRL_RST);
1736
1737 /* Wait for the reset */
1738 fibril_usleep(20);
1739
1740 /* check if RST_BIT cleared */
1741 if (E1000_REG_READ(e1000, E1000_CTRL) & (CTRL_RST))
1742 return EINVAL;
1743
1744 e1000_initialize_registers(e1000);
1745 e1000_initialize_rx_registers(e1000);
1746 e1000_initialize_tx_registers(e1000);
1747 e1000_fill_mac_from_eeprom(e1000);
1748 e1000_initialize_filters(e1000);
1749 e1000_initialize_vlan(e1000);
1750
1751 return EOK;
1752}
1753
1754/** Activate the device to receive and transmit frames
1755 *
1756 * @param nic NIC driver data
1757 *
1758 * @return EOK if activated successfully
1759 * @return Error code otherwise
1760 *
1761 */
1762static errno_t e1000_on_activating(nic_t *nic)
1763{
1764 assert(nic);
1765
1766 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1767
1768 fibril_mutex_lock(&e1000->rx_lock);
1769 fibril_mutex_lock(&e1000->tx_lock);
1770 fibril_mutex_lock(&e1000->ctrl_lock);
1771
1772 e1000_enable_interrupts(e1000);
1773
1774 errno_t rc = hw_res_enable_interrupt(e1000->parent_sess, e1000->irq);
1775 if (rc != EOK) {
1776 e1000_disable_interrupts(e1000);
1777 fibril_mutex_unlock(&e1000->ctrl_lock);
1778 fibril_mutex_unlock(&e1000->tx_lock);
1779 fibril_mutex_unlock(&e1000->rx_lock);
1780 return rc;
1781 }
1782
1783 e1000_clear_rx_ring(e1000);
1784 e1000_enable_rx(e1000);
1785
1786 e1000_clear_tx_ring(nic);
1787 e1000_enable_tx(e1000);
1788
1789 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1790 ctrl |= CTRL_SLU;
1791 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1792
1793 fibril_mutex_unlock(&e1000->ctrl_lock);
1794 fibril_mutex_unlock(&e1000->tx_lock);
1795 fibril_mutex_unlock(&e1000->rx_lock);
1796
1797 return EOK;
1798}
1799
1800/** Callback for NIC_STATE_DOWN change
1801 *
1802 * @param nic NIC driver data
1803 *
1804 * @return EOK if succeed
1805 * @return Error code otherwise
1806 *
1807 */
1808static errno_t e1000_on_down_unlocked(nic_t *nic)
1809{
1810 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1811
1812 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1813 ctrl &= ~CTRL_SLU;
1814 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1815
1816 e1000_disable_tx(e1000);
1817 e1000_disable_rx(e1000);
1818
1819 hw_res_disable_interrupt(e1000->parent_sess, e1000->irq);
1820 e1000_disable_interrupts(e1000);
1821
1822 /*
1823 * Wait for the for the end of all data
1824 * transfers to descriptors.
1825 */
1826 fibril_usleep(100);
1827
1828 return EOK;
1829}
1830
1831/** Callback for NIC_STATE_DOWN change
1832 *
1833 * @param nic NIC driver data
1834 *
1835 * @return EOK if succeed
1836 * @return Error code otherwise
1837 *
1838 */
1839static errno_t e1000_on_down(nic_t *nic)
1840{
1841 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1842
1843 fibril_mutex_lock(&e1000->rx_lock);
1844 fibril_mutex_lock(&e1000->tx_lock);
1845 fibril_mutex_lock(&e1000->ctrl_lock);
1846
1847 errno_t rc = e1000_on_down_unlocked(nic);
1848
1849 fibril_mutex_unlock(&e1000->ctrl_lock);
1850 fibril_mutex_unlock(&e1000->tx_lock);
1851 fibril_mutex_unlock(&e1000->rx_lock);
1852
1853 return rc;
1854}
1855
1856/** Callback for NIC_STATE_STOPPED change
1857 *
1858 * @param nic NIC driver data
1859 *
1860 * @return EOK if succeed
1861 * @return Error code otherwise
1862 *
1863 */
1864static errno_t e1000_on_stopping(nic_t *nic)
1865{
1866 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1867
1868 fibril_mutex_lock(&e1000->rx_lock);
1869 fibril_mutex_lock(&e1000->tx_lock);
1870 fibril_mutex_lock(&e1000->ctrl_lock);
1871
1872 errno_t rc = e1000_on_down_unlocked(nic);
1873 if (rc == EOK)
1874 rc = e1000_reset(nic);
1875
1876 fibril_mutex_unlock(&e1000->ctrl_lock);
1877 fibril_mutex_unlock(&e1000->tx_lock);
1878 fibril_mutex_unlock(&e1000->rx_lock);
1879
1880 return rc;
1881}
1882
1883/** Create driver data structure
1884 *
1885 * @return Intialized device data structure or NULL
1886 *
1887 */
1888static e1000_t *e1000_create_dev_data(ddf_dev_t *dev)
1889{
1890 nic_t *nic = nic_create_and_bind(dev);
1891 if (!nic)
1892 return NULL;
1893
1894 e1000_t *e1000 = malloc(sizeof(e1000_t));
1895 if (!e1000) {
1896 nic_unbind_and_destroy(dev);
1897 return NULL;
1898 }
1899
1900 memset(e1000, 0, sizeof(e1000_t));
1901 e1000->dev = dev;
1902
1903 nic_set_specific(nic, e1000);
1904 nic_set_send_frame_handler(nic, e1000_send_frame);
1905 nic_set_state_change_handlers(nic, e1000_on_activating,
1906 e1000_on_down, e1000_on_stopping);
1907 nic_set_filtering_change_handlers(nic,
1908 e1000_on_unicast_mode_change, e1000_on_multicast_mode_change,
1909 e1000_on_broadcast_mode_change, NULL, e1000_on_vlan_mask_change);
1910 nic_set_poll_handlers(nic, e1000_poll_mode_change, e1000_poll);
1911
1912 fibril_mutex_initialize(&e1000->ctrl_lock);
1913 fibril_mutex_initialize(&e1000->rx_lock);
1914 fibril_mutex_initialize(&e1000->tx_lock);
1915 fibril_mutex_initialize(&e1000->eeprom_lock);
1916
1917 return e1000;
1918}
1919
1920/** Delete driver data structure
1921 *
1922 * @param data E1000 device data structure
1923 *
1924 */
1925static void e1000_delete_dev_data(ddf_dev_t *dev)
1926{
1927 assert(dev);
1928
1929 if (ddf_dev_data_get(dev) != NULL)
1930 nic_unbind_and_destroy(dev);
1931}
1932
1933/** Clean up the E1000 device structure.
1934 *
1935 * @param dev Device structure.
1936 *
1937 */
1938static void e1000_dev_cleanup(ddf_dev_t *dev)
1939{
1940 assert(dev);
1941
1942 e1000_delete_dev_data(dev);
1943}
1944
1945/** Fill the irq and io_addr part of device data structure
1946 *
1947 * The hw_resources must be obtained before calling this function
1948 *
1949 * @param dev Device structure
1950 * @param hw_resources Hardware resources obtained from the parent device
1951 *
1952 * @return EOK if succeed
1953 * @return An error code otherwise
1954 *
1955 */
1956static errno_t e1000_fill_resource_info(ddf_dev_t *dev,
1957 const hw_res_list_parsed_t *hw_resources)
1958{
1959 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
1960
1961 if (hw_resources->irqs.count != 1)
1962 return EINVAL;
1963
1964 e1000->irq = hw_resources->irqs.irqs[0];
1965 e1000->reg_base_phys =
1966 MEMADDR_TO_PTR(RNGABS(hw_resources->mem_ranges.ranges[0]));
1967
1968 return EOK;
1969}
1970
1971/** Obtain information about hardware resources of the device
1972 *
1973 * The device must be connected to the parent
1974 *
1975 * @param dev Device structure
1976 *
1977 * @return EOK if succeed
1978 * @return An error code otherwise
1979 *
1980 */
1981static errno_t e1000_get_resource_info(ddf_dev_t *dev)
1982{
1983 assert(dev != NULL);
1984 assert(NIC_DATA_DEV(dev) != NULL);
1985
1986 hw_res_list_parsed_t hw_res_parsed;
1987 hw_res_list_parsed_init(&hw_res_parsed);
1988
1989 /* Get hw resources form parent driver */
1990 errno_t rc = nic_get_resources(NIC_DATA_DEV(dev), &hw_res_parsed);
1991 if (rc != EOK)
1992 return rc;
1993
1994 /* Fill resources information to the device */
1995 rc = e1000_fill_resource_info(dev, &hw_res_parsed);
1996 hw_res_list_parsed_clean(&hw_res_parsed);
1997
1998 return rc;
1999}
2000
2001/** Initialize the E1000 device structure
2002 *
2003 * @param dev Device information
2004 *
2005 * @return EOK if succeed
2006 * @return An error code otherwise
2007 *
2008 */
2009static errno_t e1000_device_initialize(ddf_dev_t *dev)
2010{
2011 /* Allocate driver data for the device. */
2012 e1000_t *e1000 = e1000_create_dev_data(dev);
2013 if (e1000 == NULL) {
2014 ddf_msg(LVL_ERROR, "Unable to allocate device softstate");
2015 return ENOMEM;
2016 }
2017
2018 e1000->parent_sess = ddf_dev_parent_sess_get(dev);
2019 if (e1000->parent_sess == NULL) {
2020 ddf_msg(LVL_ERROR, "Failed connecting parent device.");
2021 return EIO;
2022 }
2023
2024 /* Obtain and fill hardware resources info */
2025 errno_t rc = e1000_get_resource_info(dev);
2026 if (rc != EOK) {
2027 ddf_msg(LVL_ERROR, "Cannot obtain hardware resources");
2028 e1000_dev_cleanup(dev);
2029 return rc;
2030 }
2031
2032 uint16_t device_id;
2033 rc = pci_config_space_read_16(ddf_dev_parent_sess_get(dev), PCI_DEVICE_ID,
2034 &device_id);
2035 if (rc != EOK) {
2036 ddf_msg(LVL_ERROR, "Cannot access PCI configuration space");
2037 e1000_dev_cleanup(dev);
2038 return rc;
2039 }
2040
2041 e1000_board_t board;
2042 switch (device_id) {
2043 case 0x100e:
2044 case 0x1015:
2045 case 0x1016:
2046 case 0x1017:
2047 board = E1000_82540;
2048 break;
2049 case 0x1013:
2050 case 0x1018:
2051 case 0x1078:
2052 board = E1000_82541;
2053 break;
2054 case 0x1076:
2055 case 0x1077:
2056 case 0x107c:
2057 board = E1000_82541REV2;
2058 break;
2059 case 0x100f:
2060 case 0x1011:
2061 case 0x1026:
2062 case 0x1027:
2063 case 0x1028:
2064 board = E1000_82545;
2065 break;
2066 case 0x1010:
2067 case 0x1012:
2068 case 0x101d:
2069 case 0x1079:
2070 case 0x107a:
2071 case 0x107b:
2072 board = E1000_82546;
2073 break;
2074 case 0x1019:
2075 case 0x101a:
2076 board = E1000_82547;
2077 break;
2078 case 0x10b9:
2079 board = E1000_82572;
2080 break;
2081 case 0x1096:
2082 board = E1000_80003ES2;
2083 break;
2084 default:
2085 ddf_msg(LVL_ERROR, "Device not supported (%#" PRIx16 ")",
2086 device_id);
2087 e1000_dev_cleanup(dev);
2088 return ENOTSUP;
2089 }
2090
2091 switch (board) {
2092 case E1000_82540:
2093 case E1000_82541:
2094 case E1000_82541REV2:
2095 case E1000_82545:
2096 case E1000_82546:
2097 e1000->info.eerd_start = 0x01;
2098 e1000->info.eerd_done = 0x10;
2099 e1000->info.eerd_address_offset = 8;
2100 e1000->info.eerd_data_offset = 16;
2101 break;
2102 case E1000_82547:
2103 case E1000_82572:
2104 case E1000_80003ES2:
2105 e1000->info.eerd_start = 0x01;
2106 e1000->info.eerd_done = 0x02;
2107 e1000->info.eerd_address_offset = 2;
2108 e1000->info.eerd_data_offset = 16;
2109 break;
2110 }
2111
2112 return EOK;
2113}
2114
2115/** Enable the I/O ports of the device.
2116 *
2117 * @param dev E1000 device.
2118 *
2119 * @return EOK if successed
2120 * @return An error code otherwise
2121 *
2122 */
2123static errno_t e1000_pio_enable(ddf_dev_t *dev)
2124{
2125 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
2126
2127 errno_t rc = pio_enable(e1000->reg_base_phys, 8 * PAGE_SIZE,
2128 &e1000->reg_base_virt);
2129 if (rc != EOK)
2130 return EADDRNOTAVAIL;
2131
2132 return EOK;
2133}
2134
2135/** Probe and initialize the newly added device.
2136 *
2137 * @param dev E1000 device.
2138 *
2139 */
2140errno_t e1000_dev_add(ddf_dev_t *dev)
2141{
2142 ddf_fun_t *fun;
2143
2144 /* Initialize device structure for E1000 */
2145 errno_t rc = e1000_device_initialize(dev);
2146 if (rc != EOK)
2147 return rc;
2148
2149 /* Device initialization */
2150 nic_t *nic = ddf_dev_data_get(dev);
2151 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2152
2153 /* Map registers */
2154 rc = e1000_pio_enable(dev);
2155 if (rc != EOK)
2156 goto err_destroy;
2157
2158 e1000_initialize_registers(e1000);
2159 rc = e1000_initialize_tx_structure(e1000);
2160 if (rc != EOK)
2161 goto err_pio;
2162
2163 fibril_mutex_lock(&e1000->rx_lock);
2164
2165 e1000_fill_mac_from_eeprom(e1000);
2166 e1000_initialize_filters(e1000);
2167
2168 fibril_mutex_unlock(&e1000->rx_lock);
2169
2170 e1000_initialize_vlan(e1000);
2171
2172 fun = ddf_fun_create(nic_get_ddf_dev(nic), fun_exposed, "port0");
2173 if (fun == NULL)
2174 goto err_tx_structure;
2175 nic_set_ddf_fun(nic, fun);
2176 ddf_fun_set_ops(fun, &e1000_dev_ops);
2177
2178 cap_irq_handle_t irq_handle;
2179 rc = e1000_register_int_handler(nic, &irq_handle);
2180 if (rc != EOK) {
2181 goto err_fun_create;
2182 }
2183
2184 rc = e1000_initialize_rx_structure(nic);
2185 if (rc != EOK)
2186 goto err_irq;
2187
2188 nic_address_t e1000_address;
2189 e1000_get_address(e1000, &e1000_address);
2190 rc = nic_report_address(nic, &e1000_address);
2191 if (rc != EOK)
2192 goto err_rx_structure;
2193
2194 struct timespec period;
2195 period.tv_sec = 0;
2196 period.tv_nsec = USEC2NSEC(E1000_DEFAULT_INTERRUPT_INTERVAL_USEC);
2197 rc = nic_report_poll_mode(nic, NIC_POLL_PERIODIC, &period);
2198 if (rc != EOK)
2199 goto err_rx_structure;
2200
2201 rc = ddf_fun_bind(fun);
2202 if (rc != EOK)
2203 goto err_fun_bind;
2204
2205 rc = nic_fun_add_to_cats(fun);
2206 if (rc != EOK) {
2207 ddf_msg(LVL_ERROR, "Failed adding function to categories");
2208 ddf_fun_unbind(fun);
2209 return rc;
2210 }
2211 return EOK;
2212
2213err_fun_bind:
2214err_rx_structure:
2215 e1000_uninitialize_rx_structure(nic);
2216err_irq:
2217 unregister_interrupt_handler(dev, irq_handle);
2218err_fun_create:
2219 ddf_fun_destroy(fun);
2220 nic_set_ddf_fun(nic, NULL);
2221err_tx_structure:
2222 e1000_uninitialize_tx_structure(e1000);
2223err_pio:
2224 // TODO: e1000_pio_disable(dev);
2225err_destroy:
2226 e1000_dev_cleanup(dev);
2227 return rc;
2228}
2229
2230/** Quiesce E1000 device.
2231 *
2232 * @param dev E1000 device.
2233 *
2234 */
2235errno_t e1000_dev_quiesce(ddf_dev_t *dev)
2236{
2237 nic_t *nic = ddf_dev_data_get(dev);
2238 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2239 errno_t rc;
2240
2241 ddf_msg(LVL_DEBUG, "e1000_dev_quiesce()");
2242
2243 e1000_disable_interrupts(e1000);
2244 rc = e1000_reset(nic);
2245 if (rc != EOK)
2246 ddf_msg(LVL_ERROR, "e1000_dev_quiesce failed");
2247 return rc;
2248}
2249
2250/** Read 16-bit value from EEPROM of E1000 adapter
2251 *
2252 * Read using the EERD register.
2253 *
2254 * @param device E1000 device
2255 * @param eeprom_address 8-bit EEPROM address
2256 *
2257 * @return 16-bit value from EEPROM
2258 *
2259 */
2260static uint16_t e1000_eeprom_read(e1000_t *e1000, uint8_t eeprom_address)
2261{
2262 fibril_mutex_lock(&e1000->eeprom_lock);
2263
2264 /* Write address and START bit to EERD register */
2265 uint32_t write_data = e1000->info.eerd_start |
2266 (((uint32_t) eeprom_address) <<
2267 e1000->info.eerd_address_offset);
2268 E1000_REG_WRITE(e1000, E1000_EERD, write_data);
2269
2270 uint32_t eerd = E1000_REG_READ(e1000, E1000_EERD);
2271 while ((eerd & e1000->info.eerd_done) == 0) {
2272 fibril_usleep(1);
2273 eerd = E1000_REG_READ(e1000, E1000_EERD);
2274 }
2275
2276 fibril_mutex_unlock(&e1000->eeprom_lock);
2277
2278 return (uint16_t) (eerd >> e1000->info.eerd_data_offset);
2279}
2280
2281/** Get MAC address of the E1000 adapter
2282 *
2283 * @param device E1000 device
2284 * @param address Place to store the address
2285 * @param max_len Maximal addresss length to store
2286 *
2287 * @return EOK if succeed
2288 * @return An error code otherwise
2289 *
2290 */
2291static errno_t e1000_get_address(e1000_t *e1000, nic_address_t *address)
2292{
2293 fibril_mutex_lock(&e1000->rx_lock);
2294
2295 uint8_t *mac0_dest = (uint8_t *) address->address;
2296 uint8_t *mac1_dest = (uint8_t *) address->address + 1;
2297 uint8_t *mac2_dest = (uint8_t *) address->address + 2;
2298 uint8_t *mac3_dest = (uint8_t *) address->address + 3;
2299 uint8_t *mac4_dest = (uint8_t *) address->address + 4;
2300 uint8_t *mac5_dest = (uint8_t *) address->address + 5;
2301
2302 uint32_t rah = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
2303 uint32_t ral = E1000_REG_READ(e1000, E1000_RAL_ARRAY(0));
2304
2305 *mac0_dest = (uint8_t) ral;
2306 *mac1_dest = (uint8_t) (ral >> 8);
2307 *mac2_dest = (uint8_t) (ral >> 16);
2308 *mac3_dest = (uint8_t) (ral >> 24);
2309 *mac4_dest = (uint8_t) rah;
2310 *mac5_dest = (uint8_t) (rah >> 8);
2311
2312 fibril_mutex_unlock(&e1000->rx_lock);
2313 return EOK;
2314}
2315
2316/** Set card MAC address
2317 *
2318 * @param device E1000 device
2319 * @param address Address
2320 *
2321 * @return EOK if succeed
2322 * @return An error code otherwise
2323 */
2324static errno_t e1000_set_addr(ddf_fun_t *fun, const nic_address_t *addr)
2325{
2326 nic_t *nic = NIC_DATA_FUN(fun);
2327 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2328
2329 fibril_mutex_lock(&e1000->rx_lock);
2330 fibril_mutex_lock(&e1000->tx_lock);
2331
2332 errno_t rc = nic_report_address(nic, addr);
2333 if (rc == EOK)
2334 e1000_write_receive_address(e1000, 0, addr, false);
2335
2336 fibril_mutex_unlock(&e1000->tx_lock);
2337 fibril_mutex_unlock(&e1000->rx_lock);
2338
2339 return rc;
2340}
2341
2342static void e1000_eeprom_get_address(e1000_t *e1000,
2343 nic_address_t *address)
2344{
2345 uint16_t *mac0_dest = (uint16_t *) address->address;
2346 uint16_t *mac2_dest = (uint16_t *) (address->address + 2);
2347 uint16_t *mac4_dest = (uint16_t *) (address->address + 4);
2348
2349 *mac0_dest = e1000_eeprom_read(e1000, 0);
2350 *mac2_dest = e1000_eeprom_read(e1000, 1);
2351 *mac4_dest = e1000_eeprom_read(e1000, 2);
2352}
2353
2354/** Send frame
2355 *
2356 * @param nic NIC driver data structure
2357 * @param data Frame data
2358 * @param size Frame size in bytes
2359 *
2360 * @return EOK if succeed
2361 * @return Error code in the case of error
2362 *
2363 */
2364static void e1000_send_frame(nic_t *nic, void *data, size_t size)
2365{
2366 assert(nic);
2367
2368 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2369 fibril_mutex_lock(&e1000->tx_lock);
2370
2371 uint32_t tdt = E1000_REG_READ(e1000, E1000_TDT);
2372 e1000_tx_descriptor_t *tx_descriptor_addr = (e1000_tx_descriptor_t *)
2373 (e1000->tx_ring_virt + tdt * sizeof(e1000_tx_descriptor_t));
2374
2375 bool descriptor_available = false;
2376
2377 /* Descriptor never used */
2378 if (tx_descriptor_addr->length == 0)
2379 descriptor_available = true;
2380
2381 /* Descriptor done */
2382 if (tx_descriptor_addr->status & TXDESCRIPTOR_STATUS_DD)
2383 descriptor_available = true;
2384
2385 if (!descriptor_available) {
2386 /* Frame lost */
2387 fibril_mutex_unlock(&e1000->tx_lock);
2388 return;
2389 }
2390
2391 memcpy(e1000->tx_frame_virt[tdt], data, size);
2392 tx_descriptor_addr->phys_addr = PTR_TO_U64(e1000->tx_frame_phys[tdt]);
2393 tx_descriptor_addr->length = size;
2394
2395 /*
2396 * Report status to STATUS.DD (descriptor done),
2397 * add ethernet CRC, end of packet.
2398 */
2399 tx_descriptor_addr->command = TXDESCRIPTOR_COMMAND_RS |
2400 TXDESCRIPTOR_COMMAND_IFCS |
2401 TXDESCRIPTOR_COMMAND_EOP;
2402
2403 tx_descriptor_addr->checksum_offset = 0;
2404 tx_descriptor_addr->status = 0;
2405 if (e1000->vlan_tag_add) {
2406 tx_descriptor_addr->special = e1000->vlan_tag;
2407 tx_descriptor_addr->command |= TXDESCRIPTOR_COMMAND_VLE;
2408 } else
2409 tx_descriptor_addr->special = 0;
2410
2411 tx_descriptor_addr->checksum_start_field = 0;
2412
2413 tdt++;
2414 if (tdt == E1000_TX_FRAME_COUNT)
2415 tdt = 0;
2416
2417 E1000_REG_WRITE(e1000, E1000_TDT, tdt);
2418
2419 fibril_mutex_unlock(&e1000->tx_lock);
2420}
2421
2422int main(void)
2423{
2424 printf("%s: HelenOS E1000 network adapter driver\n", NAME);
2425
2426 if (nic_driver_init(NAME) != EOK)
2427 return 1;
2428
2429 nic_driver_implement(&e1000_driver_ops, &e1000_dev_ops,
2430 &e1000_nic_iface);
2431
2432 ddf_log_init(NAME);
2433 return ddf_driver_main(&e1000_driver);
2434}
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