source: mainline/uspace/drv/nic/e1k/e1k.c@ 9eb21d1

Last change on this file since 9eb21d1 was 9eb21d1, checked in by Nataliia Korop <n.corop08@…>, 10 months ago

pcapdump moved to nic_t struct
  • Property mode set to 100644
File size: 56.7 KB
Line 
1/*
2 * Copyright (c) 2011 Zdenek Bouska
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @file e1k.c
30 *
31 * Driver for Intel Pro/1000 8254x Family of Gigabit Ethernet Controllers
32 *
33 */
34
35#include <async.h>
36#include <assert.h>
37#include <stdio.h>
38#include <errno.h>
39#include <adt/list.h>
40#include <align.h>
41#include <byteorder.h>
42#include <as.h>
43#include <ddi.h>
44#include <ddf/log.h>
45#include <ddf/interrupt.h>
46#include <device/hw_res.h>
47#include <device/hw_res_parsed.h>
48#include <pci_dev_iface.h>
49#include <nic.h>
50#include <ops/nic.h>
51#include "e1k.h"
52
53#include "pcapdump_iface.h"
54#include "pcap_iface.h"
55#define NAME "e1k"
56
57#define E1000_DEFAULT_INTERRUPT_INTERVAL_USEC 250
58
59/* Must be power of 8 */
60#define E1000_RX_FRAME_COUNT 128
61#define E1000_TX_FRAME_COUNT 128
62
63#define E1000_RECEIVE_ADDRESS 16
64
65/** Maximum sending frame size */
66#define E1000_MAX_SEND_FRAME_SIZE 2048
67/** Maximum receiving frame size */
68#define E1000_MAX_RECEIVE_FRAME_SIZE 2048
69
70/** nic_driver_data_t* -> e1000_t* cast */
71#define DRIVER_DATA_NIC(nic) \
72 ((e1000_t *) nic_get_specific(nic))
73
74/** ddf_fun_t * -> nic_driver_data_t* cast */
75#define NIC_DATA_FUN(fun) \
76 ((nic_t *) ddf_dev_data_get(ddf_fun_get_dev(fun)))
77
78/** ddf_dev_t * -> nic_driver_data_t* cast */
79#define NIC_DATA_DEV(dev) \
80 ((nic_t *) ddf_dev_data_get(dev))
81
82/** ddf_dev_t * -> e1000_t* cast */
83#define DRIVER_DATA_DEV(dev) \
84 (DRIVER_DATA_NIC(NIC_DATA_DEV(dev)))
85
86/** ddf_fun_t * -> e1000_t* cast */
87#define DRIVER_DATA_FUN(fun) \
88 (DRIVER_DATA_NIC(NIC_DATA_FUN(fun)))
89
90/** Cast pointer to uint64_t
91 *
92 * @param ptr Pointer to cast
93 *
94 * @return The uint64_t pointer representation.
95 *
96 */
97#define PTR_TO_U64(ptr) ((uint64_t) ((uintptr_t) (ptr)))
98
99/** Cast the memaddr part to the void*
100 *
101 * @param memaddr The memaddr value
102 *
103 */
104#define MEMADDR_TO_PTR(memaddr) ((void *) ((size_t) (memaddr)))
105
106#define E1000_REG_BASE(e1000) \
107 ((e1000)->reg_base_virt)
108
109#define E1000_REG_ADDR(e1000, reg) \
110 ((uint32_t *) (E1000_REG_BASE(e1000) + reg))
111
112#define E1000_REG_READ(e1000, reg) \
113 (pio_read_32(E1000_REG_ADDR(e1000, reg)))
114
115#define E1000_REG_WRITE(e1000, reg, value) \
116 (pio_write_32(E1000_REG_ADDR(e1000, reg), value))
117
118/** E1000 device data */
119typedef struct {
120 /** DDF device */
121 ddf_dev_t *dev;
122 /** Parent session */
123 async_sess_t *parent_sess;
124 /** Device configuration */
125 e1000_info_t info;
126
127 /** Physical registers base address */
128 void *reg_base_phys;
129 /** Virtual registers base address */
130 void *reg_base_virt;
131
132 /** Physical tx ring address */
133 uintptr_t tx_ring_phys;
134 /** Virtual tx ring address */
135 void *tx_ring_virt;
136
137 /** Ring of TX frames, physical address */
138 uintptr_t *tx_frame_phys;
139 /** Ring of TX frames, virtual address */
140 void **tx_frame_virt;
141
142 /** Physical rx ring address */
143 uintptr_t rx_ring_phys;
144 /** Virtual rx ring address */
145 void *rx_ring_virt;
146
147 /** Ring of RX frames, physical address */
148 uintptr_t *rx_frame_phys;
149 /** Ring of RX frames, virtual address */
150 void **rx_frame_virt;
151
152 /** VLAN tag */
153 uint16_t vlan_tag;
154
155 /** Add VLAN tag to frame */
156 bool vlan_tag_add;
157
158 /** Used unicast Receive Address count */
159 unsigned int unicast_ra_count;
160
161 /** Used milticast Receive addrress count */
162 unsigned int multicast_ra_count;
163
164 /** The irq assigned */
165 int irq;
166
167 /** Lock for CTRL register */
168 fibril_mutex_t ctrl_lock;
169
170 /** Lock for receiver */
171 fibril_mutex_t rx_lock;
172
173 /** Lock for transmitter */
174 fibril_mutex_t tx_lock;
175
176 /** Lock for EEPROM access */
177 fibril_mutex_t eeprom_lock;
178
179
180} e1000_t;
181
182/** Global mutex for work with shared irq structure */
183FIBRIL_MUTEX_INITIALIZE(irq_reg_mutex);
184
185static errno_t e1000_get_address(e1000_t *, nic_address_t *);
186static void e1000_eeprom_get_address(e1000_t *, nic_address_t *);
187static errno_t e1000_set_addr(ddf_fun_t *, const nic_address_t *);
188
189static errno_t e1000_defective_get_mode(ddf_fun_t *, uint32_t *);
190static errno_t e1000_defective_set_mode(ddf_fun_t *, uint32_t);
191
192static errno_t e1000_get_cable_state(ddf_fun_t *, nic_cable_state_t *);
193static errno_t e1000_get_device_info(ddf_fun_t *, nic_device_info_t *);
194static errno_t e1000_get_operation_mode(ddf_fun_t *, int *,
195 nic_channel_mode_t *, nic_role_t *);
196static errno_t e1000_set_operation_mode(ddf_fun_t *, int,
197 nic_channel_mode_t, nic_role_t);
198static errno_t e1000_autoneg_enable(ddf_fun_t *, uint32_t);
199static errno_t e1000_autoneg_disable(ddf_fun_t *);
200static errno_t e1000_autoneg_restart(ddf_fun_t *);
201
202static errno_t e1000_vlan_set_tag(ddf_fun_t *, uint16_t, bool, bool);
203
204/** Network interface options for E1000 card driver */
205static nic_iface_t e1000_nic_iface;
206
207/** Network interface options for E1000 card driver */
208static nic_iface_t e1000_nic_iface = {
209 .set_address = &e1000_set_addr,
210 .get_device_info = &e1000_get_device_info,
211 .get_cable_state = &e1000_get_cable_state,
212 .get_operation_mode = &e1000_get_operation_mode,
213 .set_operation_mode = &e1000_set_operation_mode,
214 .autoneg_enable = &e1000_autoneg_enable,
215 .autoneg_disable = &e1000_autoneg_disable,
216 .autoneg_restart = &e1000_autoneg_restart,
217 .vlan_set_tag = &e1000_vlan_set_tag,
218 .defective_get_mode = &e1000_defective_get_mode,
219 .defective_set_mode = &e1000_defective_set_mode,
220};
221
222/** Basic device operations for E1000 driver */
223static ddf_dev_ops_t e1000_dev_ops;
224
225static errno_t e1000_dev_add(ddf_dev_t *);
226
227/** Basic driver operations for E1000 driver */
228static driver_ops_t e1000_driver_ops = {
229 .dev_add = e1000_dev_add
230};
231
232/** Driver structure for E1000 driver */
233static driver_t e1000_driver = {
234 .name = NAME,
235 .driver_ops = &e1000_driver_ops
236};
237
238/* The default implementation callbacks */
239static errno_t e1000_on_activating(nic_t *);
240static errno_t e1000_on_stopping(nic_t *);
241static void e1000_send_frame(nic_t *, void *, size_t);
242
243/** PIO ranges used in the IRQ code. */
244irq_pio_range_t e1000_irq_pio_ranges[] = {
245 {
246 .base = 0,
247 .size = PAGE_SIZE, /* XXX */
248 }
249};
250
251/** Commands to deal with interrupt
252 *
253 */
254irq_cmd_t e1000_irq_commands[] = {
255 {
256 /* Get the interrupt status */
257 .cmd = CMD_PIO_READ_32,
258 .addr = NULL,
259 .dstarg = 2
260 },
261 {
262 .cmd = CMD_AND,
263 .value = ICR_RXT0,
264 .srcarg = 2,
265 .dstarg = 1
266 },
267 {
268 .cmd = CMD_PREDICATE,
269 .value = 2,
270 .srcarg = 1
271 },
272 {
273 /* Disable interrupts until interrupt routine is finished */
274 .cmd = CMD_PIO_WRITE_32,
275 .addr = NULL,
276 .value = 0xffffffff
277 },
278 {
279 .cmd = CMD_ACCEPT
280 }
281};
282
283/** Interrupt code definition */
284irq_code_t e1000_irq_code = {
285 .rangecount = sizeof(e1000_irq_pio_ranges) /
286 sizeof(irq_pio_range_t),
287 .ranges = e1000_irq_pio_ranges,
288 .cmdcount = sizeof(e1000_irq_commands) / sizeof(irq_cmd_t),
289 .cmds = e1000_irq_commands
290};
291
292/** Get the device information
293 *
294 * @param dev NIC device
295 * @param info Information to fill
296 *
297 * @return EOK
298 *
299 */
300static errno_t e1000_get_device_info(ddf_fun_t *dev, nic_device_info_t *info)
301{
302 assert(dev);
303 assert(info);
304
305 memset(info, 0, sizeof(nic_device_info_t));
306
307 info->vendor_id = 0x8086;
308 str_cpy(info->vendor_name, NIC_VENDOR_MAX_LENGTH,
309 "Intel Corporation");
310 str_cpy(info->model_name, NIC_MODEL_MAX_LENGTH,
311 "Intel Pro");
312
313 info->ethernet_support[ETH_10M] = ETH_10BASE_T;
314 info->ethernet_support[ETH_100M] = ETH_100BASE_TX;
315 info->ethernet_support[ETH_1000M] = ETH_1000BASE_T;
316
317 return EOK;
318}
319
320/** Check the cable state
321 *
322 * @param[in] dev device
323 * @param[out] state state to fill
324 *
325 * @return EOK
326 *
327 */
328static errno_t e1000_get_cable_state(ddf_fun_t *fun, nic_cable_state_t *state)
329{
330 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
331 if (E1000_REG_READ(e1000, E1000_STATUS) & (STATUS_LU))
332 *state = NIC_CS_PLUGGED;
333 else
334 *state = NIC_CS_UNPLUGGED;
335
336 return EOK;
337}
338
339static uint16_t e1000_calculate_itr_interval_from_usecs(usec_t useconds)
340{
341 return useconds * 4;
342}
343
344/** Get operation mode of the device
345 *
346 */
347static errno_t e1000_get_operation_mode(ddf_fun_t *fun, int *speed,
348 nic_channel_mode_t *duplex, nic_role_t *role)
349{
350 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
351 uint32_t status = E1000_REG_READ(e1000, E1000_STATUS);
352
353 if (status & STATUS_FD)
354 *duplex = NIC_CM_FULL_DUPLEX;
355 else
356 *duplex = NIC_CM_HALF_DUPLEX;
357
358 uint32_t speed_bits =
359 (status >> STATUS_SPEED_SHIFT) & STATUS_SPEED_ALL;
360
361 if (speed_bits == STATUS_SPEED_10)
362 *speed = 10;
363 else if (speed_bits == STATUS_SPEED_100)
364 *speed = 100;
365 else if ((speed_bits == STATUS_SPEED_1000A) ||
366 (speed_bits == STATUS_SPEED_1000B))
367 *speed = 1000;
368
369 *role = NIC_ROLE_UNKNOWN;
370 return EOK;
371}
372
373static void e1000_link_restart(e1000_t *e1000)
374{
375 fibril_mutex_lock(&e1000->ctrl_lock);
376
377 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
378
379 if (ctrl & CTRL_SLU) {
380 ctrl &= ~(CTRL_SLU);
381 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
382 fibril_mutex_unlock(&e1000->ctrl_lock);
383
384 fibril_usleep(10);
385
386 fibril_mutex_lock(&e1000->ctrl_lock);
387 ctrl = E1000_REG_READ(e1000, E1000_CTRL);
388 ctrl |= CTRL_SLU;
389 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
390 }
391
392 fibril_mutex_unlock(&e1000->ctrl_lock);
393}
394
395/** Set operation mode of the device
396 *
397 */
398static errno_t e1000_set_operation_mode(ddf_fun_t *fun, int speed,
399 nic_channel_mode_t duplex, nic_role_t role)
400{
401 if ((speed != 10) && (speed != 100) && (speed != 1000))
402 return EINVAL;
403
404 if ((duplex != NIC_CM_HALF_DUPLEX) && (duplex != NIC_CM_FULL_DUPLEX))
405 return EINVAL;
406
407 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
408
409 fibril_mutex_lock(&e1000->ctrl_lock);
410 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
411
412 ctrl |= CTRL_FRCSPD;
413 ctrl |= CTRL_FRCDPLX;
414 ctrl &= ~(CTRL_ASDE);
415
416 if (duplex == NIC_CM_FULL_DUPLEX)
417 ctrl |= CTRL_FD;
418 else
419 ctrl &= ~(CTRL_FD);
420
421 ctrl &= ~(CTRL_SPEED_MASK);
422 if (speed == 1000)
423 ctrl |= CTRL_SPEED_1000 << CTRL_SPEED_SHIFT;
424 else if (speed == 100)
425 ctrl |= CTRL_SPEED_100 << CTRL_SPEED_SHIFT;
426 else
427 ctrl |= CTRL_SPEED_10 << CTRL_SPEED_SHIFT;
428
429 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
430
431 fibril_mutex_unlock(&e1000->ctrl_lock);
432
433 e1000_link_restart(e1000);
434
435 return EOK;
436}
437
438/** Enable auto-negotiation
439 *
440 * @param dev Device to update
441 * @param advertisement Ignored on E1000
442 *
443 * @return EOK if advertisement mode set successfully
444 *
445 */
446static errno_t e1000_autoneg_enable(ddf_fun_t *fun, uint32_t advertisement)
447{
448 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
449
450 fibril_mutex_lock(&e1000->ctrl_lock);
451
452 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
453
454 ctrl &= ~(CTRL_FRCSPD);
455 ctrl &= ~(CTRL_FRCDPLX);
456 ctrl |= CTRL_ASDE;
457
458 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
459
460 fibril_mutex_unlock(&e1000->ctrl_lock);
461
462 e1000_link_restart(e1000);
463
464 return EOK;
465}
466
467/** Disable auto-negotiation
468 *
469 * @param dev Device to update
470 *
471 * @return EOK
472 *
473 */
474static errno_t e1000_autoneg_disable(ddf_fun_t *fun)
475{
476 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
477
478 fibril_mutex_lock(&e1000->ctrl_lock);
479
480 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
481
482 ctrl |= CTRL_FRCSPD;
483 ctrl |= CTRL_FRCDPLX;
484 ctrl &= ~(CTRL_ASDE);
485
486 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
487
488 fibril_mutex_unlock(&e1000->ctrl_lock);
489
490 e1000_link_restart(e1000);
491
492 return EOK;
493}
494
495/** Restart auto-negotiation
496 *
497 * @param dev Device to update
498 *
499 * @return EOK if advertisement mode set successfully
500 *
501 */
502static errno_t e1000_autoneg_restart(ddf_fun_t *dev)
503{
504 return e1000_autoneg_enable(dev, 0);
505}
506
507/** Get state of acceptance of weird frames
508 *
509 * @param device Device to check
510 * @param[out] mode Current mode
511 *
512 */
513static errno_t e1000_defective_get_mode(ddf_fun_t *fun, uint32_t *mode)
514{
515 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
516
517 *mode = 0;
518 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
519 if (rctl & RCTL_SBP)
520 *mode = NIC_DEFECTIVE_BAD_CRC | NIC_DEFECTIVE_SHORT;
521
522 return EOK;
523}
524
525/** Set acceptance of weird frames
526 *
527 * @param device Device to update
528 * @param mode Mode to set
529 *
530 * @return ENOTSUP if the mode is not supported
531 * @return EOK of mode was set
532 *
533 */
534static errno_t e1000_defective_set_mode(ddf_fun_t *fun, uint32_t mode)
535{
536 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
537 errno_t rc = EOK;
538
539 fibril_mutex_lock(&e1000->rx_lock);
540
541 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
542 bool short_mode = (mode & NIC_DEFECTIVE_SHORT ? true : false);
543 bool bad_mode = (mode & NIC_DEFECTIVE_BAD_CRC ? true : false);
544
545 if (short_mode && bad_mode)
546 rctl |= RCTL_SBP;
547 else if ((!short_mode) && (!bad_mode))
548 rctl &= ~RCTL_SBP;
549 else
550 rc = ENOTSUP;
551
552 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
553
554 fibril_mutex_unlock(&e1000->rx_lock);
555 return rc;
556}
557
558/** Write receive address to RA registr
559 *
560 * @param e1000 E1000 data structure
561 * @param position RA register position
562 * @param address Ethernet address
563 * @param set_av_bit Set the Addtess Valid bit
564 *
565 */
566static void e1000_write_receive_address(e1000_t *e1000, unsigned int position,
567 const nic_address_t *address, bool set_av_bit)
568{
569 uint8_t *mac0 = (uint8_t *) address->address;
570 uint8_t *mac1 = (uint8_t *) address->address + 1;
571 uint8_t *mac2 = (uint8_t *) address->address + 2;
572 uint8_t *mac3 = (uint8_t *) address->address + 3;
573 uint8_t *mac4 = (uint8_t *) address->address + 4;
574 uint8_t *mac5 = (uint8_t *) address->address + 5;
575
576 uint32_t rah;
577 uint32_t ral;
578
579 ral = ((*mac3) << 24) | ((*mac2) << 16) | ((*mac1) << 8) | (*mac0);
580 rah = ((*mac5) << 8) | ((*mac4));
581
582 if (set_av_bit)
583 rah |= RAH_AV;
584 else
585 rah |= E1000_REG_READ(e1000, E1000_RAH_ARRAY(position)) & RAH_AV;
586
587 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(position), rah);
588 E1000_REG_WRITE(e1000, E1000_RAL_ARRAY(position), ral);
589}
590
591/** Disable receive address in RA registr
592 *
593 * Clear Address Valid bit
594 *
595 * @param e1000 E1000 data structure
596 * @param position RA register position
597 *
598 */
599static void e1000_disable_receive_address(e1000_t *e1000, unsigned int position)
600{
601 uint32_t rah = E1000_REG_READ(e1000, E1000_RAH_ARRAY(position));
602 rah = rah & ~RAH_AV;
603 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(position), rah);
604}
605
606/** Clear all unicast addresses from RA registers
607 *
608 * @param e1000 E1000 data structure
609 *
610 */
611static void e1000_clear_unicast_receive_addresses(e1000_t *e1000)
612{
613 for (unsigned int ra_num = 1;
614 ra_num <= e1000->unicast_ra_count;
615 ra_num++)
616 e1000_disable_receive_address(e1000, ra_num);
617
618 e1000->unicast_ra_count = 0;
619}
620
621/** Clear all multicast addresses from RA registers
622 *
623 * @param e1000 E1000 data structure
624 *
625 */
626static void e1000_clear_multicast_receive_addresses(e1000_t *e1000)
627{
628 unsigned int first_multicast_ra_num =
629 E1000_RECEIVE_ADDRESS - e1000->multicast_ra_count;
630
631 for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1;
632 ra_num >= first_multicast_ra_num;
633 ra_num--)
634 e1000_disable_receive_address(e1000, ra_num);
635
636 e1000->multicast_ra_count = 0;
637}
638
639/** Return receive address filter positions count usable for unicast
640 *
641 * @param e1000 E1000 data structure
642 *
643 * @return receive address filter positions count usable for unicast
644 *
645 */
646static unsigned int get_free_unicast_address_count(e1000_t *e1000)
647{
648 return E1000_RECEIVE_ADDRESS - 1 - e1000->multicast_ra_count;
649}
650
651/** Return receive address filter positions count usable for multicast
652 *
653 * @param e1000 E1000 data structure
654 *
655 * @return receive address filter positions count usable for multicast
656 *
657 */
658static unsigned int get_free_multicast_address_count(e1000_t *e1000)
659{
660 return E1000_RECEIVE_ADDRESS - 1 - e1000->unicast_ra_count;
661}
662
663/** Write unicast receive addresses to receive address filter registers
664 *
665 * @param e1000 E1000 data structure
666 * @param addr Pointer to address array
667 * @param addr_cnt Address array count
668 *
669 */
670static void e1000_add_unicast_receive_addresses(e1000_t *e1000,
671 const nic_address_t *addr, size_t addr_cnt)
672{
673 assert(addr_cnt <= get_free_unicast_address_count(e1000));
674
675 nic_address_t *addr_iterator = (nic_address_t *) addr;
676
677 /* ra_num = 0 is primary address */
678 for (unsigned int ra_num = 1;
679 ra_num <= addr_cnt;
680 ra_num++) {
681 e1000_write_receive_address(e1000, ra_num, addr_iterator, true);
682 addr_iterator++;
683 }
684}
685
686/** Write multicast receive addresses to receive address filter registers
687 *
688 * @param e1000 E1000 data structure
689 * @param addr Pointer to address array
690 * @param addr_cnt Address array count
691 *
692 */
693static void e1000_add_multicast_receive_addresses(e1000_t *e1000,
694 const nic_address_t *addr, size_t addr_cnt)
695{
696 assert(addr_cnt <= get_free_multicast_address_count(e1000));
697
698 nic_address_t *addr_iterator = (nic_address_t *) addr;
699
700 unsigned int first_multicast_ra_num = E1000_RECEIVE_ADDRESS - addr_cnt;
701 for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1;
702 ra_num >= first_multicast_ra_num;
703 ra_num--) {
704 e1000_write_receive_address(e1000, ra_num, addr_iterator, true);
705 addr_iterator++;
706 }
707}
708
709/** Disable receiving frames for default address
710 *
711 * @param e1000 E1000 data structure
712 *
713 */
714static void disable_ra0_address_filter(e1000_t *e1000)
715{
716 uint32_t rah0 = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
717 rah0 = rah0 & ~RAH_AV;
718 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(0), rah0);
719}
720
721/** Enable receiving frames for default address
722 *
723 * @param e1000 E1000 data structure
724 *
725 */
726static void enable_ra0_address_filter(e1000_t *e1000)
727{
728 uint32_t rah0 = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
729 rah0 = rah0 | RAH_AV;
730 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(0), rah0);
731}
732
733/** Disable unicast promiscuous mode
734 *
735 * @param e1000 E1000 data structure
736 *
737 */
738static void e1000_disable_unicast_promisc(e1000_t *e1000)
739{
740 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
741 rctl = rctl & ~RCTL_UPE;
742 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
743}
744
745/** Enable unicast promiscuous mode
746 *
747 * @param e1000 E1000 data structure
748 *
749 */
750static void e1000_enable_unicast_promisc(e1000_t *e1000)
751{
752 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
753 rctl = rctl | RCTL_UPE;
754 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
755}
756
757/** Disable multicast promiscuous mode
758 *
759 * @param e1000 E1000 data structure
760 *
761 */
762static void e1000_disable_multicast_promisc(e1000_t *e1000)
763{
764 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
765 rctl = rctl & ~RCTL_MPE;
766 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
767}
768
769/** Enable multicast promiscuous mode
770 *
771 * @param e1000 E1000 data structure
772 *
773 */
774static void e1000_enable_multicast_promisc(e1000_t *e1000)
775{
776 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
777 rctl = rctl | RCTL_MPE;
778 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
779}
780
781/** Enable accepting of broadcast frames
782 *
783 * @param e1000 E1000 data structure
784 *
785 */
786static void e1000_enable_broadcast_accept(e1000_t *e1000)
787{
788 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
789 rctl = rctl | RCTL_BAM;
790 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
791}
792
793/** Disable accepting of broadcast frames
794 *
795 * @param e1000 E1000 data structure
796 *
797 */
798static void e1000_disable_broadcast_accept(e1000_t *e1000)
799{
800 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
801 rctl = rctl & ~RCTL_BAM;
802 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
803}
804
805/** Enable VLAN filtering according to VFTA registers
806 *
807 * @param e1000 E1000 data structure
808 *
809 */
810static void e1000_enable_vlan_filter(e1000_t *e1000)
811{
812 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
813 rctl = rctl | RCTL_VFE;
814 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
815}
816
817/** Disable VLAN filtering
818 *
819 * @param e1000 E1000 data structure
820 *
821 */
822static void e1000_disable_vlan_filter(e1000_t *e1000)
823{
824 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
825 rctl = rctl & ~RCTL_VFE;
826 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
827}
828
829/** Set multicast frames acceptance mode
830 *
831 * @param nic NIC device to update
832 * @param mode Mode to set
833 * @param addr Address list (used in mode = NIC_MULTICAST_LIST)
834 * @param addr_cnt Length of address list (used in mode = NIC_MULTICAST_LIST)
835 *
836 * @return EOK
837 *
838 */
839static errno_t e1000_on_multicast_mode_change(nic_t *nic, nic_multicast_mode_t mode,
840 const nic_address_t *addr, size_t addr_cnt)
841{
842 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
843 errno_t rc = EOK;
844
845 fibril_mutex_lock(&e1000->rx_lock);
846
847 switch (mode) {
848 case NIC_MULTICAST_BLOCKED:
849 e1000_clear_multicast_receive_addresses(e1000);
850 e1000_disable_multicast_promisc(e1000);
851 nic_report_hw_filtering(nic, -1, 1, -1);
852 break;
853 case NIC_MULTICAST_LIST:
854 e1000_clear_multicast_receive_addresses(e1000);
855 if (addr_cnt > get_free_multicast_address_count(e1000)) {
856 /*
857 * Future work: fill MTA table
858 * Not strictly neccessary, it only saves some compares
859 * in the NIC library.
860 */
861 e1000_enable_multicast_promisc(e1000);
862 nic_report_hw_filtering(nic, -1, 0, -1);
863 } else {
864 e1000_disable_multicast_promisc(e1000);
865 e1000_add_multicast_receive_addresses(e1000, addr, addr_cnt);
866 nic_report_hw_filtering(nic, -1, 1, -1);
867 }
868 break;
869 case NIC_MULTICAST_PROMISC:
870 e1000_enable_multicast_promisc(e1000);
871 e1000_clear_multicast_receive_addresses(e1000);
872 nic_report_hw_filtering(nic, -1, 1, -1);
873 break;
874 default:
875 rc = ENOTSUP;
876 break;
877 }
878
879 fibril_mutex_unlock(&e1000->rx_lock);
880 return rc;
881}
882
883/** Set unicast frames acceptance mode
884 *
885 * @param nic NIC device to update
886 * @param mode Mode to set
887 * @param addr Address list (used in mode = NIC_MULTICAST_LIST)
888 * @param addr_cnt Length of address list (used in mode = NIC_MULTICAST_LIST)
889 *
890 * @return EOK
891 *
892 */
893static errno_t e1000_on_unicast_mode_change(nic_t *nic, nic_unicast_mode_t mode,
894 const nic_address_t *addr, size_t addr_cnt)
895{
896 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
897 errno_t rc = EOK;
898
899 fibril_mutex_lock(&e1000->rx_lock);
900
901 switch (mode) {
902 case NIC_UNICAST_BLOCKED:
903 disable_ra0_address_filter(e1000);
904 e1000_clear_unicast_receive_addresses(e1000);
905 e1000_disable_unicast_promisc(e1000);
906 nic_report_hw_filtering(nic, 1, -1, -1);
907 break;
908 case NIC_UNICAST_DEFAULT:
909 enable_ra0_address_filter(e1000);
910 e1000_clear_unicast_receive_addresses(e1000);
911 e1000_disable_unicast_promisc(e1000);
912 nic_report_hw_filtering(nic, 1, -1, -1);
913 break;
914 case NIC_UNICAST_LIST:
915 enable_ra0_address_filter(e1000);
916 e1000_clear_unicast_receive_addresses(e1000);
917 if (addr_cnt > get_free_unicast_address_count(e1000)) {
918 e1000_enable_unicast_promisc(e1000);
919 nic_report_hw_filtering(nic, 0, -1, -1);
920 } else {
921 e1000_disable_unicast_promisc(e1000);
922 e1000_add_unicast_receive_addresses(e1000, addr, addr_cnt);
923 nic_report_hw_filtering(nic, 1, -1, -1);
924 }
925 break;
926 case NIC_UNICAST_PROMISC:
927 e1000_enable_unicast_promisc(e1000);
928 enable_ra0_address_filter(e1000);
929 e1000_clear_unicast_receive_addresses(e1000);
930 nic_report_hw_filtering(nic, 1, -1, -1);
931 break;
932 default:
933 rc = ENOTSUP;
934 break;
935 }
936
937 fibril_mutex_unlock(&e1000->rx_lock);
938 return rc;
939}
940
941/** Set broadcast frames acceptance mode
942 *
943 * @param nic NIC device to update
944 * @param mode Mode to set
945 *
946 * @return EOK
947 *
948 */
949static errno_t e1000_on_broadcast_mode_change(nic_t *nic, nic_broadcast_mode_t mode)
950{
951 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
952 errno_t rc = EOK;
953
954 fibril_mutex_lock(&e1000->rx_lock);
955
956 switch (mode) {
957 case NIC_BROADCAST_BLOCKED:
958 e1000_disable_broadcast_accept(e1000);
959 break;
960 case NIC_BROADCAST_ACCEPTED:
961 e1000_enable_broadcast_accept(e1000);
962 break;
963 default:
964 rc = ENOTSUP;
965 break;
966 }
967
968 fibril_mutex_unlock(&e1000->rx_lock);
969 return rc;
970}
971
972/** Check if receiving is enabled
973 *
974 * @param e1000 E1000 data structure
975 *
976 * @return true if receiving is enabled
977 *
978 */
979static bool e1000_is_rx_enabled(e1000_t *e1000)
980{
981 if (E1000_REG_READ(e1000, E1000_RCTL) & (RCTL_EN))
982 return true;
983
984 return false;
985}
986
987/** Enable receiving
988 *
989 * @param e1000 E1000 data structure
990 *
991 */
992static void e1000_enable_rx(e1000_t *e1000)
993{
994 /* Set Receive Enable Bit */
995 E1000_REG_WRITE(e1000, E1000_RCTL,
996 E1000_REG_READ(e1000, E1000_RCTL) | (RCTL_EN));
997}
998
999/** Disable receiving
1000 *
1001 * @param e1000 E1000 data structure
1002 *
1003 */
1004static void e1000_disable_rx(e1000_t *e1000)
1005{
1006 /* Clear Receive Enable Bit */
1007 E1000_REG_WRITE(e1000, E1000_RCTL,
1008 E1000_REG_READ(e1000, E1000_RCTL) & ~(RCTL_EN));
1009}
1010
1011/** Set VLAN mask
1012 *
1013 * @param nic NIC device to update
1014 * @param vlan_mask VLAN mask
1015 *
1016 */
1017static void e1000_on_vlan_mask_change(nic_t *nic,
1018 const nic_vlan_mask_t *vlan_mask)
1019{
1020 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1021
1022 fibril_mutex_lock(&e1000->rx_lock);
1023
1024 if (vlan_mask) {
1025 /*
1026 * Disable receiving, so that frame matching
1027 * partially written VLAN is not received.
1028 */
1029 bool rx_enabled = e1000_is_rx_enabled(e1000);
1030 if (rx_enabled)
1031 e1000_disable_rx(e1000);
1032
1033 for (unsigned int i = 0; i < NIC_VLAN_BITMAP_SIZE; i += 4) {
1034 uint32_t bitmap_part =
1035 ((uint32_t) vlan_mask->bitmap[i]) |
1036 (((uint32_t) vlan_mask->bitmap[i + 1]) << 8) |
1037 (((uint32_t) vlan_mask->bitmap[i + 2]) << 16) |
1038 (((uint32_t) vlan_mask->bitmap[i + 3]) << 24);
1039 E1000_REG_WRITE(e1000, E1000_VFTA_ARRAY(i / 4), bitmap_part);
1040 }
1041
1042 e1000_enable_vlan_filter(e1000);
1043 if (rx_enabled)
1044 e1000_enable_rx(e1000);
1045 } else
1046 e1000_disable_vlan_filter(e1000);
1047
1048 fibril_mutex_unlock(&e1000->rx_lock);
1049}
1050
1051/** Set VLAN mask
1052 *
1053 * @param device E1000 device
1054 * @param tag VLAN tag
1055 *
1056 * @return EOK
1057 * @return ENOTSUP
1058 *
1059 */
1060static errno_t e1000_vlan_set_tag(ddf_fun_t *fun, uint16_t tag, bool add,
1061 bool strip)
1062{
1063 /* VLAN CFI bit cannot be set */
1064 if (tag & VLANTAG_CFI)
1065 return ENOTSUP;
1066
1067 /*
1068 * CTRL.VME is neccessary for both strip and add
1069 * but CTRL.VME means stripping tags on receive.
1070 */
1071 if (!strip && add)
1072 return ENOTSUP;
1073
1074 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
1075
1076 e1000->vlan_tag = tag;
1077 e1000->vlan_tag_add = add;
1078
1079 fibril_mutex_lock(&e1000->ctrl_lock);
1080
1081 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1082 if (strip)
1083 ctrl |= CTRL_VME;
1084 else
1085 ctrl &= ~CTRL_VME;
1086
1087 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1088
1089 fibril_mutex_unlock(&e1000->ctrl_lock);
1090 return EOK;
1091}
1092
1093/** Fill receive descriptor with new empty buffer
1094 *
1095 * Store frame in e1000->rx_frame_phys
1096 *
1097 * @param nic NIC data stricture
1098 * @param offset Receive descriptor offset
1099 *
1100 */
1101static void e1000_fill_new_rx_descriptor(nic_t *nic, size_t offset)
1102{
1103 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1104
1105 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1106 (e1000->rx_ring_virt + offset * sizeof(e1000_rx_descriptor_t));
1107
1108 rx_descriptor->phys_addr = PTR_TO_U64(e1000->rx_frame_phys[offset]);
1109 rx_descriptor->length = 0;
1110 rx_descriptor->checksum = 0;
1111 rx_descriptor->status = 0;
1112 rx_descriptor->errors = 0;
1113 rx_descriptor->special = 0;
1114}
1115
1116/** Clear receive descriptor
1117 *
1118 * @param e1000 E1000 data
1119 * @param offset Receive descriptor offset
1120 *
1121 */
1122static void e1000_clear_rx_descriptor(e1000_t *e1000, unsigned int offset)
1123{
1124 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1125 (e1000->rx_ring_virt + offset * sizeof(e1000_rx_descriptor_t));
1126
1127 rx_descriptor->length = 0;
1128 rx_descriptor->checksum = 0;
1129 rx_descriptor->status = 0;
1130 rx_descriptor->errors = 0;
1131 rx_descriptor->special = 0;
1132}
1133
1134/** Clear receive descriptor
1135 *
1136 * @param nic NIC data
1137 * @param offset Receive descriptor offset
1138 *
1139 */
1140static void e1000_clear_tx_descriptor(nic_t *nic, unsigned int offset)
1141{
1142 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1143
1144 e1000_tx_descriptor_t *tx_descriptor = (e1000_tx_descriptor_t *)
1145 (e1000->tx_ring_virt + offset * sizeof(e1000_tx_descriptor_t));
1146
1147 tx_descriptor->phys_addr = 0;
1148 tx_descriptor->length = 0;
1149 tx_descriptor->checksum_offset = 0;
1150 tx_descriptor->command = 0;
1151 tx_descriptor->status = 0;
1152 tx_descriptor->checksum_start_field = 0;
1153 tx_descriptor->special = 0;
1154}
1155
1156/** Increment tail pointer for receive or transmit ring
1157 *
1158 * @param tail Old Tail
1159 * @param descriptors_count Ring length
1160 *
1161 * @return New tail
1162 *
1163 */
1164static uint32_t e1000_inc_tail(uint32_t tail, uint32_t descriptors_count)
1165{
1166 if (tail + 1 == descriptors_count)
1167 return 0;
1168 else
1169 return tail + 1;
1170}
1171
1172/** Receive frames
1173 *
1174 * @param nic NIC data
1175 *
1176 */
1177static void e1000_receive_frames(nic_t *nic)
1178{
1179 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1180
1181 fibril_mutex_lock(&e1000->rx_lock);
1182
1183 uint32_t *tail_addr = E1000_REG_ADDR(e1000, E1000_RDT);
1184 uint32_t next_tail = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1185
1186 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1187 (e1000->rx_ring_virt + next_tail * sizeof(e1000_rx_descriptor_t));
1188
1189 while (rx_descriptor->status & 0x01) {
1190 uint32_t frame_size = rx_descriptor->length - E1000_CRC_SIZE;
1191
1192 nic_frame_t *frame = nic_alloc_frame(nic, frame_size);
1193 if (frame != NULL) {
1194 memcpy(frame->data, e1000->rx_frame_virt[next_tail], frame_size);
1195 pcapdump_packet(nic_get_pcap_iface(nic), frame->data, frame->size);
1196
1197 nic_received_frame(nic, frame);
1198 } else {
1199 ddf_msg(LVL_ERROR, "Memory allocation failed. Frame dropped.");
1200 }
1201
1202 e1000_fill_new_rx_descriptor(nic, next_tail);
1203
1204 *tail_addr = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1205 next_tail = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1206
1207 rx_descriptor = (e1000_rx_descriptor_t *)
1208 (e1000->rx_ring_virt + next_tail * sizeof(e1000_rx_descriptor_t));
1209 }
1210
1211 fibril_mutex_unlock(&e1000->rx_lock);
1212}
1213
1214/** Enable E1000 interupts
1215 *
1216 * @param e1000 E1000 data structure
1217 *
1218 */
1219static void e1000_enable_interrupts(e1000_t *e1000)
1220{
1221 E1000_REG_WRITE(e1000, E1000_IMS, ICR_RXT0);
1222}
1223
1224/** Disable E1000 interupts
1225 *
1226 * @param e1000 E1000 data structure
1227 *
1228 */
1229static void e1000_disable_interrupts(e1000_t *e1000)
1230{
1231 E1000_REG_WRITE(e1000, E1000_IMS, 0);
1232}
1233
1234/** Interrupt handler implementation
1235 *
1236 * This function is called from e1000_interrupt_handler()
1237 * and e1000_poll()
1238 *
1239 * @param nic NIC data
1240 * @param icr ICR register value
1241 *
1242 */
1243static void e1000_interrupt_handler_impl(nic_t *nic, uint32_t icr)
1244{
1245 if (icr & ICR_RXT0)
1246 e1000_receive_frames(nic);
1247}
1248
1249/** Handle device interrupt
1250 *
1251 * @param icall IPC call structure
1252 * @param arg Argument (nic_t *)
1253 *
1254 */
1255static void e1000_interrupt_handler(ipc_call_t *icall, void *arg)
1256{
1257 uint32_t icr = (uint32_t) ipc_get_arg2(icall);
1258 nic_t *nic = (nic_t *)arg;
1259 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1260
1261 e1000_interrupt_handler_impl(nic, icr);
1262 e1000_enable_interrupts(e1000);
1263}
1264
1265/** Register interrupt handler for the card in the system
1266 *
1267 * Note: The global irq_reg_mutex is locked because of work with global
1268 * structure.
1269 *
1270 * @param nic Driver data
1271 *
1272 * @param[out] handle IRQ capability handle if the handler was registered
1273 *
1274 * @return An error code otherwise
1275 *
1276 */
1277inline static errno_t e1000_register_int_handler(nic_t *nic,
1278 cap_irq_handle_t *handle)
1279{
1280 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1281
1282 /* Lock the mutex in whole driver while working with global structure */
1283 fibril_mutex_lock(&irq_reg_mutex);
1284
1285 e1000_irq_code.ranges[0].base = (uintptr_t) e1000->reg_base_phys;
1286 e1000_irq_code.cmds[0].addr = e1000->reg_base_phys + E1000_ICR;
1287 e1000_irq_code.cmds[3].addr = e1000->reg_base_phys + E1000_IMC;
1288
1289 errno_t rc = register_interrupt_handler(nic_get_ddf_dev(nic), e1000->irq,
1290 e1000_interrupt_handler, (void *)nic, &e1000_irq_code, handle);
1291
1292 fibril_mutex_unlock(&irq_reg_mutex);
1293 return rc;
1294}
1295
1296/** Force receiving all frames in the receive buffer
1297 *
1298 * @param nic NIC data
1299 *
1300 */
1301static void e1000_poll(nic_t *nic)
1302{
1303 assert(nic);
1304
1305 e1000_t *e1000 = nic_get_specific(nic);
1306 assert(e1000);
1307
1308 uint32_t icr = E1000_REG_READ(e1000, E1000_ICR);
1309 e1000_interrupt_handler_impl(nic, icr);
1310}
1311
1312/** Calculates ITR register interrupt from timespec structure
1313 *
1314 * @param period Period
1315 *
1316 */
1317static uint16_t e1000_calculate_itr_interval(const struct timespec *period)
1318{
1319 // TODO: use also tv_sec
1320 return e1000_calculate_itr_interval_from_usecs(NSEC2USEC(period->tv_nsec));
1321}
1322
1323/** Set polling mode
1324 *
1325 * @param device Device to set
1326 * @param mode Mode to set
1327 * @param period Period for NIC_POLL_PERIODIC
1328 *
1329 * @return EOK if succeed
1330 * @return ENOTSUP if the mode is not supported
1331 *
1332 */
1333static errno_t e1000_poll_mode_change(nic_t *nic, nic_poll_mode_t mode,
1334 const struct timespec *period)
1335{
1336 assert(nic);
1337
1338 e1000_t *e1000 = nic_get_specific(nic);
1339 assert(e1000);
1340
1341 switch (mode) {
1342 case NIC_POLL_IMMEDIATE:
1343 E1000_REG_WRITE(e1000, E1000_ITR, 0);
1344 e1000_enable_interrupts(e1000);
1345 break;
1346 case NIC_POLL_ON_DEMAND:
1347 e1000_disable_interrupts(e1000);
1348 break;
1349 case NIC_POLL_PERIODIC:
1350 assert(period);
1351 uint16_t itr_interval = e1000_calculate_itr_interval(period);
1352 E1000_REG_WRITE(e1000, E1000_ITR, (uint32_t) itr_interval);
1353 e1000_enable_interrupts(e1000);
1354 break;
1355 default:
1356 return ENOTSUP;
1357 }
1358
1359 return EOK;
1360}
1361
1362/** Initialize receive registers
1363 *
1364 * @param e1000 E1000 data structure
1365 *
1366 */
1367static void e1000_initialize_rx_registers(e1000_t *e1000)
1368{
1369 E1000_REG_WRITE(e1000, E1000_RDLEN, E1000_RX_FRAME_COUNT * 16);
1370 E1000_REG_WRITE(e1000, E1000_RDH, 0);
1371
1372 /* It is not posible to let HW use all descriptors */
1373 E1000_REG_WRITE(e1000, E1000_RDT, E1000_RX_FRAME_COUNT - 1);
1374
1375 /* Set Broadcast Enable Bit */
1376 E1000_REG_WRITE(e1000, E1000_RCTL, RCTL_BAM);
1377}
1378
1379/** Initialize receive structure
1380 *
1381 * @param nic NIC data
1382 *
1383 * @return EOK if succeed
1384 * @return An error code otherwise
1385 *
1386 */
1387static errno_t e1000_initialize_rx_structure(nic_t *nic)
1388{
1389 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1390 fibril_mutex_lock(&e1000->rx_lock);
1391
1392 e1000->rx_ring_virt = AS_AREA_ANY;
1393 errno_t rc = dmamem_map_anonymous(
1394 E1000_RX_FRAME_COUNT * sizeof(e1000_rx_descriptor_t),
1395 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0,
1396 &e1000->rx_ring_phys, &e1000->rx_ring_virt);
1397 if (rc != EOK)
1398 return rc;
1399
1400 E1000_REG_WRITE(e1000, E1000_RDBAH,
1401 (uint32_t) (PTR_TO_U64(e1000->rx_ring_phys) >> 32));
1402 E1000_REG_WRITE(e1000, E1000_RDBAL,
1403 (uint32_t) PTR_TO_U64(e1000->rx_ring_phys));
1404
1405 e1000->rx_frame_phys = (uintptr_t *)
1406 calloc(E1000_RX_FRAME_COUNT, sizeof(uintptr_t));
1407 e1000->rx_frame_virt =
1408 calloc(E1000_RX_FRAME_COUNT, sizeof(void *));
1409 if ((e1000->rx_frame_phys == NULL) || (e1000->rx_frame_virt == NULL)) {
1410 rc = ENOMEM;
1411 goto error;
1412 }
1413
1414 for (size_t i = 0; i < E1000_RX_FRAME_COUNT; i++) {
1415 uintptr_t frame_phys;
1416 void *frame_virt = AS_AREA_ANY;
1417
1418 rc = dmamem_map_anonymous(E1000_MAX_SEND_FRAME_SIZE,
1419 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0,
1420 &frame_phys, &frame_virt);
1421 if (rc != EOK)
1422 goto error;
1423
1424 e1000->rx_frame_phys[i] = frame_phys;
1425 e1000->rx_frame_virt[i] = frame_virt;
1426 }
1427
1428 /* Write descriptor */
1429 for (size_t i = 0; i < E1000_RX_FRAME_COUNT; i++)
1430 e1000_fill_new_rx_descriptor(nic, i);
1431
1432 e1000_initialize_rx_registers(e1000);
1433
1434 fibril_mutex_unlock(&e1000->rx_lock);
1435 return EOK;
1436
1437error:
1438 for (size_t i = 0; i < E1000_RX_FRAME_COUNT; i++) {
1439 if (e1000->rx_frame_virt[i] != NULL) {
1440 dmamem_unmap_anonymous(e1000->rx_frame_virt[i]);
1441 e1000->rx_frame_phys[i] = 0;
1442 e1000->rx_frame_virt[i] = NULL;
1443 }
1444 }
1445
1446 if (e1000->rx_frame_phys != NULL) {
1447 free(e1000->rx_frame_phys);
1448 e1000->rx_frame_phys = NULL;
1449 }
1450
1451 if (e1000->rx_frame_virt != NULL) {
1452 free(e1000->rx_frame_virt);
1453 e1000->rx_frame_virt = NULL;
1454 }
1455
1456 return rc;
1457}
1458
1459/** Uninitialize receive structure
1460 *
1461 * @param nic NIC data
1462 *
1463 */
1464static void e1000_uninitialize_rx_structure(nic_t *nic)
1465{
1466 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1467
1468 /* Write descriptor */
1469 for (unsigned int offset = 0; offset < E1000_RX_FRAME_COUNT; offset++) {
1470 dmamem_unmap_anonymous(e1000->rx_frame_virt[offset]);
1471 e1000->rx_frame_phys[offset] = 0;
1472 e1000->rx_frame_virt[offset] = NULL;
1473 }
1474
1475 free(e1000->rx_frame_virt);
1476
1477 e1000->rx_frame_phys = NULL;
1478 e1000->rx_frame_virt = NULL;
1479
1480 dmamem_unmap_anonymous(e1000->rx_ring_virt);
1481}
1482
1483/** Clear receive descriptor ring
1484 *
1485 * @param e1000 E1000 data
1486 *
1487 */
1488static void e1000_clear_rx_ring(e1000_t *e1000)
1489{
1490 /* Write descriptor */
1491 for (unsigned int offset = 0;
1492 offset < E1000_RX_FRAME_COUNT;
1493 offset++)
1494 e1000_clear_rx_descriptor(e1000, offset);
1495}
1496
1497/** Initialize filters
1498 *
1499 * @param e1000 E1000 data
1500 *
1501 */
1502static void e1000_initialize_filters(e1000_t *e1000)
1503{
1504 /* Initialize address filter */
1505 e1000->unicast_ra_count = 0;
1506 e1000->multicast_ra_count = 0;
1507 e1000_clear_unicast_receive_addresses(e1000);
1508}
1509
1510/** Initialize VLAN
1511 *
1512 * @param e1000 E1000 data
1513 *
1514 */
1515static void e1000_initialize_vlan(e1000_t *e1000)
1516{
1517 e1000->vlan_tag_add = false;
1518}
1519
1520/** Fill MAC address from EEPROM to RA[0] register
1521 *
1522 * @param e1000 E1000 data
1523 *
1524 */
1525static void e1000_fill_mac_from_eeprom(e1000_t *e1000)
1526{
1527 /* MAC address from eeprom to RA[0] */
1528 nic_address_t address;
1529 e1000_eeprom_get_address(e1000, &address);
1530 e1000_write_receive_address(e1000, 0, &address, true);
1531}
1532
1533/** Initialize other registers
1534 *
1535 * @param dev E1000 data.
1536 *
1537 * @return EOK if succeed
1538 * @return An error code otherwise
1539 *
1540 */
1541static void e1000_initialize_registers(e1000_t *e1000)
1542{
1543 E1000_REG_WRITE(e1000, E1000_ITR,
1544 e1000_calculate_itr_interval_from_usecs(
1545 E1000_DEFAULT_INTERRUPT_INTERVAL_USEC));
1546 E1000_REG_WRITE(e1000, E1000_FCAH, 0);
1547 E1000_REG_WRITE(e1000, E1000_FCAL, 0);
1548 E1000_REG_WRITE(e1000, E1000_FCT, 0);
1549 E1000_REG_WRITE(e1000, E1000_FCTTV, 0);
1550 E1000_REG_WRITE(e1000, E1000_VET, VET_VALUE);
1551 E1000_REG_WRITE(e1000, E1000_CTRL, CTRL_ASDE);
1552}
1553
1554/** Initialize transmit registers
1555 *
1556 * @param e1000 E1000 data.
1557 *
1558 */
1559static void e1000_initialize_tx_registers(e1000_t *e1000)
1560{
1561 E1000_REG_WRITE(e1000, E1000_TDLEN, E1000_TX_FRAME_COUNT * 16);
1562 E1000_REG_WRITE(e1000, E1000_TDH, 0);
1563 E1000_REG_WRITE(e1000, E1000_TDT, 0);
1564
1565 E1000_REG_WRITE(e1000, E1000_TIPG,
1566 10 << TIPG_IPGT_SHIFT |
1567 8 << TIPG_IPGR1_SHIFT |
1568 6 << TIPG_IPGR2_SHIFT);
1569
1570 E1000_REG_WRITE(e1000, E1000_TCTL,
1571 0x0F << TCTL_CT_SHIFT /* Collision Threshold */ |
1572 0x40 << TCTL_COLD_SHIFT /* Collision Distance */ |
1573 TCTL_PSP /* Pad Short Packets */);
1574}
1575
1576/** Initialize transmit structure
1577 *
1578 * @param e1000 E1000 data.
1579 *
1580 */
1581static errno_t e1000_initialize_tx_structure(e1000_t *e1000)
1582{
1583 size_t i;
1584
1585 fibril_mutex_lock(&e1000->tx_lock);
1586
1587 e1000->tx_ring_phys = 0;
1588 e1000->tx_ring_virt = AS_AREA_ANY;
1589
1590 e1000->tx_frame_phys = NULL;
1591 e1000->tx_frame_virt = NULL;
1592
1593 errno_t rc = dmamem_map_anonymous(
1594 E1000_TX_FRAME_COUNT * sizeof(e1000_tx_descriptor_t),
1595 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0,
1596 &e1000->tx_ring_phys, &e1000->tx_ring_virt);
1597 if (rc != EOK)
1598 goto error;
1599
1600 memset(e1000->tx_ring_virt, 0,
1601 E1000_TX_FRAME_COUNT * sizeof(e1000_tx_descriptor_t));
1602
1603 e1000->tx_frame_phys = (uintptr_t *)
1604 calloc(E1000_TX_FRAME_COUNT, sizeof(uintptr_t));
1605 e1000->tx_frame_virt =
1606 calloc(E1000_TX_FRAME_COUNT, sizeof(void *));
1607
1608 if ((e1000->tx_frame_phys == NULL) || (e1000->tx_frame_virt == NULL)) {
1609 rc = ENOMEM;
1610 goto error;
1611 }
1612
1613 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1614 e1000->tx_frame_virt[i] = AS_AREA_ANY;
1615 rc = dmamem_map_anonymous(E1000_MAX_SEND_FRAME_SIZE,
1616 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE,
1617 0, &e1000->tx_frame_phys[i], &e1000->tx_frame_virt[i]);
1618 if (rc != EOK)
1619 goto error;
1620 }
1621
1622 E1000_REG_WRITE(e1000, E1000_TDBAH,
1623 (uint32_t) (PTR_TO_U64(e1000->tx_ring_phys) >> 32));
1624 E1000_REG_WRITE(e1000, E1000_TDBAL,
1625 (uint32_t) PTR_TO_U64(e1000->tx_ring_phys));
1626
1627 e1000_initialize_tx_registers(e1000);
1628
1629 fibril_mutex_unlock(&e1000->tx_lock);
1630 return EOK;
1631
1632error:
1633 if (e1000->tx_ring_virt != NULL) {
1634 dmamem_unmap_anonymous(e1000->tx_ring_virt);
1635 e1000->tx_ring_virt = NULL;
1636 }
1637
1638 if ((e1000->tx_frame_phys != NULL) && (e1000->tx_frame_virt != NULL)) {
1639 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1640 if (e1000->tx_frame_virt[i] != NULL) {
1641 dmamem_unmap_anonymous(e1000->tx_frame_virt[i]);
1642 e1000->tx_frame_phys[i] = 0;
1643 e1000->tx_frame_virt[i] = NULL;
1644 }
1645 }
1646 }
1647
1648 if (e1000->tx_frame_phys != NULL) {
1649 free(e1000->tx_frame_phys);
1650 e1000->tx_frame_phys = NULL;
1651 }
1652
1653 if (e1000->tx_frame_virt != NULL) {
1654 free(e1000->tx_frame_virt);
1655 e1000->tx_frame_virt = NULL;
1656 }
1657
1658 return rc;
1659}
1660
1661/** Uninitialize transmit structure
1662 *
1663 * @param nic NIC data
1664 *
1665 */
1666static void e1000_uninitialize_tx_structure(e1000_t *e1000)
1667{
1668 size_t i;
1669
1670 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1671 dmamem_unmap_anonymous(e1000->tx_frame_virt[i]);
1672 e1000->tx_frame_phys[i] = 0;
1673 e1000->tx_frame_virt[i] = NULL;
1674 }
1675
1676 if (e1000->tx_frame_phys != NULL) {
1677 free(e1000->tx_frame_phys);
1678 e1000->tx_frame_phys = NULL;
1679 }
1680
1681 if (e1000->tx_frame_virt != NULL) {
1682 free(e1000->tx_frame_virt);
1683 e1000->tx_frame_virt = NULL;
1684 }
1685
1686 dmamem_unmap_anonymous(e1000->tx_ring_virt);
1687}
1688
1689/** Clear transmit descriptor ring
1690 *
1691 * @param nic NIC data
1692 *
1693 */
1694static void e1000_clear_tx_ring(nic_t *nic)
1695{
1696 /* Write descriptor */
1697 for (unsigned int offset = 0;
1698 offset < E1000_TX_FRAME_COUNT;
1699 offset++)
1700 e1000_clear_tx_descriptor(nic, offset);
1701}
1702
1703/** Enable transmit
1704 *
1705 * @param e1000 E1000 data
1706 *
1707 */
1708static void e1000_enable_tx(e1000_t *e1000)
1709{
1710 /* Set Transmit Enable Bit */
1711 E1000_REG_WRITE(e1000, E1000_TCTL,
1712 E1000_REG_READ(e1000, E1000_TCTL) | (TCTL_EN));
1713}
1714
1715/** Disable transmit
1716 *
1717 * @param e1000 E1000 data
1718 *
1719 */
1720static void e1000_disable_tx(e1000_t *e1000)
1721{
1722 /* Clear Transmit Enable Bit */
1723 E1000_REG_WRITE(e1000, E1000_TCTL,
1724 E1000_REG_READ(e1000, E1000_TCTL) & ~(TCTL_EN));
1725}
1726
1727/** Reset E1000 device
1728 *
1729 * @param e1000 The E1000 data
1730 *
1731 */
1732static errno_t e1000_reset(nic_t *nic)
1733{
1734 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1735
1736 E1000_REG_WRITE(e1000, E1000_CTRL, CTRL_RST);
1737
1738 /* Wait for the reset */
1739 fibril_usleep(20);
1740
1741 /* check if RST_BIT cleared */
1742 if (E1000_REG_READ(e1000, E1000_CTRL) & (CTRL_RST))
1743 return EINVAL;
1744
1745 e1000_initialize_registers(e1000);
1746 e1000_initialize_rx_registers(e1000);
1747 e1000_initialize_tx_registers(e1000);
1748 e1000_fill_mac_from_eeprom(e1000);
1749 e1000_initialize_filters(e1000);
1750 e1000_initialize_vlan(e1000);
1751
1752 return EOK;
1753}
1754
1755/** Activate the device to receive and transmit frames
1756 *
1757 * @param nic NIC driver data
1758 *
1759 * @return EOK if activated successfully
1760 * @return Error code otherwise
1761 *
1762 */
1763static errno_t e1000_on_activating(nic_t *nic)
1764{
1765 assert(nic);
1766
1767 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1768
1769 fibril_mutex_lock(&e1000->rx_lock);
1770 fibril_mutex_lock(&e1000->tx_lock);
1771 fibril_mutex_lock(&e1000->ctrl_lock);
1772
1773 e1000_enable_interrupts(e1000);
1774
1775 errno_t rc = hw_res_enable_interrupt(e1000->parent_sess, e1000->irq);
1776 if (rc != EOK) {
1777 e1000_disable_interrupts(e1000);
1778 fibril_mutex_unlock(&e1000->ctrl_lock);
1779 fibril_mutex_unlock(&e1000->tx_lock);
1780 fibril_mutex_unlock(&e1000->rx_lock);
1781 return rc;
1782 }
1783
1784 e1000_clear_rx_ring(e1000);
1785 e1000_enable_rx(e1000);
1786
1787 e1000_clear_tx_ring(nic);
1788 e1000_enable_tx(e1000);
1789
1790 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1791 ctrl |= CTRL_SLU;
1792 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1793
1794 fibril_mutex_unlock(&e1000->ctrl_lock);
1795 fibril_mutex_unlock(&e1000->tx_lock);
1796 fibril_mutex_unlock(&e1000->rx_lock);
1797
1798 return EOK;
1799}
1800
1801/** Callback for NIC_STATE_DOWN change
1802 *
1803 * @param nic NIC driver data
1804 *
1805 * @return EOK if succeed
1806 * @return Error code otherwise
1807 *
1808 */
1809static errno_t e1000_on_down_unlocked(nic_t *nic)
1810{
1811 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1812
1813 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1814 ctrl &= ~CTRL_SLU;
1815 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1816
1817 e1000_disable_tx(e1000);
1818 e1000_disable_rx(e1000);
1819
1820 hw_res_disable_interrupt(e1000->parent_sess, e1000->irq);
1821 e1000_disable_interrupts(e1000);
1822
1823 /*
1824 * Wait for the for the end of all data
1825 * transfers to descriptors.
1826 */
1827 fibril_usleep(100);
1828
1829 return EOK;
1830}
1831
1832/** Callback for NIC_STATE_DOWN change
1833 *
1834 * @param nic NIC driver data
1835 *
1836 * @return EOK if succeed
1837 * @return Error code otherwise
1838 *
1839 */
1840static errno_t e1000_on_down(nic_t *nic)
1841{
1842 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1843
1844 fibril_mutex_lock(&e1000->rx_lock);
1845 fibril_mutex_lock(&e1000->tx_lock);
1846 fibril_mutex_lock(&e1000->ctrl_lock);
1847
1848 errno_t rc = e1000_on_down_unlocked(nic);
1849
1850 fibril_mutex_unlock(&e1000->ctrl_lock);
1851 fibril_mutex_unlock(&e1000->tx_lock);
1852 fibril_mutex_unlock(&e1000->rx_lock);
1853
1854 return rc;
1855}
1856
1857/** Callback for NIC_STATE_STOPPED change
1858 *
1859 * @param nic NIC driver data
1860 *
1861 * @return EOK if succeed
1862 * @return Error code otherwise
1863 *
1864 */
1865static errno_t e1000_on_stopping(nic_t *nic)
1866{
1867 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1868
1869 fibril_mutex_lock(&e1000->rx_lock);
1870 fibril_mutex_lock(&e1000->tx_lock);
1871 fibril_mutex_lock(&e1000->ctrl_lock);
1872
1873 errno_t rc = e1000_on_down_unlocked(nic);
1874 if (rc == EOK)
1875 rc = e1000_reset(nic);
1876
1877 fibril_mutex_unlock(&e1000->ctrl_lock);
1878 fibril_mutex_unlock(&e1000->tx_lock);
1879 fibril_mutex_unlock(&e1000->rx_lock);
1880
1881 return rc;
1882}
1883
1884/** Create driver data structure
1885 *
1886 * @return Intialized device data structure or NULL
1887 *
1888 */
1889static e1000_t *e1000_create_dev_data(ddf_dev_t *dev)
1890{
1891 nic_t *nic = nic_create_and_bind(dev);
1892 if (!nic)
1893 return NULL;
1894
1895 e1000_t *e1000 = malloc(sizeof(e1000_t));
1896 if (!e1000) {
1897 nic_unbind_and_destroy(dev);
1898 return NULL;
1899 }
1900
1901 memset(e1000, 0, sizeof(e1000_t));
1902 e1000->dev = dev;
1903
1904 nic_set_specific(nic, e1000);
1905 nic_set_send_frame_handler(nic, e1000_send_frame);
1906 nic_set_state_change_handlers(nic, e1000_on_activating,
1907 e1000_on_down, e1000_on_stopping);
1908 nic_set_filtering_change_handlers(nic,
1909 e1000_on_unicast_mode_change, e1000_on_multicast_mode_change,
1910 e1000_on_broadcast_mode_change, NULL, e1000_on_vlan_mask_change);
1911 nic_set_poll_handlers(nic, e1000_poll_mode_change, e1000_poll);
1912
1913 fibril_mutex_initialize(&e1000->ctrl_lock);
1914 fibril_mutex_initialize(&e1000->rx_lock);
1915 fibril_mutex_initialize(&e1000->tx_lock);
1916 fibril_mutex_initialize(&e1000->eeprom_lock);
1917
1918 return e1000;
1919}
1920
1921/** Delete driver data structure
1922 *
1923 * @param data E1000 device data structure
1924 *
1925 */
1926inline static void e1000_delete_dev_data(ddf_dev_t *dev)
1927{
1928 assert(dev);
1929
1930 if (ddf_dev_data_get(dev) != NULL)
1931 nic_unbind_and_destroy(dev);
1932}
1933
1934/** Clean up the E1000 device structure.
1935 *
1936 * @param dev Device structure.
1937 *
1938 */
1939static void e1000_dev_cleanup(ddf_dev_t *dev)
1940{
1941 assert(dev);
1942
1943 e1000_delete_dev_data(dev);
1944}
1945
1946/** Fill the irq and io_addr part of device data structure
1947 *
1948 * The hw_resources must be obtained before calling this function
1949 *
1950 * @param dev Device structure
1951 * @param hw_resources Hardware resources obtained from the parent device
1952 *
1953 * @return EOK if succeed
1954 * @return An error code otherwise
1955 *
1956 */
1957static errno_t e1000_fill_resource_info(ddf_dev_t *dev,
1958 const hw_res_list_parsed_t *hw_resources)
1959{
1960 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
1961
1962 if (hw_resources->irqs.count != 1)
1963 return EINVAL;
1964
1965 e1000->irq = hw_resources->irqs.irqs[0];
1966 e1000->reg_base_phys =
1967 MEMADDR_TO_PTR(RNGABS(hw_resources->mem_ranges.ranges[0]));
1968
1969 return EOK;
1970}
1971
1972/** Obtain information about hardware resources of the device
1973 *
1974 * The device must be connected to the parent
1975 *
1976 * @param dev Device structure
1977 *
1978 * @return EOK if succeed
1979 * @return An error code otherwise
1980 *
1981 */
1982static errno_t e1000_get_resource_info(ddf_dev_t *dev)
1983{
1984 assert(dev != NULL);
1985 assert(NIC_DATA_DEV(dev) != NULL);
1986
1987 hw_res_list_parsed_t hw_res_parsed;
1988 hw_res_list_parsed_init(&hw_res_parsed);
1989
1990 /* Get hw resources form parent driver */
1991 errno_t rc = nic_get_resources(NIC_DATA_DEV(dev), &hw_res_parsed);
1992 if (rc != EOK)
1993 return rc;
1994
1995 /* Fill resources information to the device */
1996 rc = e1000_fill_resource_info(dev, &hw_res_parsed);
1997 hw_res_list_parsed_clean(&hw_res_parsed);
1998
1999 return rc;
2000}
2001
2002/** Initialize the E1000 device structure
2003 *
2004 * @param dev Device information
2005 *
2006 * @return EOK if succeed
2007 * @return An error code otherwise
2008 *
2009 */
2010static errno_t e1000_device_initialize(ddf_dev_t *dev)
2011{
2012 /* Allocate driver data for the device. */
2013 e1000_t *e1000 = e1000_create_dev_data(dev);
2014 if (e1000 == NULL) {
2015 ddf_msg(LVL_ERROR, "Unable to allocate device softstate");
2016 return ENOMEM;
2017 }
2018
2019 e1000->parent_sess = ddf_dev_parent_sess_get(dev);
2020 if (e1000->parent_sess == NULL) {
2021 ddf_msg(LVL_ERROR, "Failed connecting parent device.");
2022 return EIO;
2023 }
2024
2025 /* Obtain and fill hardware resources info */
2026 errno_t rc = e1000_get_resource_info(dev);
2027 if (rc != EOK) {
2028 ddf_msg(LVL_ERROR, "Cannot obtain hardware resources");
2029 e1000_dev_cleanup(dev);
2030 return rc;
2031 }
2032
2033 uint16_t device_id;
2034 rc = pci_config_space_read_16(ddf_dev_parent_sess_get(dev), PCI_DEVICE_ID,
2035 &device_id);
2036 if (rc != EOK) {
2037 ddf_msg(LVL_ERROR, "Cannot access PCI configuration space");
2038 e1000_dev_cleanup(dev);
2039 return rc;
2040 }
2041
2042 e1000_board_t board;
2043 switch (device_id) {
2044 case 0x100e:
2045 case 0x1015:
2046 case 0x1016:
2047 case 0x1017:
2048 board = E1000_82540;
2049 break;
2050 case 0x1013:
2051 case 0x1018:
2052 case 0x1078:
2053 board = E1000_82541;
2054 break;
2055 case 0x1076:
2056 case 0x1077:
2057 case 0x107c:
2058 board = E1000_82541REV2;
2059 break;
2060 case 0x100f:
2061 case 0x1011:
2062 case 0x1026:
2063 case 0x1027:
2064 case 0x1028:
2065 board = E1000_82545;
2066 break;
2067 case 0x1010:
2068 case 0x1012:
2069 case 0x101d:
2070 case 0x1079:
2071 case 0x107a:
2072 case 0x107b:
2073 board = E1000_82546;
2074 break;
2075 case 0x1019:
2076 case 0x101a:
2077 board = E1000_82547;
2078 break;
2079 case 0x10b9:
2080 board = E1000_82572;
2081 break;
2082 case 0x1096:
2083 board = E1000_80003ES2;
2084 break;
2085 default:
2086 ddf_msg(LVL_ERROR, "Device not supported (%#" PRIx16 ")",
2087 device_id);
2088 e1000_dev_cleanup(dev);
2089 return ENOTSUP;
2090 }
2091
2092 switch (board) {
2093 case E1000_82540:
2094 case E1000_82541:
2095 case E1000_82541REV2:
2096 case E1000_82545:
2097 case E1000_82546:
2098 e1000->info.eerd_start = 0x01;
2099 e1000->info.eerd_done = 0x10;
2100 e1000->info.eerd_address_offset = 8;
2101 e1000->info.eerd_data_offset = 16;
2102 break;
2103 case E1000_82547:
2104 case E1000_82572:
2105 case E1000_80003ES2:
2106 e1000->info.eerd_start = 0x01;
2107 e1000->info.eerd_done = 0x02;
2108 e1000->info.eerd_address_offset = 2;
2109 e1000->info.eerd_data_offset = 16;
2110 break;
2111 }
2112
2113 return EOK;
2114}
2115
2116/** Enable the I/O ports of the device.
2117 *
2118 * @param dev E1000 device.
2119 *
2120 * @return EOK if successed
2121 * @return An error code otherwise
2122 *
2123 */
2124static errno_t e1000_pio_enable(ddf_dev_t *dev)
2125{
2126 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
2127
2128 errno_t rc = pio_enable(e1000->reg_base_phys, 8 * PAGE_SIZE,
2129 &e1000->reg_base_virt);
2130 if (rc != EOK)
2131 return EADDRNOTAVAIL;
2132
2133 return EOK;
2134}
2135
2136/** Probe and initialize the newly added device.
2137 *
2138 * @param dev E1000 device.
2139 *
2140 */
2141errno_t e1000_dev_add(ddf_dev_t *dev)
2142{
2143 ddf_fun_t *fun;
2144
2145 /* Initialize device structure for E1000 */
2146 errno_t rc = e1000_device_initialize(dev);
2147 if (rc != EOK)
2148 return rc;
2149
2150 /* Device initialization */
2151 nic_t *nic = ddf_dev_data_get(dev);
2152 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2153
2154 /* Map registers */
2155 rc = e1000_pio_enable(dev);
2156 if (rc != EOK)
2157 goto err_destroy;
2158
2159 e1000_initialize_registers(e1000);
2160 rc = e1000_initialize_tx_structure(e1000);
2161 if (rc != EOK)
2162 goto err_pio;
2163
2164 fibril_mutex_lock(&e1000->rx_lock);
2165
2166 e1000_fill_mac_from_eeprom(e1000);
2167 e1000_initialize_filters(e1000);
2168
2169 fibril_mutex_unlock(&e1000->rx_lock);
2170
2171 e1000_initialize_vlan(e1000);
2172
2173 fun = ddf_fun_create(nic_get_ddf_dev(nic), fun_exposed, "port0");
2174 if (fun == NULL)
2175 goto err_tx_structure;
2176 nic_set_ddf_fun(nic, fun);
2177 ddf_fun_set_ops(fun, &e1000_dev_ops);
2178
2179 cap_irq_handle_t irq_handle;
2180 rc = e1000_register_int_handler(nic, &irq_handle);
2181 if (rc != EOK) {
2182 goto err_fun_create;
2183 }
2184
2185 rc = e1000_initialize_rx_structure(nic);
2186 if (rc != EOK)
2187 goto err_irq;
2188
2189 nic_address_t e1000_address;
2190 e1000_get_address(e1000, &e1000_address);
2191 rc = nic_report_address(nic, &e1000_address);
2192 if (rc != EOK)
2193 goto err_rx_structure;
2194
2195 struct timespec period;
2196 period.tv_sec = 0;
2197 period.tv_nsec = USEC2NSEC(E1000_DEFAULT_INTERRUPT_INTERVAL_USEC);
2198 rc = nic_report_poll_mode(nic, NIC_POLL_PERIODIC, &period);
2199 if (rc != EOK)
2200 goto err_rx_structure;
2201
2202 rc = ddf_fun_bind(fun);
2203 if (rc != EOK)
2204 goto err_fun_bind;
2205
2206 rc = ddf_fun_add_to_category(fun, DEVICE_CATEGORY_NIC);
2207 if (rc != EOK)
2208 goto err_add_to_cat;
2209
2210 errno_t pcap_rc = pcapdump_init(nic_get_pcap_iface(nic));
2211
2212 if (pcap_rc != EOK) {
2213 printf("Failed creating pcapdump port\n");
2214 }
2215 rc = ddf_fun_add_to_category(fun, "pcap");
2216 if (rc != EOK)
2217 goto err_add_to_cat;
2218
2219 return EOK;
2220
2221err_add_to_cat:
2222 ddf_fun_unbind(fun);
2223err_fun_bind:
2224err_rx_structure:
2225 e1000_uninitialize_rx_structure(nic);
2226err_irq:
2227 unregister_interrupt_handler(dev, irq_handle);
2228err_fun_create:
2229 ddf_fun_destroy(fun);
2230 nic_set_ddf_fun(nic, NULL);
2231err_tx_structure:
2232 e1000_uninitialize_tx_structure(e1000);
2233err_pio:
2234 // TODO: e1000_pio_disable(dev);
2235err_destroy:
2236 e1000_dev_cleanup(dev);
2237 return rc;
2238}
2239
2240/** Read 16-bit value from EEPROM of E1000 adapter
2241 *
2242 * Read using the EERD register.
2243 *
2244 * @param device E1000 device
2245 * @param eeprom_address 8-bit EEPROM address
2246 *
2247 * @return 16-bit value from EEPROM
2248 *
2249 */
2250static uint16_t e1000_eeprom_read(e1000_t *e1000, uint8_t eeprom_address)
2251{
2252 fibril_mutex_lock(&e1000->eeprom_lock);
2253
2254 /* Write address and START bit to EERD register */
2255 uint32_t write_data = e1000->info.eerd_start |
2256 (((uint32_t) eeprom_address) <<
2257 e1000->info.eerd_address_offset);
2258 E1000_REG_WRITE(e1000, E1000_EERD, write_data);
2259
2260 uint32_t eerd = E1000_REG_READ(e1000, E1000_EERD);
2261 while ((eerd & e1000->info.eerd_done) == 0) {
2262 fibril_usleep(1);
2263 eerd = E1000_REG_READ(e1000, E1000_EERD);
2264 }
2265
2266 fibril_mutex_unlock(&e1000->eeprom_lock);
2267
2268 return (uint16_t) (eerd >> e1000->info.eerd_data_offset);
2269}
2270
2271/** Get MAC address of the E1000 adapter
2272 *
2273 * @param device E1000 device
2274 * @param address Place to store the address
2275 * @param max_len Maximal addresss length to store
2276 *
2277 * @return EOK if succeed
2278 * @return An error code otherwise
2279 *
2280 */
2281static errno_t e1000_get_address(e1000_t *e1000, nic_address_t *address)
2282{
2283 fibril_mutex_lock(&e1000->rx_lock);
2284
2285 uint8_t *mac0_dest = (uint8_t *) address->address;
2286 uint8_t *mac1_dest = (uint8_t *) address->address + 1;
2287 uint8_t *mac2_dest = (uint8_t *) address->address + 2;
2288 uint8_t *mac3_dest = (uint8_t *) address->address + 3;
2289 uint8_t *mac4_dest = (uint8_t *) address->address + 4;
2290 uint8_t *mac5_dest = (uint8_t *) address->address + 5;
2291
2292 uint32_t rah = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
2293 uint32_t ral = E1000_REG_READ(e1000, E1000_RAL_ARRAY(0));
2294
2295 *mac0_dest = (uint8_t) ral;
2296 *mac1_dest = (uint8_t) (ral >> 8);
2297 *mac2_dest = (uint8_t) (ral >> 16);
2298 *mac3_dest = (uint8_t) (ral >> 24);
2299 *mac4_dest = (uint8_t) rah;
2300 *mac5_dest = (uint8_t) (rah >> 8);
2301
2302 fibril_mutex_unlock(&e1000->rx_lock);
2303 return EOK;
2304}
2305
2306/** Set card MAC address
2307 *
2308 * @param device E1000 device
2309 * @param address Address
2310 *
2311 * @return EOK if succeed
2312 * @return An error code otherwise
2313 */
2314static errno_t e1000_set_addr(ddf_fun_t *fun, const nic_address_t *addr)
2315{
2316 nic_t *nic = NIC_DATA_FUN(fun);
2317 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2318
2319 fibril_mutex_lock(&e1000->rx_lock);
2320 fibril_mutex_lock(&e1000->tx_lock);
2321
2322 errno_t rc = nic_report_address(nic, addr);
2323 if (rc == EOK)
2324 e1000_write_receive_address(e1000, 0, addr, false);
2325
2326 fibril_mutex_unlock(&e1000->tx_lock);
2327 fibril_mutex_unlock(&e1000->rx_lock);
2328
2329 return rc;
2330}
2331
2332static void e1000_eeprom_get_address(e1000_t *e1000,
2333 nic_address_t *address)
2334{
2335 uint16_t *mac0_dest = (uint16_t *) address->address;
2336 uint16_t *mac2_dest = (uint16_t *) (address->address + 2);
2337 uint16_t *mac4_dest = (uint16_t *) (address->address + 4);
2338
2339 *mac0_dest = e1000_eeprom_read(e1000, 0);
2340 *mac2_dest = e1000_eeprom_read(e1000, 1);
2341 *mac4_dest = e1000_eeprom_read(e1000, 2);
2342}
2343
2344/** Send frame
2345 *
2346 * @param nic NIC driver data structure
2347 * @param data Frame data
2348 * @param size Frame size in bytes
2349 *
2350 * @return EOK if succeed
2351 * @return Error code in the case of error
2352 *
2353 */
2354static void e1000_send_frame(nic_t *nic, void *data, size_t size)
2355{
2356 assert(nic);
2357
2358 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2359 fibril_mutex_lock(&e1000->tx_lock);
2360
2361 uint32_t tdt = E1000_REG_READ(e1000, E1000_TDT);
2362 e1000_tx_descriptor_t *tx_descriptor_addr = (e1000_tx_descriptor_t *)
2363 (e1000->tx_ring_virt + tdt * sizeof(e1000_tx_descriptor_t));
2364
2365 bool descriptor_available = false;
2366
2367 /* Descriptor never used */
2368 if (tx_descriptor_addr->length == 0)
2369 descriptor_available = true;
2370
2371 /* Descriptor done */
2372 if (tx_descriptor_addr->status & TXDESCRIPTOR_STATUS_DD)
2373 descriptor_available = true;
2374
2375 if (!descriptor_available) {
2376 /* Frame lost */
2377 fibril_mutex_unlock(&e1000->tx_lock);
2378 return;
2379 }
2380
2381 memcpy(e1000->tx_frame_virt[tdt], data, size);
2382 pcapdump_packet(nic_get_pcap_iface(nic), data, size);
2383 tx_descriptor_addr->phys_addr = PTR_TO_U64(e1000->tx_frame_phys[tdt]);
2384 tx_descriptor_addr->length = size;
2385
2386 /*
2387 * Report status to STATUS.DD (descriptor done),
2388 * add ethernet CRC, end of packet.
2389 */
2390 tx_descriptor_addr->command = TXDESCRIPTOR_COMMAND_RS |
2391 TXDESCRIPTOR_COMMAND_IFCS |
2392 TXDESCRIPTOR_COMMAND_EOP;
2393
2394 tx_descriptor_addr->checksum_offset = 0;
2395 tx_descriptor_addr->status = 0;
2396 if (e1000->vlan_tag_add) {
2397 tx_descriptor_addr->special = e1000->vlan_tag;
2398 tx_descriptor_addr->command |= TXDESCRIPTOR_COMMAND_VLE;
2399 } else
2400 tx_descriptor_addr->special = 0;
2401
2402 tx_descriptor_addr->checksum_start_field = 0;
2403
2404 tdt++;
2405 if (tdt == E1000_TX_FRAME_COUNT)
2406 tdt = 0;
2407
2408 E1000_REG_WRITE(e1000, E1000_TDT, tdt);
2409
2410 fibril_mutex_unlock(&e1000->tx_lock);
2411}
2412
2413int main(void)
2414{
2415 printf("%s: HelenOS E1000 network adapter driver\n", NAME);
2416
2417 if (nic_driver_init(NAME) != EOK)
2418 return 1;
2419
2420 nic_driver_implement(&e1000_driver_ops, &e1000_dev_ops,
2421 &e1000_nic_iface);
2422
2423 ddf_log_init(NAME);
2424 return ddf_driver_main(&e1000_driver);
2425}
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