source: mainline/uspace/drv/nic/e1k/e1k.c@ 145a13b

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 145a13b was 807be7e, checked in by jxsvoboda <5887334+jxsvoboda@…>, 5 years ago

Mask the ICR register in the interrupt claim pseudo-code to prevent
false interrupt claims when masked-out ICR causes are true.
  • Property mode set to 100644
File size: 56.4 KB
Line 
1/*
2 * Copyright (c) 2011 Zdenek Bouska
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @file e1k.c
30 *
31 * Driver for Intel Pro/1000 8254x Family of Gigabit Ethernet Controllers
32 *
33 */
34
35#include <async.h>
36#include <assert.h>
37#include <stdio.h>
38#include <errno.h>
39#include <adt/list.h>
40#include <align.h>
41#include <byteorder.h>
42#include <as.h>
43#include <ddi.h>
44#include <ddf/log.h>
45#include <ddf/interrupt.h>
46#include <device/hw_res.h>
47#include <device/hw_res_parsed.h>
48#include <pci_dev_iface.h>
49#include <nic.h>
50#include <ops/nic.h>
51#include "e1k.h"
52
53#define NAME "e1k"
54
55#define E1000_DEFAULT_INTERRUPT_INTERVAL_USEC 250
56
57/* Must be power of 8 */
58#define E1000_RX_FRAME_COUNT 128
59#define E1000_TX_FRAME_COUNT 128
60
61#define E1000_RECEIVE_ADDRESS 16
62
63/** Maximum sending frame size */
64#define E1000_MAX_SEND_FRAME_SIZE 2048
65/** Maximum receiving frame size */
66#define E1000_MAX_RECEIVE_FRAME_SIZE 2048
67
68/** nic_driver_data_t* -> e1000_t* cast */
69#define DRIVER_DATA_NIC(nic) \
70 ((e1000_t *) nic_get_specific(nic))
71
72/** ddf_fun_t * -> nic_driver_data_t* cast */
73#define NIC_DATA_FUN(fun) \
74 ((nic_t *) ddf_dev_data_get(ddf_fun_get_dev(fun)))
75
76/** ddf_dev_t * -> nic_driver_data_t* cast */
77#define NIC_DATA_DEV(dev) \
78 ((nic_t *) ddf_dev_data_get(dev))
79
80/** ddf_dev_t * -> e1000_t* cast */
81#define DRIVER_DATA_DEV(dev) \
82 (DRIVER_DATA_NIC(NIC_DATA_DEV(dev)))
83
84/** ddf_fun_t * -> e1000_t* cast */
85#define DRIVER_DATA_FUN(fun) \
86 (DRIVER_DATA_NIC(NIC_DATA_FUN(fun)))
87
88/** Cast pointer to uint64_t
89 *
90 * @param ptr Pointer to cast
91 *
92 * @return The uint64_t pointer representation.
93 *
94 */
95#define PTR_TO_U64(ptr) ((uint64_t) ((uintptr_t) (ptr)))
96
97/** Cast the memaddr part to the void*
98 *
99 * @param memaddr The memaddr value
100 *
101 */
102#define MEMADDR_TO_PTR(memaddr) ((void *) ((size_t) (memaddr)))
103
104#define E1000_REG_BASE(e1000) \
105 ((e1000)->reg_base_virt)
106
107#define E1000_REG_ADDR(e1000, reg) \
108 ((uint32_t *) (E1000_REG_BASE(e1000) + reg))
109
110#define E1000_REG_READ(e1000, reg) \
111 (pio_read_32(E1000_REG_ADDR(e1000, reg)))
112
113#define E1000_REG_WRITE(e1000, reg, value) \
114 (pio_write_32(E1000_REG_ADDR(e1000, reg), value))
115
116/** E1000 device data */
117typedef struct {
118 /** DDF device */
119 ddf_dev_t *dev;
120 /** Parent session */
121 async_sess_t *parent_sess;
122 /** Device configuration */
123 e1000_info_t info;
124
125 /** Physical registers base address */
126 void *reg_base_phys;
127 /** Virtual registers base address */
128 void *reg_base_virt;
129
130 /** Physical tx ring address */
131 uintptr_t tx_ring_phys;
132 /** Virtual tx ring address */
133 void *tx_ring_virt;
134
135 /** Ring of TX frames, physical address */
136 uintptr_t *tx_frame_phys;
137 /** Ring of TX frames, virtual address */
138 void **tx_frame_virt;
139
140 /** Physical rx ring address */
141 uintptr_t rx_ring_phys;
142 /** Virtual rx ring address */
143 void *rx_ring_virt;
144
145 /** Ring of RX frames, physical address */
146 uintptr_t *rx_frame_phys;
147 /** Ring of RX frames, virtual address */
148 void **rx_frame_virt;
149
150 /** VLAN tag */
151 uint16_t vlan_tag;
152
153 /** Add VLAN tag to frame */
154 bool vlan_tag_add;
155
156 /** Used unicast Receive Address count */
157 unsigned int unicast_ra_count;
158
159 /** Used milticast Receive addrress count */
160 unsigned int multicast_ra_count;
161
162 /** The irq assigned */
163 int irq;
164
165 /** Lock for CTRL register */
166 fibril_mutex_t ctrl_lock;
167
168 /** Lock for receiver */
169 fibril_mutex_t rx_lock;
170
171 /** Lock for transmitter */
172 fibril_mutex_t tx_lock;
173
174 /** Lock for EEPROM access */
175 fibril_mutex_t eeprom_lock;
176} e1000_t;
177
178/** Global mutex for work with shared irq structure */
179FIBRIL_MUTEX_INITIALIZE(irq_reg_mutex);
180
181static errno_t e1000_get_address(e1000_t *, nic_address_t *);
182static void e1000_eeprom_get_address(e1000_t *, nic_address_t *);
183static errno_t e1000_set_addr(ddf_fun_t *, const nic_address_t *);
184
185static errno_t e1000_defective_get_mode(ddf_fun_t *, uint32_t *);
186static errno_t e1000_defective_set_mode(ddf_fun_t *, uint32_t);
187
188static errno_t e1000_get_cable_state(ddf_fun_t *, nic_cable_state_t *);
189static errno_t e1000_get_device_info(ddf_fun_t *, nic_device_info_t *);
190static errno_t e1000_get_operation_mode(ddf_fun_t *, int *,
191 nic_channel_mode_t *, nic_role_t *);
192static errno_t e1000_set_operation_mode(ddf_fun_t *, int,
193 nic_channel_mode_t, nic_role_t);
194static errno_t e1000_autoneg_enable(ddf_fun_t *, uint32_t);
195static errno_t e1000_autoneg_disable(ddf_fun_t *);
196static errno_t e1000_autoneg_restart(ddf_fun_t *);
197
198static errno_t e1000_vlan_set_tag(ddf_fun_t *, uint16_t, bool, bool);
199
200/** Network interface options for E1000 card driver */
201static nic_iface_t e1000_nic_iface;
202
203/** Network interface options for E1000 card driver */
204static nic_iface_t e1000_nic_iface = {
205 .set_address = &e1000_set_addr,
206 .get_device_info = &e1000_get_device_info,
207 .get_cable_state = &e1000_get_cable_state,
208 .get_operation_mode = &e1000_get_operation_mode,
209 .set_operation_mode = &e1000_set_operation_mode,
210 .autoneg_enable = &e1000_autoneg_enable,
211 .autoneg_disable = &e1000_autoneg_disable,
212 .autoneg_restart = &e1000_autoneg_restart,
213 .vlan_set_tag = &e1000_vlan_set_tag,
214 .defective_get_mode = &e1000_defective_get_mode,
215 .defective_set_mode = &e1000_defective_set_mode,
216};
217
218/** Basic device operations for E1000 driver */
219static ddf_dev_ops_t e1000_dev_ops;
220
221static errno_t e1000_dev_add(ddf_dev_t *);
222
223/** Basic driver operations for E1000 driver */
224static driver_ops_t e1000_driver_ops = {
225 .dev_add = e1000_dev_add
226};
227
228/** Driver structure for E1000 driver */
229static driver_t e1000_driver = {
230 .name = NAME,
231 .driver_ops = &e1000_driver_ops
232};
233
234/* The default implementation callbacks */
235static errno_t e1000_on_activating(nic_t *);
236static errno_t e1000_on_stopping(nic_t *);
237static void e1000_send_frame(nic_t *, void *, size_t);
238
239/** PIO ranges used in the IRQ code. */
240irq_pio_range_t e1000_irq_pio_ranges[] = {
241 {
242 .base = 0,
243 .size = PAGE_SIZE, /* XXX */
244 }
245};
246
247/** Commands to deal with interrupt
248 *
249 */
250irq_cmd_t e1000_irq_commands[] = {
251 {
252 /* Get the interrupt status */
253 .cmd = CMD_PIO_READ_32,
254 .addr = NULL,
255 .dstarg = 2
256 },
257 {
258 .cmd = CMD_AND,
259 .value = ICR_RXT0,
260 .srcarg = 2,
261 .dstarg = 1
262 },
263 {
264 .cmd = CMD_PREDICATE,
265 .value = 2,
266 .srcarg = 1
267 },
268 {
269 /* Disable interrupts until interrupt routine is finished */
270 .cmd = CMD_PIO_WRITE_32,
271 .addr = NULL,
272 .value = 0xffffffff
273 },
274 {
275 .cmd = CMD_ACCEPT
276 }
277};
278
279/** Interrupt code definition */
280irq_code_t e1000_irq_code = {
281 .rangecount = sizeof(e1000_irq_pio_ranges) /
282 sizeof(irq_pio_range_t),
283 .ranges = e1000_irq_pio_ranges,
284 .cmdcount = sizeof(e1000_irq_commands) / sizeof(irq_cmd_t),
285 .cmds = e1000_irq_commands
286};
287
288/** Get the device information
289 *
290 * @param dev NIC device
291 * @param info Information to fill
292 *
293 * @return EOK
294 *
295 */
296static errno_t e1000_get_device_info(ddf_fun_t *dev, nic_device_info_t *info)
297{
298 assert(dev);
299 assert(info);
300
301 memset(info, 0, sizeof(nic_device_info_t));
302
303 info->vendor_id = 0x8086;
304 str_cpy(info->vendor_name, NIC_VENDOR_MAX_LENGTH,
305 "Intel Corporation");
306 str_cpy(info->model_name, NIC_MODEL_MAX_LENGTH,
307 "Intel Pro");
308
309 info->ethernet_support[ETH_10M] = ETH_10BASE_T;
310 info->ethernet_support[ETH_100M] = ETH_100BASE_TX;
311 info->ethernet_support[ETH_1000M] = ETH_1000BASE_T;
312
313 return EOK;
314}
315
316/** Check the cable state
317 *
318 * @param[in] dev device
319 * @param[out] state state to fill
320 *
321 * @return EOK
322 *
323 */
324static errno_t e1000_get_cable_state(ddf_fun_t *fun, nic_cable_state_t *state)
325{
326 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
327 if (E1000_REG_READ(e1000, E1000_STATUS) & (STATUS_LU))
328 *state = NIC_CS_PLUGGED;
329 else
330 *state = NIC_CS_UNPLUGGED;
331
332 return EOK;
333}
334
335static uint16_t e1000_calculate_itr_interval_from_usecs(usec_t useconds)
336{
337 return useconds * 4;
338}
339
340/** Get operation mode of the device
341 *
342 */
343static errno_t e1000_get_operation_mode(ddf_fun_t *fun, int *speed,
344 nic_channel_mode_t *duplex, nic_role_t *role)
345{
346 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
347 uint32_t status = E1000_REG_READ(e1000, E1000_STATUS);
348
349 if (status & STATUS_FD)
350 *duplex = NIC_CM_FULL_DUPLEX;
351 else
352 *duplex = NIC_CM_HALF_DUPLEX;
353
354 uint32_t speed_bits =
355 (status >> STATUS_SPEED_SHIFT) & STATUS_SPEED_ALL;
356
357 if (speed_bits == STATUS_SPEED_10)
358 *speed = 10;
359 else if (speed_bits == STATUS_SPEED_100)
360 *speed = 100;
361 else if ((speed_bits == STATUS_SPEED_1000A) ||
362 (speed_bits == STATUS_SPEED_1000B))
363 *speed = 1000;
364
365 *role = NIC_ROLE_UNKNOWN;
366 return EOK;
367}
368
369static void e1000_link_restart(e1000_t *e1000)
370{
371 fibril_mutex_lock(&e1000->ctrl_lock);
372
373 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
374
375 if (ctrl & CTRL_SLU) {
376 ctrl &= ~(CTRL_SLU);
377 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
378 fibril_mutex_unlock(&e1000->ctrl_lock);
379
380 fibril_usleep(10);
381
382 fibril_mutex_lock(&e1000->ctrl_lock);
383 ctrl = E1000_REG_READ(e1000, E1000_CTRL);
384 ctrl |= CTRL_SLU;
385 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
386 }
387
388 fibril_mutex_unlock(&e1000->ctrl_lock);
389}
390
391/** Set operation mode of the device
392 *
393 */
394static errno_t e1000_set_operation_mode(ddf_fun_t *fun, int speed,
395 nic_channel_mode_t duplex, nic_role_t role)
396{
397 if ((speed != 10) && (speed != 100) && (speed != 1000))
398 return EINVAL;
399
400 if ((duplex != NIC_CM_HALF_DUPLEX) && (duplex != NIC_CM_FULL_DUPLEX))
401 return EINVAL;
402
403 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
404
405 fibril_mutex_lock(&e1000->ctrl_lock);
406 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
407
408 ctrl |= CTRL_FRCSPD;
409 ctrl |= CTRL_FRCDPLX;
410 ctrl &= ~(CTRL_ASDE);
411
412 if (duplex == NIC_CM_FULL_DUPLEX)
413 ctrl |= CTRL_FD;
414 else
415 ctrl &= ~(CTRL_FD);
416
417 ctrl &= ~(CTRL_SPEED_MASK);
418 if (speed == 1000)
419 ctrl |= CTRL_SPEED_1000 << CTRL_SPEED_SHIFT;
420 else if (speed == 100)
421 ctrl |= CTRL_SPEED_100 << CTRL_SPEED_SHIFT;
422 else
423 ctrl |= CTRL_SPEED_10 << CTRL_SPEED_SHIFT;
424
425 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
426
427 fibril_mutex_unlock(&e1000->ctrl_lock);
428
429 e1000_link_restart(e1000);
430
431 return EOK;
432}
433
434/** Enable auto-negotiation
435 *
436 * @param dev Device to update
437 * @param advertisement Ignored on E1000
438 *
439 * @return EOK if advertisement mode set successfully
440 *
441 */
442static errno_t e1000_autoneg_enable(ddf_fun_t *fun, uint32_t advertisement)
443{
444 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
445
446 fibril_mutex_lock(&e1000->ctrl_lock);
447
448 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
449
450 ctrl &= ~(CTRL_FRCSPD);
451 ctrl &= ~(CTRL_FRCDPLX);
452 ctrl |= CTRL_ASDE;
453
454 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
455
456 fibril_mutex_unlock(&e1000->ctrl_lock);
457
458 e1000_link_restart(e1000);
459
460 return EOK;
461}
462
463/** Disable auto-negotiation
464 *
465 * @param dev Device to update
466 *
467 * @return EOK
468 *
469 */
470static errno_t e1000_autoneg_disable(ddf_fun_t *fun)
471{
472 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
473
474 fibril_mutex_lock(&e1000->ctrl_lock);
475
476 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
477
478 ctrl |= CTRL_FRCSPD;
479 ctrl |= CTRL_FRCDPLX;
480 ctrl &= ~(CTRL_ASDE);
481
482 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
483
484 fibril_mutex_unlock(&e1000->ctrl_lock);
485
486 e1000_link_restart(e1000);
487
488 return EOK;
489}
490
491/** Restart auto-negotiation
492 *
493 * @param dev Device to update
494 *
495 * @return EOK if advertisement mode set successfully
496 *
497 */
498static errno_t e1000_autoneg_restart(ddf_fun_t *dev)
499{
500 return e1000_autoneg_enable(dev, 0);
501}
502
503/** Get state of acceptance of weird frames
504 *
505 * @param device Device to check
506 * @param[out] mode Current mode
507 *
508 */
509static errno_t e1000_defective_get_mode(ddf_fun_t *fun, uint32_t *mode)
510{
511 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
512
513 *mode = 0;
514 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
515 if (rctl & RCTL_SBP)
516 *mode = NIC_DEFECTIVE_BAD_CRC | NIC_DEFECTIVE_SHORT;
517
518 return EOK;
519}
520
521/** Set acceptance of weird frames
522 *
523 * @param device Device to update
524 * @param mode Mode to set
525 *
526 * @return ENOTSUP if the mode is not supported
527 * @return EOK of mode was set
528 *
529 */
530static errno_t e1000_defective_set_mode(ddf_fun_t *fun, uint32_t mode)
531{
532 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
533 errno_t rc = EOK;
534
535 fibril_mutex_lock(&e1000->rx_lock);
536
537 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
538 bool short_mode = (mode & NIC_DEFECTIVE_SHORT ? true : false);
539 bool bad_mode = (mode & NIC_DEFECTIVE_BAD_CRC ? true : false);
540
541 if (short_mode && bad_mode)
542 rctl |= RCTL_SBP;
543 else if ((!short_mode) && (!bad_mode))
544 rctl &= ~RCTL_SBP;
545 else
546 rc = ENOTSUP;
547
548 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
549
550 fibril_mutex_unlock(&e1000->rx_lock);
551 return rc;
552}
553
554/** Write receive address to RA registr
555 *
556 * @param e1000 E1000 data structure
557 * @param position RA register position
558 * @param address Ethernet address
559 * @param set_av_bit Set the Addtess Valid bit
560 *
561 */
562static void e1000_write_receive_address(e1000_t *e1000, unsigned int position,
563 const nic_address_t *address, bool set_av_bit)
564{
565 uint8_t *mac0 = (uint8_t *) address->address;
566 uint8_t *mac1 = (uint8_t *) address->address + 1;
567 uint8_t *mac2 = (uint8_t *) address->address + 2;
568 uint8_t *mac3 = (uint8_t *) address->address + 3;
569 uint8_t *mac4 = (uint8_t *) address->address + 4;
570 uint8_t *mac5 = (uint8_t *) address->address + 5;
571
572 uint32_t rah;
573 uint32_t ral;
574
575 ral = ((*mac3) << 24) | ((*mac2) << 16) | ((*mac1) << 8) | (*mac0);
576 rah = ((*mac5) << 8) | ((*mac4));
577
578 if (set_av_bit)
579 rah |= RAH_AV;
580 else
581 rah |= E1000_REG_READ(e1000, E1000_RAH_ARRAY(position)) & RAH_AV;
582
583 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(position), rah);
584 E1000_REG_WRITE(e1000, E1000_RAL_ARRAY(position), ral);
585}
586
587/** Disable receive address in RA registr
588 *
589 * Clear Address Valid bit
590 *
591 * @param e1000 E1000 data structure
592 * @param position RA register position
593 *
594 */
595static void e1000_disable_receive_address(e1000_t *e1000, unsigned int position)
596{
597 uint32_t rah = E1000_REG_READ(e1000, E1000_RAH_ARRAY(position));
598 rah = rah & ~RAH_AV;
599 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(position), rah);
600}
601
602/** Clear all unicast addresses from RA registers
603 *
604 * @param e1000 E1000 data structure
605 *
606 */
607static void e1000_clear_unicast_receive_addresses(e1000_t *e1000)
608{
609 for (unsigned int ra_num = 1;
610 ra_num <= e1000->unicast_ra_count;
611 ra_num++)
612 e1000_disable_receive_address(e1000, ra_num);
613
614 e1000->unicast_ra_count = 0;
615}
616
617/** Clear all multicast addresses from RA registers
618 *
619 * @param e1000 E1000 data structure
620 *
621 */
622static void e1000_clear_multicast_receive_addresses(e1000_t *e1000)
623{
624 unsigned int first_multicast_ra_num =
625 E1000_RECEIVE_ADDRESS - e1000->multicast_ra_count;
626
627 for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1;
628 ra_num >= first_multicast_ra_num;
629 ra_num--)
630 e1000_disable_receive_address(e1000, ra_num);
631
632 e1000->multicast_ra_count = 0;
633}
634
635/** Return receive address filter positions count usable for unicast
636 *
637 * @param e1000 E1000 data structure
638 *
639 * @return receive address filter positions count usable for unicast
640 *
641 */
642static unsigned int get_free_unicast_address_count(e1000_t *e1000)
643{
644 return E1000_RECEIVE_ADDRESS - 1 - e1000->multicast_ra_count;
645}
646
647/** Return receive address filter positions count usable for multicast
648 *
649 * @param e1000 E1000 data structure
650 *
651 * @return receive address filter positions count usable for multicast
652 *
653 */
654static unsigned int get_free_multicast_address_count(e1000_t *e1000)
655{
656 return E1000_RECEIVE_ADDRESS - 1 - e1000->unicast_ra_count;
657}
658
659/** Write unicast receive addresses to receive address filter registers
660 *
661 * @param e1000 E1000 data structure
662 * @param addr Pointer to address array
663 * @param addr_cnt Address array count
664 *
665 */
666static void e1000_add_unicast_receive_addresses(e1000_t *e1000,
667 const nic_address_t *addr, size_t addr_cnt)
668{
669 assert(addr_cnt <= get_free_unicast_address_count(e1000));
670
671 nic_address_t *addr_iterator = (nic_address_t *) addr;
672
673 /* ra_num = 0 is primary address */
674 for (unsigned int ra_num = 1;
675 ra_num <= addr_cnt;
676 ra_num++) {
677 e1000_write_receive_address(e1000, ra_num, addr_iterator, true);
678 addr_iterator++;
679 }
680}
681
682/** Write multicast receive addresses to receive address filter registers
683 *
684 * @param e1000 E1000 data structure
685 * @param addr Pointer to address array
686 * @param addr_cnt Address array count
687 *
688 */
689static void e1000_add_multicast_receive_addresses(e1000_t *e1000,
690 const nic_address_t *addr, size_t addr_cnt)
691{
692 assert(addr_cnt <= get_free_multicast_address_count(e1000));
693
694 nic_address_t *addr_iterator = (nic_address_t *) addr;
695
696 unsigned int first_multicast_ra_num = E1000_RECEIVE_ADDRESS - addr_cnt;
697 for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1;
698 ra_num >= first_multicast_ra_num;
699 ra_num--) {
700 e1000_write_receive_address(e1000, ra_num, addr_iterator, true);
701 addr_iterator++;
702 }
703}
704
705/** Disable receiving frames for default address
706 *
707 * @param e1000 E1000 data structure
708 *
709 */
710static void disable_ra0_address_filter(e1000_t *e1000)
711{
712 uint32_t rah0 = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
713 rah0 = rah0 & ~RAH_AV;
714 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(0), rah0);
715}
716
717/** Enable receiving frames for default address
718 *
719 * @param e1000 E1000 data structure
720 *
721 */
722static void enable_ra0_address_filter(e1000_t *e1000)
723{
724 uint32_t rah0 = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
725 rah0 = rah0 | RAH_AV;
726 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(0), rah0);
727}
728
729/** Disable unicast promiscuous mode
730 *
731 * @param e1000 E1000 data structure
732 *
733 */
734static void e1000_disable_unicast_promisc(e1000_t *e1000)
735{
736 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
737 rctl = rctl & ~RCTL_UPE;
738 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
739}
740
741/** Enable unicast promiscuous mode
742 *
743 * @param e1000 E1000 data structure
744 *
745 */
746static void e1000_enable_unicast_promisc(e1000_t *e1000)
747{
748 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
749 rctl = rctl | RCTL_UPE;
750 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
751}
752
753/** Disable multicast promiscuous mode
754 *
755 * @param e1000 E1000 data structure
756 *
757 */
758static void e1000_disable_multicast_promisc(e1000_t *e1000)
759{
760 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
761 rctl = rctl & ~RCTL_MPE;
762 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
763}
764
765/** Enable multicast promiscuous mode
766 *
767 * @param e1000 E1000 data structure
768 *
769 */
770static void e1000_enable_multicast_promisc(e1000_t *e1000)
771{
772 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
773 rctl = rctl | RCTL_MPE;
774 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
775}
776
777/** Enable accepting of broadcast frames
778 *
779 * @param e1000 E1000 data structure
780 *
781 */
782static void e1000_enable_broadcast_accept(e1000_t *e1000)
783{
784 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
785 rctl = rctl | RCTL_BAM;
786 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
787}
788
789/** Disable accepting of broadcast frames
790 *
791 * @param e1000 E1000 data structure
792 *
793 */
794static void e1000_disable_broadcast_accept(e1000_t *e1000)
795{
796 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
797 rctl = rctl & ~RCTL_BAM;
798 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
799}
800
801/** Enable VLAN filtering according to VFTA registers
802 *
803 * @param e1000 E1000 data structure
804 *
805 */
806static void e1000_enable_vlan_filter(e1000_t *e1000)
807{
808 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
809 rctl = rctl | RCTL_VFE;
810 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
811}
812
813/** Disable VLAN filtering
814 *
815 * @param e1000 E1000 data structure
816 *
817 */
818static void e1000_disable_vlan_filter(e1000_t *e1000)
819{
820 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
821 rctl = rctl & ~RCTL_VFE;
822 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
823}
824
825/** Set multicast frames acceptance mode
826 *
827 * @param nic NIC device to update
828 * @param mode Mode to set
829 * @param addr Address list (used in mode = NIC_MULTICAST_LIST)
830 * @param addr_cnt Length of address list (used in mode = NIC_MULTICAST_LIST)
831 *
832 * @return EOK
833 *
834 */
835static errno_t e1000_on_multicast_mode_change(nic_t *nic, nic_multicast_mode_t mode,
836 const nic_address_t *addr, size_t addr_cnt)
837{
838 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
839 errno_t rc = EOK;
840
841 fibril_mutex_lock(&e1000->rx_lock);
842
843 switch (mode) {
844 case NIC_MULTICAST_BLOCKED:
845 e1000_clear_multicast_receive_addresses(e1000);
846 e1000_disable_multicast_promisc(e1000);
847 nic_report_hw_filtering(nic, -1, 1, -1);
848 break;
849 case NIC_MULTICAST_LIST:
850 e1000_clear_multicast_receive_addresses(e1000);
851 if (addr_cnt > get_free_multicast_address_count(e1000)) {
852 /*
853 * Future work: fill MTA table
854 * Not strictly neccessary, it only saves some compares
855 * in the NIC library.
856 */
857 e1000_enable_multicast_promisc(e1000);
858 nic_report_hw_filtering(nic, -1, 0, -1);
859 } else {
860 e1000_disable_multicast_promisc(e1000);
861 e1000_add_multicast_receive_addresses(e1000, addr, addr_cnt);
862 nic_report_hw_filtering(nic, -1, 1, -1);
863 }
864 break;
865 case NIC_MULTICAST_PROMISC:
866 e1000_enable_multicast_promisc(e1000);
867 e1000_clear_multicast_receive_addresses(e1000);
868 nic_report_hw_filtering(nic, -1, 1, -1);
869 break;
870 default:
871 rc = ENOTSUP;
872 break;
873 }
874
875 fibril_mutex_unlock(&e1000->rx_lock);
876 return rc;
877}
878
879/** Set unicast frames acceptance mode
880 *
881 * @param nic NIC device to update
882 * @param mode Mode to set
883 * @param addr Address list (used in mode = NIC_MULTICAST_LIST)
884 * @param addr_cnt Length of address list (used in mode = NIC_MULTICAST_LIST)
885 *
886 * @return EOK
887 *
888 */
889static errno_t e1000_on_unicast_mode_change(nic_t *nic, nic_unicast_mode_t mode,
890 const nic_address_t *addr, size_t addr_cnt)
891{
892 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
893 errno_t rc = EOK;
894
895 fibril_mutex_lock(&e1000->rx_lock);
896
897 switch (mode) {
898 case NIC_UNICAST_BLOCKED:
899 disable_ra0_address_filter(e1000);
900 e1000_clear_unicast_receive_addresses(e1000);
901 e1000_disable_unicast_promisc(e1000);
902 nic_report_hw_filtering(nic, 1, -1, -1);
903 break;
904 case NIC_UNICAST_DEFAULT:
905 enable_ra0_address_filter(e1000);
906 e1000_clear_unicast_receive_addresses(e1000);
907 e1000_disable_unicast_promisc(e1000);
908 nic_report_hw_filtering(nic, 1, -1, -1);
909 break;
910 case NIC_UNICAST_LIST:
911 enable_ra0_address_filter(e1000);
912 e1000_clear_unicast_receive_addresses(e1000);
913 if (addr_cnt > get_free_unicast_address_count(e1000)) {
914 e1000_enable_unicast_promisc(e1000);
915 nic_report_hw_filtering(nic, 0, -1, -1);
916 } else {
917 e1000_disable_unicast_promisc(e1000);
918 e1000_add_unicast_receive_addresses(e1000, addr, addr_cnt);
919 nic_report_hw_filtering(nic, 1, -1, -1);
920 }
921 break;
922 case NIC_UNICAST_PROMISC:
923 e1000_enable_unicast_promisc(e1000);
924 enable_ra0_address_filter(e1000);
925 e1000_clear_unicast_receive_addresses(e1000);
926 nic_report_hw_filtering(nic, 1, -1, -1);
927 break;
928 default:
929 rc = ENOTSUP;
930 break;
931 }
932
933 fibril_mutex_unlock(&e1000->rx_lock);
934 return rc;
935}
936
937/** Set broadcast frames acceptance mode
938 *
939 * @param nic NIC device to update
940 * @param mode Mode to set
941 *
942 * @return EOK
943 *
944 */
945static errno_t e1000_on_broadcast_mode_change(nic_t *nic, nic_broadcast_mode_t mode)
946{
947 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
948 errno_t rc = EOK;
949
950 fibril_mutex_lock(&e1000->rx_lock);
951
952 switch (mode) {
953 case NIC_BROADCAST_BLOCKED:
954 e1000_disable_broadcast_accept(e1000);
955 break;
956 case NIC_BROADCAST_ACCEPTED:
957 e1000_enable_broadcast_accept(e1000);
958 break;
959 default:
960 rc = ENOTSUP;
961 break;
962 }
963
964 fibril_mutex_unlock(&e1000->rx_lock);
965 return rc;
966}
967
968/** Check if receiving is enabled
969 *
970 * @param e1000 E1000 data structure
971 *
972 * @return true if receiving is enabled
973 *
974 */
975static bool e1000_is_rx_enabled(e1000_t *e1000)
976{
977 if (E1000_REG_READ(e1000, E1000_RCTL) & (RCTL_EN))
978 return true;
979
980 return false;
981}
982
983/** Enable receiving
984 *
985 * @param e1000 E1000 data structure
986 *
987 */
988static void e1000_enable_rx(e1000_t *e1000)
989{
990 /* Set Receive Enable Bit */
991 E1000_REG_WRITE(e1000, E1000_RCTL,
992 E1000_REG_READ(e1000, E1000_RCTL) | (RCTL_EN));
993}
994
995/** Disable receiving
996 *
997 * @param e1000 E1000 data structure
998 *
999 */
1000static void e1000_disable_rx(e1000_t *e1000)
1001{
1002 /* Clear Receive Enable Bit */
1003 E1000_REG_WRITE(e1000, E1000_RCTL,
1004 E1000_REG_READ(e1000, E1000_RCTL) & ~(RCTL_EN));
1005}
1006
1007/** Set VLAN mask
1008 *
1009 * @param nic NIC device to update
1010 * @param vlan_mask VLAN mask
1011 *
1012 */
1013static void e1000_on_vlan_mask_change(nic_t *nic,
1014 const nic_vlan_mask_t *vlan_mask)
1015{
1016 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1017
1018 fibril_mutex_lock(&e1000->rx_lock);
1019
1020 if (vlan_mask) {
1021 /*
1022 * Disable receiving, so that frame matching
1023 * partially written VLAN is not received.
1024 */
1025 bool rx_enabled = e1000_is_rx_enabled(e1000);
1026 if (rx_enabled)
1027 e1000_disable_rx(e1000);
1028
1029 for (unsigned int i = 0; i < NIC_VLAN_BITMAP_SIZE; i += 4) {
1030 uint32_t bitmap_part =
1031 ((uint32_t) vlan_mask->bitmap[i]) |
1032 (((uint32_t) vlan_mask->bitmap[i + 1]) << 8) |
1033 (((uint32_t) vlan_mask->bitmap[i + 2]) << 16) |
1034 (((uint32_t) vlan_mask->bitmap[i + 3]) << 24);
1035 E1000_REG_WRITE(e1000, E1000_VFTA_ARRAY(i / 4), bitmap_part);
1036 }
1037
1038 e1000_enable_vlan_filter(e1000);
1039 if (rx_enabled)
1040 e1000_enable_rx(e1000);
1041 } else
1042 e1000_disable_vlan_filter(e1000);
1043
1044 fibril_mutex_unlock(&e1000->rx_lock);
1045}
1046
1047/** Set VLAN mask
1048 *
1049 * @param device E1000 device
1050 * @param tag VLAN tag
1051 *
1052 * @return EOK
1053 * @return ENOTSUP
1054 *
1055 */
1056static errno_t e1000_vlan_set_tag(ddf_fun_t *fun, uint16_t tag, bool add,
1057 bool strip)
1058{
1059 /* VLAN CFI bit cannot be set */
1060 if (tag & VLANTAG_CFI)
1061 return ENOTSUP;
1062
1063 /*
1064 * CTRL.VME is neccessary for both strip and add
1065 * but CTRL.VME means stripping tags on receive.
1066 */
1067 if (!strip && add)
1068 return ENOTSUP;
1069
1070 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
1071
1072 e1000->vlan_tag = tag;
1073 e1000->vlan_tag_add = add;
1074
1075 fibril_mutex_lock(&e1000->ctrl_lock);
1076
1077 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1078 if (strip)
1079 ctrl |= CTRL_VME;
1080 else
1081 ctrl &= ~CTRL_VME;
1082
1083 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1084
1085 fibril_mutex_unlock(&e1000->ctrl_lock);
1086 return EOK;
1087}
1088
1089/** Fill receive descriptor with new empty buffer
1090 *
1091 * Store frame in e1000->rx_frame_phys
1092 *
1093 * @param nic NIC data stricture
1094 * @param offset Receive descriptor offset
1095 *
1096 */
1097static void e1000_fill_new_rx_descriptor(nic_t *nic, size_t offset)
1098{
1099 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1100
1101 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1102 (e1000->rx_ring_virt + offset * sizeof(e1000_rx_descriptor_t));
1103
1104 rx_descriptor->phys_addr = PTR_TO_U64(e1000->rx_frame_phys[offset]);
1105 rx_descriptor->length = 0;
1106 rx_descriptor->checksum = 0;
1107 rx_descriptor->status = 0;
1108 rx_descriptor->errors = 0;
1109 rx_descriptor->special = 0;
1110}
1111
1112/** Clear receive descriptor
1113 *
1114 * @param e1000 E1000 data
1115 * @param offset Receive descriptor offset
1116 *
1117 */
1118static void e1000_clear_rx_descriptor(e1000_t *e1000, unsigned int offset)
1119{
1120 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1121 (e1000->rx_ring_virt + offset * sizeof(e1000_rx_descriptor_t));
1122
1123 rx_descriptor->length = 0;
1124 rx_descriptor->checksum = 0;
1125 rx_descriptor->status = 0;
1126 rx_descriptor->errors = 0;
1127 rx_descriptor->special = 0;
1128}
1129
1130/** Clear receive descriptor
1131 *
1132 * @param nic NIC data
1133 * @param offset Receive descriptor offset
1134 *
1135 */
1136static void e1000_clear_tx_descriptor(nic_t *nic, unsigned int offset)
1137{
1138 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1139
1140 e1000_tx_descriptor_t *tx_descriptor = (e1000_tx_descriptor_t *)
1141 (e1000->tx_ring_virt + offset * sizeof(e1000_tx_descriptor_t));
1142
1143 tx_descriptor->phys_addr = 0;
1144 tx_descriptor->length = 0;
1145 tx_descriptor->checksum_offset = 0;
1146 tx_descriptor->command = 0;
1147 tx_descriptor->status = 0;
1148 tx_descriptor->checksum_start_field = 0;
1149 tx_descriptor->special = 0;
1150}
1151
1152/** Increment tail pointer for receive or transmit ring
1153 *
1154 * @param tail Old Tail
1155 * @param descriptors_count Ring length
1156 *
1157 * @return New tail
1158 *
1159 */
1160static uint32_t e1000_inc_tail(uint32_t tail, uint32_t descriptors_count)
1161{
1162 if (tail + 1 == descriptors_count)
1163 return 0;
1164 else
1165 return tail + 1;
1166}
1167
1168/** Receive frames
1169 *
1170 * @param nic NIC data
1171 *
1172 */
1173static void e1000_receive_frames(nic_t *nic)
1174{
1175 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1176
1177 fibril_mutex_lock(&e1000->rx_lock);
1178
1179 uint32_t *tail_addr = E1000_REG_ADDR(e1000, E1000_RDT);
1180 uint32_t next_tail = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1181
1182 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1183 (e1000->rx_ring_virt + next_tail * sizeof(e1000_rx_descriptor_t));
1184
1185 while (rx_descriptor->status & 0x01) {
1186 uint32_t frame_size = rx_descriptor->length - E1000_CRC_SIZE;
1187
1188 nic_frame_t *frame = nic_alloc_frame(nic, frame_size);
1189 if (frame != NULL) {
1190 memcpy(frame->data, e1000->rx_frame_virt[next_tail], frame_size);
1191 nic_received_frame(nic, frame);
1192 } else {
1193 ddf_msg(LVL_ERROR, "Memory allocation failed. Frame dropped.");
1194 }
1195
1196 e1000_fill_new_rx_descriptor(nic, next_tail);
1197
1198 *tail_addr = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1199 next_tail = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1200
1201 rx_descriptor = (e1000_rx_descriptor_t *)
1202 (e1000->rx_ring_virt + next_tail * sizeof(e1000_rx_descriptor_t));
1203 }
1204
1205 fibril_mutex_unlock(&e1000->rx_lock);
1206}
1207
1208/** Enable E1000 interupts
1209 *
1210 * @param e1000 E1000 data structure
1211 *
1212 */
1213static void e1000_enable_interrupts(e1000_t *e1000)
1214{
1215 E1000_REG_WRITE(e1000, E1000_IMS, ICR_RXT0);
1216}
1217
1218/** Disable E1000 interupts
1219 *
1220 * @param e1000 E1000 data structure
1221 *
1222 */
1223static void e1000_disable_interrupts(e1000_t *e1000)
1224{
1225 E1000_REG_WRITE(e1000, E1000_IMS, 0);
1226}
1227
1228/** Interrupt handler implementation
1229 *
1230 * This function is called from e1000_interrupt_handler()
1231 * and e1000_poll()
1232 *
1233 * @param nic NIC data
1234 * @param icr ICR register value
1235 *
1236 */
1237static void e1000_interrupt_handler_impl(nic_t *nic, uint32_t icr)
1238{
1239 if (icr & ICR_RXT0)
1240 e1000_receive_frames(nic);
1241}
1242
1243/** Handle device interrupt
1244 *
1245 * @param icall IPC call structure
1246 * @param dev E1000 device
1247 *
1248 */
1249static void e1000_interrupt_handler(ipc_call_t *icall,
1250 ddf_dev_t *dev)
1251{
1252 uint32_t icr = (uint32_t) ipc_get_arg2(icall);
1253 nic_t *nic = NIC_DATA_DEV(dev);
1254 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1255
1256 e1000_interrupt_handler_impl(nic, icr);
1257 e1000_enable_interrupts(e1000);
1258}
1259
1260/** Register interrupt handler for the card in the system
1261 *
1262 * Note: The global irq_reg_mutex is locked because of work with global
1263 * structure.
1264 *
1265 * @param nic Driver data
1266 *
1267 * @param[out] handle IRQ capability handle if the handler was registered
1268 *
1269 * @return An error code otherwise
1270 *
1271 */
1272inline static errno_t e1000_register_int_handler(nic_t *nic,
1273 cap_irq_handle_t *handle)
1274{
1275 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1276
1277 /* Lock the mutex in whole driver while working with global structure */
1278 fibril_mutex_lock(&irq_reg_mutex);
1279
1280 e1000_irq_code.ranges[0].base = (uintptr_t) e1000->reg_base_phys;
1281 e1000_irq_code.cmds[0].addr = e1000->reg_base_phys + E1000_ICR;
1282 e1000_irq_code.cmds[3].addr = e1000->reg_base_phys + E1000_IMC;
1283
1284 errno_t rc = register_interrupt_handler(nic_get_ddf_dev(nic), e1000->irq,
1285 e1000_interrupt_handler, &e1000_irq_code, handle);
1286
1287 fibril_mutex_unlock(&irq_reg_mutex);
1288 return rc;
1289}
1290
1291/** Force receiving all frames in the receive buffer
1292 *
1293 * @param nic NIC data
1294 *
1295 */
1296static void e1000_poll(nic_t *nic)
1297{
1298 assert(nic);
1299
1300 e1000_t *e1000 = nic_get_specific(nic);
1301 assert(e1000);
1302
1303 uint32_t icr = E1000_REG_READ(e1000, E1000_ICR);
1304 e1000_interrupt_handler_impl(nic, icr);
1305}
1306
1307/** Calculates ITR register interrupt from timespec structure
1308 *
1309 * @param period Period
1310 *
1311 */
1312static uint16_t e1000_calculate_itr_interval(const struct timespec *period)
1313{
1314 // TODO: use also tv_sec
1315 return e1000_calculate_itr_interval_from_usecs(NSEC2USEC(period->tv_nsec));
1316}
1317
1318/** Set polling mode
1319 *
1320 * @param device Device to set
1321 * @param mode Mode to set
1322 * @param period Period for NIC_POLL_PERIODIC
1323 *
1324 * @return EOK if succeed
1325 * @return ENOTSUP if the mode is not supported
1326 *
1327 */
1328static errno_t e1000_poll_mode_change(nic_t *nic, nic_poll_mode_t mode,
1329 const struct timespec *period)
1330{
1331 assert(nic);
1332
1333 e1000_t *e1000 = nic_get_specific(nic);
1334 assert(e1000);
1335
1336 switch (mode) {
1337 case NIC_POLL_IMMEDIATE:
1338 E1000_REG_WRITE(e1000, E1000_ITR, 0);
1339 e1000_enable_interrupts(e1000);
1340 break;
1341 case NIC_POLL_ON_DEMAND:
1342 e1000_disable_interrupts(e1000);
1343 break;
1344 case NIC_POLL_PERIODIC:
1345 assert(period);
1346 uint16_t itr_interval = e1000_calculate_itr_interval(period);
1347 E1000_REG_WRITE(e1000, E1000_ITR, (uint32_t) itr_interval);
1348 e1000_enable_interrupts(e1000);
1349 break;
1350 default:
1351 return ENOTSUP;
1352 }
1353
1354 return EOK;
1355}
1356
1357/** Initialize receive registers
1358 *
1359 * @param e1000 E1000 data structure
1360 *
1361 */
1362static void e1000_initialize_rx_registers(e1000_t *e1000)
1363{
1364 E1000_REG_WRITE(e1000, E1000_RDLEN, E1000_RX_FRAME_COUNT * 16);
1365 E1000_REG_WRITE(e1000, E1000_RDH, 0);
1366
1367 /* It is not posible to let HW use all descriptors */
1368 E1000_REG_WRITE(e1000, E1000_RDT, E1000_RX_FRAME_COUNT - 1);
1369
1370 /* Set Broadcast Enable Bit */
1371 E1000_REG_WRITE(e1000, E1000_RCTL, RCTL_BAM);
1372}
1373
1374/** Initialize receive structure
1375 *
1376 * @param nic NIC data
1377 *
1378 * @return EOK if succeed
1379 * @return An error code otherwise
1380 *
1381 */
1382static errno_t e1000_initialize_rx_structure(nic_t *nic)
1383{
1384 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1385 fibril_mutex_lock(&e1000->rx_lock);
1386
1387 e1000->rx_ring_virt = AS_AREA_ANY;
1388 errno_t rc = dmamem_map_anonymous(
1389 E1000_RX_FRAME_COUNT * sizeof(e1000_rx_descriptor_t),
1390 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0,
1391 &e1000->rx_ring_phys, &e1000->rx_ring_virt);
1392 if (rc != EOK)
1393 return rc;
1394
1395 E1000_REG_WRITE(e1000, E1000_RDBAH,
1396 (uint32_t) (PTR_TO_U64(e1000->rx_ring_phys) >> 32));
1397 E1000_REG_WRITE(e1000, E1000_RDBAL,
1398 (uint32_t) PTR_TO_U64(e1000->rx_ring_phys));
1399
1400 e1000->rx_frame_phys = (uintptr_t *)
1401 calloc(E1000_RX_FRAME_COUNT, sizeof(uintptr_t));
1402 e1000->rx_frame_virt =
1403 calloc(E1000_RX_FRAME_COUNT, sizeof(void *));
1404 if ((e1000->rx_frame_phys == NULL) || (e1000->rx_frame_virt == NULL)) {
1405 rc = ENOMEM;
1406 goto error;
1407 }
1408
1409 for (size_t i = 0; i < E1000_RX_FRAME_COUNT; i++) {
1410 uintptr_t frame_phys;
1411 void *frame_virt = AS_AREA_ANY;
1412
1413 rc = dmamem_map_anonymous(E1000_MAX_SEND_FRAME_SIZE,
1414 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0,
1415 &frame_phys, &frame_virt);
1416 if (rc != EOK)
1417 goto error;
1418
1419 e1000->rx_frame_phys[i] = frame_phys;
1420 e1000->rx_frame_virt[i] = frame_virt;
1421 }
1422
1423 /* Write descriptor */
1424 for (size_t i = 0; i < E1000_RX_FRAME_COUNT; i++)
1425 e1000_fill_new_rx_descriptor(nic, i);
1426
1427 e1000_initialize_rx_registers(e1000);
1428
1429 fibril_mutex_unlock(&e1000->rx_lock);
1430 return EOK;
1431
1432error:
1433 for (size_t i = 0; i < E1000_RX_FRAME_COUNT; i++) {
1434 if (e1000->rx_frame_virt[i] != NULL) {
1435 dmamem_unmap_anonymous(e1000->rx_frame_virt[i]);
1436 e1000->rx_frame_phys[i] = 0;
1437 e1000->rx_frame_virt[i] = NULL;
1438 }
1439 }
1440
1441 if (e1000->rx_frame_phys != NULL) {
1442 free(e1000->rx_frame_phys);
1443 e1000->rx_frame_phys = NULL;
1444 }
1445
1446 if (e1000->rx_frame_virt != NULL) {
1447 free(e1000->rx_frame_virt);
1448 e1000->rx_frame_virt = NULL;
1449 }
1450
1451 return rc;
1452}
1453
1454/** Uninitialize receive structure
1455 *
1456 * @param nic NIC data
1457 *
1458 */
1459static void e1000_uninitialize_rx_structure(nic_t *nic)
1460{
1461 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1462
1463 /* Write descriptor */
1464 for (unsigned int offset = 0; offset < E1000_RX_FRAME_COUNT; offset++) {
1465 dmamem_unmap_anonymous(e1000->rx_frame_virt[offset]);
1466 e1000->rx_frame_phys[offset] = 0;
1467 e1000->rx_frame_virt[offset] = NULL;
1468 }
1469
1470 free(e1000->rx_frame_virt);
1471
1472 e1000->rx_frame_phys = NULL;
1473 e1000->rx_frame_virt = NULL;
1474
1475 dmamem_unmap_anonymous(e1000->rx_ring_virt);
1476}
1477
1478/** Clear receive descriptor ring
1479 *
1480 * @param e1000 E1000 data
1481 *
1482 */
1483static void e1000_clear_rx_ring(e1000_t *e1000)
1484{
1485 /* Write descriptor */
1486 for (unsigned int offset = 0;
1487 offset < E1000_RX_FRAME_COUNT;
1488 offset++)
1489 e1000_clear_rx_descriptor(e1000, offset);
1490}
1491
1492/** Initialize filters
1493 *
1494 * @param e1000 E1000 data
1495 *
1496 */
1497static void e1000_initialize_filters(e1000_t *e1000)
1498{
1499 /* Initialize address filter */
1500 e1000->unicast_ra_count = 0;
1501 e1000->multicast_ra_count = 0;
1502 e1000_clear_unicast_receive_addresses(e1000);
1503}
1504
1505/** Initialize VLAN
1506 *
1507 * @param e1000 E1000 data
1508 *
1509 */
1510static void e1000_initialize_vlan(e1000_t *e1000)
1511{
1512 e1000->vlan_tag_add = false;
1513}
1514
1515/** Fill MAC address from EEPROM to RA[0] register
1516 *
1517 * @param e1000 E1000 data
1518 *
1519 */
1520static void e1000_fill_mac_from_eeprom(e1000_t *e1000)
1521{
1522 /* MAC address from eeprom to RA[0] */
1523 nic_address_t address;
1524 e1000_eeprom_get_address(e1000, &address);
1525 e1000_write_receive_address(e1000, 0, &address, true);
1526}
1527
1528/** Initialize other registers
1529 *
1530 * @param dev E1000 data.
1531 *
1532 * @return EOK if succeed
1533 * @return An error code otherwise
1534 *
1535 */
1536static void e1000_initialize_registers(e1000_t *e1000)
1537{
1538 E1000_REG_WRITE(e1000, E1000_ITR,
1539 e1000_calculate_itr_interval_from_usecs(
1540 E1000_DEFAULT_INTERRUPT_INTERVAL_USEC));
1541 E1000_REG_WRITE(e1000, E1000_FCAH, 0);
1542 E1000_REG_WRITE(e1000, E1000_FCAL, 0);
1543 E1000_REG_WRITE(e1000, E1000_FCT, 0);
1544 E1000_REG_WRITE(e1000, E1000_FCTTV, 0);
1545 E1000_REG_WRITE(e1000, E1000_VET, VET_VALUE);
1546 E1000_REG_WRITE(e1000, E1000_CTRL, CTRL_ASDE);
1547}
1548
1549/** Initialize transmit registers
1550 *
1551 * @param e1000 E1000 data.
1552 *
1553 */
1554static void e1000_initialize_tx_registers(e1000_t *e1000)
1555{
1556 E1000_REG_WRITE(e1000, E1000_TDLEN, E1000_TX_FRAME_COUNT * 16);
1557 E1000_REG_WRITE(e1000, E1000_TDH, 0);
1558 E1000_REG_WRITE(e1000, E1000_TDT, 0);
1559
1560 E1000_REG_WRITE(e1000, E1000_TIPG,
1561 10 << TIPG_IPGT_SHIFT |
1562 8 << TIPG_IPGR1_SHIFT |
1563 6 << TIPG_IPGR2_SHIFT);
1564
1565 E1000_REG_WRITE(e1000, E1000_TCTL,
1566 0x0F << TCTL_CT_SHIFT /* Collision Threshold */ |
1567 0x40 << TCTL_COLD_SHIFT /* Collision Distance */ |
1568 TCTL_PSP /* Pad Short Packets */);
1569}
1570
1571/** Initialize transmit structure
1572 *
1573 * @param e1000 E1000 data.
1574 *
1575 */
1576static errno_t e1000_initialize_tx_structure(e1000_t *e1000)
1577{
1578 size_t i;
1579
1580 fibril_mutex_lock(&e1000->tx_lock);
1581
1582 e1000->tx_ring_phys = 0;
1583 e1000->tx_ring_virt = AS_AREA_ANY;
1584
1585 e1000->tx_frame_phys = NULL;
1586 e1000->tx_frame_virt = NULL;
1587
1588 errno_t rc = dmamem_map_anonymous(
1589 E1000_TX_FRAME_COUNT * sizeof(e1000_tx_descriptor_t),
1590 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0,
1591 &e1000->tx_ring_phys, &e1000->tx_ring_virt);
1592 if (rc != EOK)
1593 goto error;
1594
1595 memset(e1000->tx_ring_virt, 0,
1596 E1000_TX_FRAME_COUNT * sizeof(e1000_tx_descriptor_t));
1597
1598 e1000->tx_frame_phys = (uintptr_t *)
1599 calloc(E1000_TX_FRAME_COUNT, sizeof(uintptr_t));
1600 e1000->tx_frame_virt =
1601 calloc(E1000_TX_FRAME_COUNT, sizeof(void *));
1602
1603 if ((e1000->tx_frame_phys == NULL) || (e1000->tx_frame_virt == NULL)) {
1604 rc = ENOMEM;
1605 goto error;
1606 }
1607
1608 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1609 e1000->tx_frame_virt[i] = AS_AREA_ANY;
1610 rc = dmamem_map_anonymous(E1000_MAX_SEND_FRAME_SIZE,
1611 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE,
1612 0, &e1000->tx_frame_phys[i], &e1000->tx_frame_virt[i]);
1613 if (rc != EOK)
1614 goto error;
1615 }
1616
1617 E1000_REG_WRITE(e1000, E1000_TDBAH,
1618 (uint32_t) (PTR_TO_U64(e1000->tx_ring_phys) >> 32));
1619 E1000_REG_WRITE(e1000, E1000_TDBAL,
1620 (uint32_t) PTR_TO_U64(e1000->tx_ring_phys));
1621
1622 e1000_initialize_tx_registers(e1000);
1623
1624 fibril_mutex_unlock(&e1000->tx_lock);
1625 return EOK;
1626
1627error:
1628 if (e1000->tx_ring_virt != NULL) {
1629 dmamem_unmap_anonymous(e1000->tx_ring_virt);
1630 e1000->tx_ring_virt = NULL;
1631 }
1632
1633 if ((e1000->tx_frame_phys != NULL) && (e1000->tx_frame_virt != NULL)) {
1634 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1635 if (e1000->tx_frame_virt[i] != NULL) {
1636 dmamem_unmap_anonymous(e1000->tx_frame_virt[i]);
1637 e1000->tx_frame_phys[i] = 0;
1638 e1000->tx_frame_virt[i] = NULL;
1639 }
1640 }
1641 }
1642
1643 if (e1000->tx_frame_phys != NULL) {
1644 free(e1000->tx_frame_phys);
1645 e1000->tx_frame_phys = NULL;
1646 }
1647
1648 if (e1000->tx_frame_virt != NULL) {
1649 free(e1000->tx_frame_virt);
1650 e1000->tx_frame_virt = NULL;
1651 }
1652
1653 return rc;
1654}
1655
1656/** Uninitialize transmit structure
1657 *
1658 * @param nic NIC data
1659 *
1660 */
1661static void e1000_uninitialize_tx_structure(e1000_t *e1000)
1662{
1663 size_t i;
1664
1665 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1666 dmamem_unmap_anonymous(e1000->tx_frame_virt[i]);
1667 e1000->tx_frame_phys[i] = 0;
1668 e1000->tx_frame_virt[i] = NULL;
1669 }
1670
1671 if (e1000->tx_frame_phys != NULL) {
1672 free(e1000->tx_frame_phys);
1673 e1000->tx_frame_phys = NULL;
1674 }
1675
1676 if (e1000->tx_frame_virt != NULL) {
1677 free(e1000->tx_frame_virt);
1678 e1000->tx_frame_virt = NULL;
1679 }
1680
1681 dmamem_unmap_anonymous(e1000->tx_ring_virt);
1682}
1683
1684/** Clear transmit descriptor ring
1685 *
1686 * @param nic NIC data
1687 *
1688 */
1689static void e1000_clear_tx_ring(nic_t *nic)
1690{
1691 /* Write descriptor */
1692 for (unsigned int offset = 0;
1693 offset < E1000_TX_FRAME_COUNT;
1694 offset++)
1695 e1000_clear_tx_descriptor(nic, offset);
1696}
1697
1698/** Enable transmit
1699 *
1700 * @param e1000 E1000 data
1701 *
1702 */
1703static void e1000_enable_tx(e1000_t *e1000)
1704{
1705 /* Set Transmit Enable Bit */
1706 E1000_REG_WRITE(e1000, E1000_TCTL,
1707 E1000_REG_READ(e1000, E1000_TCTL) | (TCTL_EN));
1708}
1709
1710/** Disable transmit
1711 *
1712 * @param e1000 E1000 data
1713 *
1714 */
1715static void e1000_disable_tx(e1000_t *e1000)
1716{
1717 /* Clear Transmit Enable Bit */
1718 E1000_REG_WRITE(e1000, E1000_TCTL,
1719 E1000_REG_READ(e1000, E1000_TCTL) & ~(TCTL_EN));
1720}
1721
1722/** Reset E1000 device
1723 *
1724 * @param e1000 The E1000 data
1725 *
1726 */
1727static errno_t e1000_reset(nic_t *nic)
1728{
1729 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1730
1731 E1000_REG_WRITE(e1000, E1000_CTRL, CTRL_RST);
1732
1733 /* Wait for the reset */
1734 fibril_usleep(20);
1735
1736 /* check if RST_BIT cleared */
1737 if (E1000_REG_READ(e1000, E1000_CTRL) & (CTRL_RST))
1738 return EINVAL;
1739
1740 e1000_initialize_registers(e1000);
1741 e1000_initialize_rx_registers(e1000);
1742 e1000_initialize_tx_registers(e1000);
1743 e1000_fill_mac_from_eeprom(e1000);
1744 e1000_initialize_filters(e1000);
1745 e1000_initialize_vlan(e1000);
1746
1747 return EOK;
1748}
1749
1750/** Activate the device to receive and transmit frames
1751 *
1752 * @param nic NIC driver data
1753 *
1754 * @return EOK if activated successfully
1755 * @return Error code otherwise
1756 *
1757 */
1758static errno_t e1000_on_activating(nic_t *nic)
1759{
1760 assert(nic);
1761
1762 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1763
1764 fibril_mutex_lock(&e1000->rx_lock);
1765 fibril_mutex_lock(&e1000->tx_lock);
1766 fibril_mutex_lock(&e1000->ctrl_lock);
1767
1768 e1000_enable_interrupts(e1000);
1769
1770 errno_t rc = hw_res_enable_interrupt(e1000->parent_sess, e1000->irq);
1771 if (rc != EOK) {
1772 e1000_disable_interrupts(e1000);
1773 fibril_mutex_unlock(&e1000->ctrl_lock);
1774 fibril_mutex_unlock(&e1000->tx_lock);
1775 fibril_mutex_unlock(&e1000->rx_lock);
1776 return rc;
1777 }
1778
1779 e1000_clear_rx_ring(e1000);
1780 e1000_enable_rx(e1000);
1781
1782 e1000_clear_tx_ring(nic);
1783 e1000_enable_tx(e1000);
1784
1785 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1786 ctrl |= CTRL_SLU;
1787 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1788
1789 fibril_mutex_unlock(&e1000->ctrl_lock);
1790 fibril_mutex_unlock(&e1000->tx_lock);
1791 fibril_mutex_unlock(&e1000->rx_lock);
1792
1793 return EOK;
1794}
1795
1796/** Callback for NIC_STATE_DOWN change
1797 *
1798 * @param nic NIC driver data
1799 *
1800 * @return EOK if succeed
1801 * @return Error code otherwise
1802 *
1803 */
1804static errno_t e1000_on_down_unlocked(nic_t *nic)
1805{
1806 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1807
1808 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1809 ctrl &= ~CTRL_SLU;
1810 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1811
1812 e1000_disable_tx(e1000);
1813 e1000_disable_rx(e1000);
1814
1815 hw_res_disable_interrupt(e1000->parent_sess, e1000->irq);
1816 e1000_disable_interrupts(e1000);
1817
1818 /*
1819 * Wait for the for the end of all data
1820 * transfers to descriptors.
1821 */
1822 fibril_usleep(100);
1823
1824 return EOK;
1825}
1826
1827/** Callback for NIC_STATE_DOWN change
1828 *
1829 * @param nic NIC driver data
1830 *
1831 * @return EOK if succeed
1832 * @return Error code otherwise
1833 *
1834 */
1835static errno_t e1000_on_down(nic_t *nic)
1836{
1837 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1838
1839 fibril_mutex_lock(&e1000->rx_lock);
1840 fibril_mutex_lock(&e1000->tx_lock);
1841 fibril_mutex_lock(&e1000->ctrl_lock);
1842
1843 errno_t rc = e1000_on_down_unlocked(nic);
1844
1845 fibril_mutex_unlock(&e1000->ctrl_lock);
1846 fibril_mutex_unlock(&e1000->tx_lock);
1847 fibril_mutex_unlock(&e1000->rx_lock);
1848
1849 return rc;
1850}
1851
1852/** Callback for NIC_STATE_STOPPED change
1853 *
1854 * @param nic NIC driver data
1855 *
1856 * @return EOK if succeed
1857 * @return Error code otherwise
1858 *
1859 */
1860static errno_t e1000_on_stopping(nic_t *nic)
1861{
1862 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1863
1864 fibril_mutex_lock(&e1000->rx_lock);
1865 fibril_mutex_lock(&e1000->tx_lock);
1866 fibril_mutex_lock(&e1000->ctrl_lock);
1867
1868 errno_t rc = e1000_on_down_unlocked(nic);
1869 if (rc == EOK)
1870 rc = e1000_reset(nic);
1871
1872 fibril_mutex_unlock(&e1000->ctrl_lock);
1873 fibril_mutex_unlock(&e1000->tx_lock);
1874 fibril_mutex_unlock(&e1000->rx_lock);
1875
1876 return rc;
1877}
1878
1879/** Create driver data structure
1880 *
1881 * @return Intialized device data structure or NULL
1882 *
1883 */
1884static e1000_t *e1000_create_dev_data(ddf_dev_t *dev)
1885{
1886 nic_t *nic = nic_create_and_bind(dev);
1887 if (!nic)
1888 return NULL;
1889
1890 e1000_t *e1000 = malloc(sizeof(e1000_t));
1891 if (!e1000) {
1892 nic_unbind_and_destroy(dev);
1893 return NULL;
1894 }
1895
1896 memset(e1000, 0, sizeof(e1000_t));
1897 e1000->dev = dev;
1898
1899 nic_set_specific(nic, e1000);
1900 nic_set_send_frame_handler(nic, e1000_send_frame);
1901 nic_set_state_change_handlers(nic, e1000_on_activating,
1902 e1000_on_down, e1000_on_stopping);
1903 nic_set_filtering_change_handlers(nic,
1904 e1000_on_unicast_mode_change, e1000_on_multicast_mode_change,
1905 e1000_on_broadcast_mode_change, NULL, e1000_on_vlan_mask_change);
1906 nic_set_poll_handlers(nic, e1000_poll_mode_change, e1000_poll);
1907
1908 fibril_mutex_initialize(&e1000->ctrl_lock);
1909 fibril_mutex_initialize(&e1000->rx_lock);
1910 fibril_mutex_initialize(&e1000->tx_lock);
1911 fibril_mutex_initialize(&e1000->eeprom_lock);
1912
1913 return e1000;
1914}
1915
1916/** Delete driver data structure
1917 *
1918 * @param data E1000 device data structure
1919 *
1920 */
1921inline static void e1000_delete_dev_data(ddf_dev_t *dev)
1922{
1923 assert(dev);
1924
1925 if (ddf_dev_data_get(dev) != NULL)
1926 nic_unbind_and_destroy(dev);
1927}
1928
1929/** Clean up the E1000 device structure.
1930 *
1931 * @param dev Device structure.
1932 *
1933 */
1934static void e1000_dev_cleanup(ddf_dev_t *dev)
1935{
1936 assert(dev);
1937
1938 e1000_delete_dev_data(dev);
1939}
1940
1941/** Fill the irq and io_addr part of device data structure
1942 *
1943 * The hw_resources must be obtained before calling this function
1944 *
1945 * @param dev Device structure
1946 * @param hw_resources Hardware resources obtained from the parent device
1947 *
1948 * @return EOK if succeed
1949 * @return An error code otherwise
1950 *
1951 */
1952static errno_t e1000_fill_resource_info(ddf_dev_t *dev,
1953 const hw_res_list_parsed_t *hw_resources)
1954{
1955 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
1956
1957 if (hw_resources->irqs.count != 1)
1958 return EINVAL;
1959
1960 e1000->irq = hw_resources->irqs.irqs[0];
1961 e1000->reg_base_phys =
1962 MEMADDR_TO_PTR(RNGABS(hw_resources->mem_ranges.ranges[0]));
1963
1964 return EOK;
1965}
1966
1967/** Obtain information about hardware resources of the device
1968 *
1969 * The device must be connected to the parent
1970 *
1971 * @param dev Device structure
1972 *
1973 * @return EOK if succeed
1974 * @return An error code otherwise
1975 *
1976 */
1977static errno_t e1000_get_resource_info(ddf_dev_t *dev)
1978{
1979 assert(dev != NULL);
1980 assert(NIC_DATA_DEV(dev) != NULL);
1981
1982 hw_res_list_parsed_t hw_res_parsed;
1983 hw_res_list_parsed_init(&hw_res_parsed);
1984
1985 /* Get hw resources form parent driver */
1986 errno_t rc = nic_get_resources(NIC_DATA_DEV(dev), &hw_res_parsed);
1987 if (rc != EOK)
1988 return rc;
1989
1990 /* Fill resources information to the device */
1991 rc = e1000_fill_resource_info(dev, &hw_res_parsed);
1992 hw_res_list_parsed_clean(&hw_res_parsed);
1993
1994 return rc;
1995}
1996
1997/** Initialize the E1000 device structure
1998 *
1999 * @param dev Device information
2000 *
2001 * @return EOK if succeed
2002 * @return An error code otherwise
2003 *
2004 */
2005static errno_t e1000_device_initialize(ddf_dev_t *dev)
2006{
2007 /* Allocate driver data for the device. */
2008 e1000_t *e1000 = e1000_create_dev_data(dev);
2009 if (e1000 == NULL) {
2010 ddf_msg(LVL_ERROR, "Unable to allocate device softstate");
2011 return ENOMEM;
2012 }
2013
2014 e1000->parent_sess = ddf_dev_parent_sess_get(dev);
2015 if (e1000->parent_sess == NULL) {
2016 ddf_msg(LVL_ERROR, "Failed connecting parent device.");
2017 return EIO;
2018 }
2019
2020 /* Obtain and fill hardware resources info */
2021 errno_t rc = e1000_get_resource_info(dev);
2022 if (rc != EOK) {
2023 ddf_msg(LVL_ERROR, "Cannot obtain hardware resources");
2024 e1000_dev_cleanup(dev);
2025 return rc;
2026 }
2027
2028 uint16_t device_id;
2029 rc = pci_config_space_read_16(ddf_dev_parent_sess_get(dev), PCI_DEVICE_ID,
2030 &device_id);
2031 if (rc != EOK) {
2032 ddf_msg(LVL_ERROR, "Cannot access PCI configuration space");
2033 e1000_dev_cleanup(dev);
2034 return rc;
2035 }
2036
2037 e1000_board_t board;
2038 switch (device_id) {
2039 case 0x100e:
2040 case 0x1015:
2041 case 0x1016:
2042 case 0x1017:
2043 board = E1000_82540;
2044 break;
2045 case 0x1013:
2046 case 0x1018:
2047 case 0x1078:
2048 board = E1000_82541;
2049 break;
2050 case 0x1076:
2051 case 0x1077:
2052 case 0x107c:
2053 board = E1000_82541REV2;
2054 break;
2055 case 0x100f:
2056 case 0x1011:
2057 case 0x1026:
2058 case 0x1027:
2059 case 0x1028:
2060 board = E1000_82545;
2061 break;
2062 case 0x1010:
2063 case 0x1012:
2064 case 0x101d:
2065 case 0x1079:
2066 case 0x107a:
2067 case 0x107b:
2068 board = E1000_82546;
2069 break;
2070 case 0x1019:
2071 case 0x101a:
2072 board = E1000_82547;
2073 break;
2074 case 0x10b9:
2075 board = E1000_82572;
2076 break;
2077 case 0x1096:
2078 board = E1000_80003ES2;
2079 break;
2080 default:
2081 ddf_msg(LVL_ERROR, "Device not supported (%#" PRIx16 ")",
2082 device_id);
2083 e1000_dev_cleanup(dev);
2084 return ENOTSUP;
2085 }
2086
2087 switch (board) {
2088 case E1000_82540:
2089 case E1000_82541:
2090 case E1000_82541REV2:
2091 case E1000_82545:
2092 case E1000_82546:
2093 e1000->info.eerd_start = 0x01;
2094 e1000->info.eerd_done = 0x10;
2095 e1000->info.eerd_address_offset = 8;
2096 e1000->info.eerd_data_offset = 16;
2097 break;
2098 case E1000_82547:
2099 case E1000_82572:
2100 case E1000_80003ES2:
2101 e1000->info.eerd_start = 0x01;
2102 e1000->info.eerd_done = 0x02;
2103 e1000->info.eerd_address_offset = 2;
2104 e1000->info.eerd_data_offset = 16;
2105 break;
2106 }
2107
2108 return EOK;
2109}
2110
2111/** Enable the I/O ports of the device.
2112 *
2113 * @param dev E1000 device.
2114 *
2115 * @return EOK if successed
2116 * @return An error code otherwise
2117 *
2118 */
2119static errno_t e1000_pio_enable(ddf_dev_t *dev)
2120{
2121 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
2122
2123 errno_t rc = pio_enable(e1000->reg_base_phys, 8 * PAGE_SIZE,
2124 &e1000->reg_base_virt);
2125 if (rc != EOK)
2126 return EADDRNOTAVAIL;
2127
2128 return EOK;
2129}
2130
2131/** Probe and initialize the newly added device.
2132 *
2133 * @param dev E1000 device.
2134 *
2135 */
2136errno_t e1000_dev_add(ddf_dev_t *dev)
2137{
2138 ddf_fun_t *fun;
2139
2140 /* Initialize device structure for E1000 */
2141 errno_t rc = e1000_device_initialize(dev);
2142 if (rc != EOK)
2143 return rc;
2144
2145 /* Device initialization */
2146 nic_t *nic = ddf_dev_data_get(dev);
2147 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2148
2149 /* Map registers */
2150 rc = e1000_pio_enable(dev);
2151 if (rc != EOK)
2152 goto err_destroy;
2153
2154 e1000_initialize_registers(e1000);
2155 rc = e1000_initialize_tx_structure(e1000);
2156 if (rc != EOK)
2157 goto err_pio;
2158
2159 fibril_mutex_lock(&e1000->rx_lock);
2160
2161 e1000_fill_mac_from_eeprom(e1000);
2162 e1000_initialize_filters(e1000);
2163
2164 fibril_mutex_unlock(&e1000->rx_lock);
2165
2166 e1000_initialize_vlan(e1000);
2167
2168 fun = ddf_fun_create(nic_get_ddf_dev(nic), fun_exposed, "port0");
2169 if (fun == NULL)
2170 goto err_tx_structure;
2171 nic_set_ddf_fun(nic, fun);
2172 ddf_fun_set_ops(fun, &e1000_dev_ops);
2173
2174 cap_irq_handle_t irq_handle;
2175 rc = e1000_register_int_handler(nic, &irq_handle);
2176 if (rc != EOK) {
2177 goto err_fun_create;
2178 }
2179
2180 rc = e1000_initialize_rx_structure(nic);
2181 if (rc != EOK)
2182 goto err_irq;
2183
2184 nic_address_t e1000_address;
2185 e1000_get_address(e1000, &e1000_address);
2186 rc = nic_report_address(nic, &e1000_address);
2187 if (rc != EOK)
2188 goto err_rx_structure;
2189
2190 struct timespec period;
2191 period.tv_sec = 0;
2192 period.tv_nsec = USEC2NSEC(E1000_DEFAULT_INTERRUPT_INTERVAL_USEC);
2193 rc = nic_report_poll_mode(nic, NIC_POLL_PERIODIC, &period);
2194 if (rc != EOK)
2195 goto err_rx_structure;
2196
2197 rc = ddf_fun_bind(fun);
2198 if (rc != EOK)
2199 goto err_fun_bind;
2200
2201 rc = ddf_fun_add_to_category(fun, DEVICE_CATEGORY_NIC);
2202 if (rc != EOK)
2203 goto err_add_to_cat;
2204
2205 return EOK;
2206
2207err_add_to_cat:
2208 ddf_fun_unbind(fun);
2209err_fun_bind:
2210err_rx_structure:
2211 e1000_uninitialize_rx_structure(nic);
2212err_irq:
2213 unregister_interrupt_handler(dev, irq_handle);
2214err_fun_create:
2215 ddf_fun_destroy(fun);
2216 nic_set_ddf_fun(nic, NULL);
2217err_tx_structure:
2218 e1000_uninitialize_tx_structure(e1000);
2219err_pio:
2220 // TODO: e1000_pio_disable(dev);
2221err_destroy:
2222 e1000_dev_cleanup(dev);
2223 return rc;
2224}
2225
2226/** Read 16-bit value from EEPROM of E1000 adapter
2227 *
2228 * Read using the EERD register.
2229 *
2230 * @param device E1000 device
2231 * @param eeprom_address 8-bit EEPROM address
2232 *
2233 * @return 16-bit value from EEPROM
2234 *
2235 */
2236static uint16_t e1000_eeprom_read(e1000_t *e1000, uint8_t eeprom_address)
2237{
2238 fibril_mutex_lock(&e1000->eeprom_lock);
2239
2240 /* Write address and START bit to EERD register */
2241 uint32_t write_data = e1000->info.eerd_start |
2242 (((uint32_t) eeprom_address) <<
2243 e1000->info.eerd_address_offset);
2244 E1000_REG_WRITE(e1000, E1000_EERD, write_data);
2245
2246 uint32_t eerd = E1000_REG_READ(e1000, E1000_EERD);
2247 while ((eerd & e1000->info.eerd_done) == 0) {
2248 fibril_usleep(1);
2249 eerd = E1000_REG_READ(e1000, E1000_EERD);
2250 }
2251
2252 fibril_mutex_unlock(&e1000->eeprom_lock);
2253
2254 return (uint16_t) (eerd >> e1000->info.eerd_data_offset);
2255}
2256
2257/** Get MAC address of the E1000 adapter
2258 *
2259 * @param device E1000 device
2260 * @param address Place to store the address
2261 * @param max_len Maximal addresss length to store
2262 *
2263 * @return EOK if succeed
2264 * @return An error code otherwise
2265 *
2266 */
2267static errno_t e1000_get_address(e1000_t *e1000, nic_address_t *address)
2268{
2269 fibril_mutex_lock(&e1000->rx_lock);
2270
2271 uint8_t *mac0_dest = (uint8_t *) address->address;
2272 uint8_t *mac1_dest = (uint8_t *) address->address + 1;
2273 uint8_t *mac2_dest = (uint8_t *) address->address + 2;
2274 uint8_t *mac3_dest = (uint8_t *) address->address + 3;
2275 uint8_t *mac4_dest = (uint8_t *) address->address + 4;
2276 uint8_t *mac5_dest = (uint8_t *) address->address + 5;
2277
2278 uint32_t rah = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
2279 uint32_t ral = E1000_REG_READ(e1000, E1000_RAL_ARRAY(0));
2280
2281 *mac0_dest = (uint8_t) ral;
2282 *mac1_dest = (uint8_t) (ral >> 8);
2283 *mac2_dest = (uint8_t) (ral >> 16);
2284 *mac3_dest = (uint8_t) (ral >> 24);
2285 *mac4_dest = (uint8_t) rah;
2286 *mac5_dest = (uint8_t) (rah >> 8);
2287
2288 fibril_mutex_unlock(&e1000->rx_lock);
2289 return EOK;
2290}
2291
2292/** Set card MAC address
2293 *
2294 * @param device E1000 device
2295 * @param address Address
2296 *
2297 * @return EOK if succeed
2298 * @return An error code otherwise
2299 */
2300static errno_t e1000_set_addr(ddf_fun_t *fun, const nic_address_t *addr)
2301{
2302 nic_t *nic = NIC_DATA_FUN(fun);
2303 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2304
2305 fibril_mutex_lock(&e1000->rx_lock);
2306 fibril_mutex_lock(&e1000->tx_lock);
2307
2308 errno_t rc = nic_report_address(nic, addr);
2309 if (rc == EOK)
2310 e1000_write_receive_address(e1000, 0, addr, false);
2311
2312 fibril_mutex_unlock(&e1000->tx_lock);
2313 fibril_mutex_unlock(&e1000->rx_lock);
2314
2315 return rc;
2316}
2317
2318static void e1000_eeprom_get_address(e1000_t *e1000,
2319 nic_address_t *address)
2320{
2321 uint16_t *mac0_dest = (uint16_t *) address->address;
2322 uint16_t *mac2_dest = (uint16_t *) (address->address + 2);
2323 uint16_t *mac4_dest = (uint16_t *) (address->address + 4);
2324
2325 *mac0_dest = e1000_eeprom_read(e1000, 0);
2326 *mac2_dest = e1000_eeprom_read(e1000, 1);
2327 *mac4_dest = e1000_eeprom_read(e1000, 2);
2328}
2329
2330/** Send frame
2331 *
2332 * @param nic NIC driver data structure
2333 * @param data Frame data
2334 * @param size Frame size in bytes
2335 *
2336 * @return EOK if succeed
2337 * @return Error code in the case of error
2338 *
2339 */
2340static void e1000_send_frame(nic_t *nic, void *data, size_t size)
2341{
2342 assert(nic);
2343
2344 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2345 fibril_mutex_lock(&e1000->tx_lock);
2346
2347 uint32_t tdt = E1000_REG_READ(e1000, E1000_TDT);
2348 e1000_tx_descriptor_t *tx_descriptor_addr = (e1000_tx_descriptor_t *)
2349 (e1000->tx_ring_virt + tdt * sizeof(e1000_tx_descriptor_t));
2350
2351 bool descriptor_available = false;
2352
2353 /* Descriptor never used */
2354 if (tx_descriptor_addr->length == 0)
2355 descriptor_available = true;
2356
2357 /* Descriptor done */
2358 if (tx_descriptor_addr->status & TXDESCRIPTOR_STATUS_DD)
2359 descriptor_available = true;
2360
2361 if (!descriptor_available) {
2362 /* Frame lost */
2363 fibril_mutex_unlock(&e1000->tx_lock);
2364 return;
2365 }
2366
2367 memcpy(e1000->tx_frame_virt[tdt], data, size);
2368
2369 tx_descriptor_addr->phys_addr = PTR_TO_U64(e1000->tx_frame_phys[tdt]);
2370 tx_descriptor_addr->length = size;
2371
2372 /*
2373 * Report status to STATUS.DD (descriptor done),
2374 * add ethernet CRC, end of packet.
2375 */
2376 tx_descriptor_addr->command = TXDESCRIPTOR_COMMAND_RS |
2377 TXDESCRIPTOR_COMMAND_IFCS |
2378 TXDESCRIPTOR_COMMAND_EOP;
2379
2380 tx_descriptor_addr->checksum_offset = 0;
2381 tx_descriptor_addr->status = 0;
2382 if (e1000->vlan_tag_add) {
2383 tx_descriptor_addr->special = e1000->vlan_tag;
2384 tx_descriptor_addr->command |= TXDESCRIPTOR_COMMAND_VLE;
2385 } else
2386 tx_descriptor_addr->special = 0;
2387
2388 tx_descriptor_addr->checksum_start_field = 0;
2389
2390 tdt++;
2391 if (tdt == E1000_TX_FRAME_COUNT)
2392 tdt = 0;
2393
2394 E1000_REG_WRITE(e1000, E1000_TDT, tdt);
2395
2396 fibril_mutex_unlock(&e1000->tx_lock);
2397}
2398
2399int main(void)
2400{
2401 printf("%s: HelenOS E1000 network adapter driver\n", NAME);
2402
2403 if (nic_driver_init(NAME) != EOK)
2404 return 1;
2405
2406 nic_driver_implement(&e1000_driver_ops, &e1000_dev_ops,
2407 &e1000_nic_iface);
2408
2409 ddf_log_init(NAME);
2410 return ddf_driver_main(&e1000_driver);
2411}
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