source: mainline/uspace/drv/nic/e1k/e1k.c@ 9ce251c7

Last change on this file since 9ce251c7 was 9ce251c7, checked in by Nataliia Korop <n.corop08@…>, 10 months ago

moved to nic, fixed all except addressing

  • Property mode set to 100644
File size: 56.5 KB
RevLine 
[bf84871]1/*
2 * Copyright (c) 2011 Zdenek Bouska
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[1df224c]29/** @file e1k.c
30 *
31 * Driver for Intel Pro/1000 8254x Family of Gigabit Ethernet Controllers
[bf84871]32 *
33 */
34
[f300523]35#include <async.h>
[bf84871]36#include <assert.h>
37#include <stdio.h>
38#include <errno.h>
39#include <adt/list.h>
40#include <align.h>
41#include <byteorder.h>
42#include <as.h>
[869d936]43#include <ddi.h>
[77c2b02]44#include <ddf/log.h>
[bf84871]45#include <ddf/interrupt.h>
[d51838f]46#include <device/hw_res.h>
[bf84871]47#include <device/hw_res_parsed.h>
[99e8fb7b]48#include <pci_dev_iface.h>
[bf84871]49#include <nic.h>
50#include <ops/nic.h>
[9ce251c7]51#include <pcapdump_iface.h>
[1df224c]52#include "e1k.h"
[bf84871]53
[1df224c]54#define NAME "e1k"
[bf84871]55
[9916841]56#define E1000_DEFAULT_INTERRUPT_INTERVAL_USEC 250
[bf84871]57
[ee7f78a]58/* Must be power of 8 */
59#define E1000_RX_FRAME_COUNT 128
60#define E1000_TX_FRAME_COUNT 128
[bf84871]61
[1df224c]62#define E1000_RECEIVE_ADDRESS 16
[bf84871]63
[1bc35b5]64/** Maximum sending frame size */
[6d8455d]65#define E1000_MAX_SEND_FRAME_SIZE 2048
[321052f7]66/** Maximum receiving frame size */
[1bc35b5]67#define E1000_MAX_RECEIVE_FRAME_SIZE 2048
[bf84871]68
69/** nic_driver_data_t* -> e1000_t* cast */
[c4be33a]70#define DRIVER_DATA_NIC(nic) \
71 ((e1000_t *) nic_get_specific(nic))
[1df224c]72
[56fd7cf]73/** ddf_fun_t * -> nic_driver_data_t* cast */
74#define NIC_DATA_FUN(fun) \
[7eb6c96]75 ((nic_t *) ddf_dev_data_get(ddf_fun_get_dev(fun)))
[56fd7cf]76
77/** ddf_dev_t * -> nic_driver_data_t* cast */
[1df224c]78#define NIC_DATA_DEV(dev) \
[56fd7cf]79 ((nic_t *) ddf_dev_data_get(dev))
[1df224c]80
[56fd7cf]81/** ddf_dev_t * -> e1000_t* cast */
[1df224c]82#define DRIVER_DATA_DEV(dev) \
83 (DRIVER_DATA_NIC(NIC_DATA_DEV(dev)))
[bf84871]84
[56fd7cf]85/** ddf_fun_t * -> e1000_t* cast */
86#define DRIVER_DATA_FUN(fun) \
87 (DRIVER_DATA_NIC(NIC_DATA_FUN(fun)))
88
[1df224c]89/** Cast pointer to uint64_t
90 *
91 * @param ptr Pointer to cast
92 *
93 * @return The uint64_t pointer representation.
[bf84871]94 *
95 */
[1df224c]96#define PTR_TO_U64(ptr) ((uint64_t) ((uintptr_t) (ptr)))
[bf84871]97
98/** Cast the memaddr part to the void*
99 *
[1df224c]100 * @param memaddr The memaddr value
101 *
[bf84871]102 */
[1df224c]103#define MEMADDR_TO_PTR(memaddr) ((void *) ((size_t) (memaddr)))
104
[c4be33a]105#define E1000_REG_BASE(e1000) \
106 ((e1000)->reg_base_virt)
[bf84871]107
[c4be33a]108#define E1000_REG_ADDR(e1000, reg) \
109 ((uint32_t *) (E1000_REG_BASE(e1000) + reg))
[bf84871]110
[c4be33a]111#define E1000_REG_READ(e1000, reg) \
112 (pio_read_32(E1000_REG_ADDR(e1000, reg)))
[1df224c]113
[c4be33a]114#define E1000_REG_WRITE(e1000, reg, value) \
115 (pio_write_32(E1000_REG_ADDR(e1000, reg), value))
[bf84871]116
117/** E1000 device data */
[c4be33a]118typedef struct {
[d51838f]119 /** DDF device */
120 ddf_dev_t *dev;
121 /** Parent session */
122 async_sess_t *parent_sess;
[77c2b02]123 /** Device configuration */
124 e1000_info_t info;
[a35b458]125
[bf84871]126 /** Physical registers base address */
[c4be33a]127 void *reg_base_phys;
[bf84871]128 /** Virtual registers base address */
[c4be33a]129 void *reg_base_virt;
[a35b458]130
[c4be33a]131 /** Physical tx ring address */
[8442d10]132 uintptr_t tx_ring_phys;
[c4be33a]133 /** Virtual tx ring address */
134 void *tx_ring_virt;
[a35b458]135
[6d8455d]136 /** Ring of TX frames, physical address */
[8442d10]137 uintptr_t *tx_frame_phys;
[6d8455d]138 /** Ring of TX frames, virtual address */
139 void **tx_frame_virt;
[a35b458]140
[c4be33a]141 /** Physical rx ring address */
[8442d10]142 uintptr_t rx_ring_phys;
[c4be33a]143 /** Virtual rx ring address */
144 void *rx_ring_virt;
[a35b458]145
[1bc35b5]146 /** Ring of RX frames, physical address */
[8442d10]147 uintptr_t *rx_frame_phys;
[1bc35b5]148 /** Ring of RX frames, virtual address */
149 void **rx_frame_virt;
[a35b458]150
[bf84871]151 /** VLAN tag */
152 uint16_t vlan_tag;
[a35b458]153
[1bc35b5]154 /** Add VLAN tag to frame */
[1df224c]155 bool vlan_tag_add;
[a35b458]156
[bf84871]157 /** Used unicast Receive Address count */
158 unsigned int unicast_ra_count;
[a35b458]159
[1df224c]160 /** Used milticast Receive addrress count */
[bf84871]161 unsigned int multicast_ra_count;
[a35b458]162
[bf84871]163 /** The irq assigned */
164 int irq;
[a35b458]165
[bf84871]166 /** Lock for CTRL register */
167 fibril_mutex_t ctrl_lock;
[a35b458]168
[bf84871]169 /** Lock for receiver */
170 fibril_mutex_t rx_lock;
[a35b458]171
[bf84871]172 /** Lock for transmitter */
173 fibril_mutex_t tx_lock;
[a35b458]174
[bf84871]175 /** Lock for EEPROM access */
176 fibril_mutex_t eeprom_lock;
[17a8fcf]177
[bf84871]178} e1000_t;
179
180/** Global mutex for work with shared irq structure */
181FIBRIL_MUTEX_INITIALIZE(irq_reg_mutex);
182
[b7fd2a0]183static errno_t e1000_get_address(e1000_t *, nic_address_t *);
[1df224c]184static void e1000_eeprom_get_address(e1000_t *, nic_address_t *);
[b7fd2a0]185static errno_t e1000_set_addr(ddf_fun_t *, const nic_address_t *);
[bf84871]186
[b7fd2a0]187static errno_t e1000_defective_get_mode(ddf_fun_t *, uint32_t *);
188static errno_t e1000_defective_set_mode(ddf_fun_t *, uint32_t);
[bf84871]189
[b7fd2a0]190static errno_t e1000_get_cable_state(ddf_fun_t *, nic_cable_state_t *);
191static errno_t e1000_get_device_info(ddf_fun_t *, nic_device_info_t *);
192static errno_t e1000_get_operation_mode(ddf_fun_t *, int *,
[1df224c]193 nic_channel_mode_t *, nic_role_t *);
[b7fd2a0]194static errno_t e1000_set_operation_mode(ddf_fun_t *, int,
[1df224c]195 nic_channel_mode_t, nic_role_t);
[b7fd2a0]196static errno_t e1000_autoneg_enable(ddf_fun_t *, uint32_t);
197static errno_t e1000_autoneg_disable(ddf_fun_t *);
198static errno_t e1000_autoneg_restart(ddf_fun_t *);
[bf84871]199
[b7fd2a0]200static errno_t e1000_vlan_set_tag(ddf_fun_t *, uint16_t, bool, bool);
[bf84871]201
202/** Network interface options for E1000 card driver */
203static nic_iface_t e1000_nic_iface;
204
205/** Network interface options for E1000 card driver */
206static nic_iface_t e1000_nic_iface = {
207 .set_address = &e1000_set_addr,
208 .get_device_info = &e1000_get_device_info,
209 .get_cable_state = &e1000_get_cable_state,
210 .get_operation_mode = &e1000_get_operation_mode,
211 .set_operation_mode = &e1000_set_operation_mode,
212 .autoneg_enable = &e1000_autoneg_enable,
213 .autoneg_disable = &e1000_autoneg_disable,
214 .autoneg_restart = &e1000_autoneg_restart,
215 .vlan_set_tag = &e1000_vlan_set_tag,
216 .defective_get_mode = &e1000_defective_get_mode,
217 .defective_set_mode = &e1000_defective_set_mode,
218};
219
220/** Basic device operations for E1000 driver */
221static ddf_dev_ops_t e1000_dev_ops;
222
[b7fd2a0]223static errno_t e1000_dev_add(ddf_dev_t *);
[bf84871]224
225/** Basic driver operations for E1000 driver */
226static driver_ops_t e1000_driver_ops = {
[9916841]227 .dev_add = e1000_dev_add
[bf84871]228};
229
230/** Driver structure for E1000 driver */
231static driver_t e1000_driver = {
232 .name = NAME,
233 .driver_ops = &e1000_driver_ops
234};
235
236/* The default implementation callbacks */
[b7fd2a0]237static errno_t e1000_on_activating(nic_t *);
238static errno_t e1000_on_stopping(nic_t *);
[6d8455d]239static void e1000_send_frame(nic_t *, void *, size_t);
[bf84871]240
[ec52752]241/** PIO ranges used in the IRQ code. */
242irq_pio_range_t e1000_irq_pio_ranges[] = {
243 {
244 .base = 0,
245 .size = PAGE_SIZE, /* XXX */
246 }
247};
248
[bf84871]249/** Commands to deal with interrupt
250 *
251 */
252irq_cmd_t e1000_irq_commands[] = {
[1df224c]253 {
254 /* Get the interrupt status */
255 .cmd = CMD_PIO_READ_32,
256 .addr = NULL,
257 .dstarg = 2
258 },
[807be7e]259 {
260 .cmd = CMD_AND,
261 .value = ICR_RXT0,
262 .srcarg = 2,
263 .dstarg = 1
264 },
[1df224c]265 {
266 .cmd = CMD_PREDICATE,
267 .value = 2,
[807be7e]268 .srcarg = 1
[1df224c]269 },
270 {
271 /* Disable interrupts until interrupt routine is finished */
272 .cmd = CMD_PIO_WRITE_32,
273 .addr = NULL,
[c4be33a]274 .value = 0xffffffff
[1df224c]275 },
276 {
277 .cmd = CMD_ACCEPT
278 }
[bf84871]279};
280
281/** Interrupt code definition */
282irq_code_t e1000_irq_code = {
[ec52752]283 .rangecount = sizeof(e1000_irq_pio_ranges) /
284 sizeof(irq_pio_range_t),
285 .ranges = e1000_irq_pio_ranges,
[1df224c]286 .cmdcount = sizeof(e1000_irq_commands) / sizeof(irq_cmd_t),
[bf84871]287 .cmds = e1000_irq_commands
288};
289
290/** Get the device information
291 *
[1df224c]292 * @param dev NIC device
293 * @param info Information to fill
294 *
295 * @return EOK
296 *
[bf84871]297 */
[b7fd2a0]298static errno_t e1000_get_device_info(ddf_fun_t *dev, nic_device_info_t *info)
[bf84871]299{
300 assert(dev);
301 assert(info);
[a35b458]302
[acdb5bac]303 memset(info, 0, sizeof(nic_device_info_t));
[a35b458]304
[1df224c]305 info->vendor_id = 0x8086;
306 str_cpy(info->vendor_name, NIC_VENDOR_MAX_LENGTH,
307 "Intel Corporation");
308 str_cpy(info->model_name, NIC_MODEL_MAX_LENGTH,
309 "Intel Pro");
[a35b458]310
[bf84871]311 info->ethernet_support[ETH_10M] = ETH_10BASE_T;
312 info->ethernet_support[ETH_100M] = ETH_100BASE_TX;
313 info->ethernet_support[ETH_1000M] = ETH_1000BASE_T;
[a35b458]314
[bf84871]315 return EOK;
316}
317
318/** Check the cable state
319 *
[1df224c]320 * @param[in] dev device
321 * @param[out] state state to fill
322 *
323 * @return EOK
324 *
[bf84871]325 */
[b7fd2a0]326static errno_t e1000_get_cable_state(ddf_fun_t *fun, nic_cable_state_t *state)
[bf84871]327{
[56fd7cf]328 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
[c4be33a]329 if (E1000_REG_READ(e1000, E1000_STATUS) & (STATUS_LU))
[bf84871]330 *state = NIC_CS_PLUGGED;
[1df224c]331 else
[bf84871]332 *state = NIC_CS_UNPLUGGED;
[a35b458]333
[bf84871]334 return EOK;
335}
336
[bd41ac52]337static uint16_t e1000_calculate_itr_interval_from_usecs(usec_t useconds)
[1df224c]338{
[bf84871]339 return useconds * 4;
340}
341
342/** Get operation mode of the device
[1df224c]343 *
[bf84871]344 */
[b7fd2a0]345static errno_t e1000_get_operation_mode(ddf_fun_t *fun, int *speed,
[bf84871]346 nic_channel_mode_t *duplex, nic_role_t *role)
347{
[56fd7cf]348 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
[c4be33a]349 uint32_t status = E1000_REG_READ(e1000, E1000_STATUS);
[a35b458]350
[1df224c]351 if (status & STATUS_FD)
[bf84871]352 *duplex = NIC_CM_FULL_DUPLEX;
[1df224c]353 else
[bf84871]354 *duplex = NIC_CM_HALF_DUPLEX;
[a35b458]355
[1df224c]356 uint32_t speed_bits =
357 (status >> STATUS_SPEED_SHIFT) & STATUS_SPEED_ALL;
[a35b458]358
[1df224c]359 if (speed_bits == STATUS_SPEED_10)
[bf84871]360 *speed = 10;
[1df224c]361 else if (speed_bits == STATUS_SPEED_100)
[bf84871]362 *speed = 100;
[1df224c]363 else if ((speed_bits == STATUS_SPEED_1000A) ||
364 (speed_bits == STATUS_SPEED_1000B))
[bf84871]365 *speed = 1000;
[a35b458]366
[bf84871]367 *role = NIC_ROLE_UNKNOWN;
368 return EOK;
369}
370
[c4be33a]371static void e1000_link_restart(e1000_t *e1000)
[bf84871]372{
[c4be33a]373 fibril_mutex_lock(&e1000->ctrl_lock);
[a35b458]374
[c4be33a]375 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
[a35b458]376
[bf84871]377 if (ctrl & CTRL_SLU) {
378 ctrl &= ~(CTRL_SLU);
[8974294]379 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
[c4be33a]380 fibril_mutex_unlock(&e1000->ctrl_lock);
[a35b458]381
[5f97ef44]382 fibril_usleep(10);
[a35b458]383
[c4be33a]384 fibril_mutex_lock(&e1000->ctrl_lock);
[8974294]385 ctrl = E1000_REG_READ(e1000, E1000_CTRL);
[bf84871]386 ctrl |= CTRL_SLU;
[8974294]387 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
[bf84871]388 }
[a35b458]389
[c4be33a]390 fibril_mutex_unlock(&e1000->ctrl_lock);
[bf84871]391}
392
393/** Set operation mode of the device
394 *
395 */
[b7fd2a0]396static errno_t e1000_set_operation_mode(ddf_fun_t *fun, int speed,
[bf84871]397 nic_channel_mode_t duplex, nic_role_t role)
398{
[1df224c]399 if ((speed != 10) && (speed != 100) && (speed != 1000))
[bf84871]400 return EINVAL;
[a35b458]401
[1df224c]402 if ((duplex != NIC_CM_HALF_DUPLEX) && (duplex != NIC_CM_FULL_DUPLEX))
[bf84871]403 return EINVAL;
[a35b458]404
[56fd7cf]405 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
[a35b458]406
[c4be33a]407 fibril_mutex_lock(&e1000->ctrl_lock);
408 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
[a35b458]409
[bf84871]410 ctrl |= CTRL_FRCSPD;
411 ctrl |= CTRL_FRCDPLX;
412 ctrl &= ~(CTRL_ASDE);
[a35b458]413
[1df224c]414 if (duplex == NIC_CM_FULL_DUPLEX)
[bf84871]415 ctrl |= CTRL_FD;
[1df224c]416 else
[bf84871]417 ctrl &= ~(CTRL_FD);
[a35b458]418
[bf84871]419 ctrl &= ~(CTRL_SPEED_MASK);
[1df224c]420 if (speed == 1000)
[bf84871]421 ctrl |= CTRL_SPEED_1000 << CTRL_SPEED_SHIFT;
[1df224c]422 else if (speed == 100)
[bf84871]423 ctrl |= CTRL_SPEED_100 << CTRL_SPEED_SHIFT;
[1df224c]424 else
[bf84871]425 ctrl |= CTRL_SPEED_10 << CTRL_SPEED_SHIFT;
[a35b458]426
[c4be33a]427 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
[a35b458]428
[c4be33a]429 fibril_mutex_unlock(&e1000->ctrl_lock);
[a35b458]430
[c4be33a]431 e1000_link_restart(e1000);
[a35b458]432
[bf84871]433 return EOK;
434}
435
[1df224c]436/** Enable auto-negotiation
437 *
438 * @param dev Device to update
439 * @param advertisement Ignored on E1000
440 *
441 * @return EOK if advertisement mode set successfully
[bf84871]442 *
443 */
[b7fd2a0]444static errno_t e1000_autoneg_enable(ddf_fun_t *fun, uint32_t advertisement)
[bf84871]445{
[56fd7cf]446 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
[a35b458]447
[c4be33a]448 fibril_mutex_lock(&e1000->ctrl_lock);
[a35b458]449
[c4be33a]450 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
[a35b458]451
[bf84871]452 ctrl &= ~(CTRL_FRCSPD);
453 ctrl &= ~(CTRL_FRCDPLX);
454 ctrl |= CTRL_ASDE;
[a35b458]455
[c4be33a]456 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
[a35b458]457
[c4be33a]458 fibril_mutex_unlock(&e1000->ctrl_lock);
[a35b458]459
[c4be33a]460 e1000_link_restart(e1000);
[a35b458]461
[bf84871]462 return EOK;
463}
464
[1df224c]465/** Disable auto-negotiation
466 *
467 * @param dev Device to update
468 *
469 * @return EOK
[bf84871]470 *
471 */
[b7fd2a0]472static errno_t e1000_autoneg_disable(ddf_fun_t *fun)
[bf84871]473{
[56fd7cf]474 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
[a35b458]475
[c4be33a]476 fibril_mutex_lock(&e1000->ctrl_lock);
[a35b458]477
[c4be33a]478 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
[a35b458]479
[bf84871]480 ctrl |= CTRL_FRCSPD;
481 ctrl |= CTRL_FRCDPLX;
482 ctrl &= ~(CTRL_ASDE);
[a35b458]483
[c4be33a]484 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
[a35b458]485
[c4be33a]486 fibril_mutex_unlock(&e1000->ctrl_lock);
[a35b458]487
[c4be33a]488 e1000_link_restart(e1000);
[a35b458]489
[bf84871]490 return EOK;
491}
492
[1df224c]493/** Restart auto-negotiation
494 *
495 * @param dev Device to update
496 *
497 * @return EOK if advertisement mode set successfully
[bf84871]498 *
499 */
[b7fd2a0]500static errno_t e1000_autoneg_restart(ddf_fun_t *dev)
[bf84871]501{
502 return e1000_autoneg_enable(dev, 0);
503}
504
[1bc35b5]505/** Get state of acceptance of weird frames
[bf84871]506 *
[1df224c]507 * @param device Device to check
508 * @param[out] mode Current mode
509 *
[bf84871]510 */
[b7fd2a0]511static errno_t e1000_defective_get_mode(ddf_fun_t *fun, uint32_t *mode)
[bf84871]512{
[56fd7cf]513 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
[a35b458]514
[bf84871]515 *mode = 0;
[c4be33a]516 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
[1df224c]517 if (rctl & RCTL_SBP)
[bf84871]518 *mode = NIC_DEFECTIVE_BAD_CRC | NIC_DEFECTIVE_SHORT;
[a35b458]519
[bf84871]520 return EOK;
[850fd32]521}
[bf84871]522
[1bc35b5]523/** Set acceptance of weird frames
[bf84871]524 *
[1df224c]525 * @param device Device to update
526 * @param mode Mode to set
527 *
528 * @return ENOTSUP if the mode is not supported
529 * @return EOK of mode was set
530 *
[bf84871]531 */
[b7fd2a0]532static errno_t e1000_defective_set_mode(ddf_fun_t *fun, uint32_t mode)
[bf84871]533{
[56fd7cf]534 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
[b7fd2a0]535 errno_t rc = EOK;
[a35b458]536
[c4be33a]537 fibril_mutex_lock(&e1000->rx_lock);
[a35b458]538
[c4be33a]539 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
[bf84871]540 bool short_mode = (mode & NIC_DEFECTIVE_SHORT ? true : false);
541 bool bad_mode = (mode & NIC_DEFECTIVE_BAD_CRC ? true : false);
[a35b458]542
[1df224c]543 if (short_mode && bad_mode)
[bf84871]544 rctl |= RCTL_SBP;
[1df224c]545 else if ((!short_mode) && (!bad_mode))
[bf84871]546 rctl &= ~RCTL_SBP;
[1df224c]547 else
[bf84871]548 rc = ENOTSUP;
[a35b458]549
[c4be33a]550 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
[a35b458]551
[c4be33a]552 fibril_mutex_unlock(&e1000->rx_lock);
[bf84871]553 return rc;
[84239b1]554}
[bf84871]555
556/** Write receive address to RA registr
557 *
[c4be33a]558 * @param e1000 E1000 data structure
[1df224c]559 * @param position RA register position
560 * @param address Ethernet address
561 * @param set_av_bit Set the Addtess Valid bit
562 *
[bf84871]563 */
[c4be33a]564static void e1000_write_receive_address(e1000_t *e1000, unsigned int position,
[3bacee1]565 const nic_address_t *address, bool set_av_bit)
[1df224c]566{
567 uint8_t *mac0 = (uint8_t *) address->address;
568 uint8_t *mac1 = (uint8_t *) address->address + 1;
569 uint8_t *mac2 = (uint8_t *) address->address + 2;
570 uint8_t *mac3 = (uint8_t *) address->address + 3;
571 uint8_t *mac4 = (uint8_t *) address->address + 4;
572 uint8_t *mac5 = (uint8_t *) address->address + 5;
[a35b458]573
[bf84871]574 uint32_t rah;
575 uint32_t ral;
[a35b458]576
[bf84871]577 ral = ((*mac3) << 24) | ((*mac2) << 16) | ((*mac1) << 8) | (*mac0);
578 rah = ((*mac5) << 8) | ((*mac4));
[a35b458]579
[1df224c]580 if (set_av_bit)
[bf84871]581 rah |= RAH_AV;
[1df224c]582 else
[c4be33a]583 rah |= E1000_REG_READ(e1000, E1000_RAH_ARRAY(position)) & RAH_AV;
[a35b458]584
[c4be33a]585 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(position), rah);
586 E1000_REG_WRITE(e1000, E1000_RAL_ARRAY(position), ral);
[bf84871]587}
588
589/** Disable receive address in RA registr
590 *
[1df224c]591 * Clear Address Valid bit
592 *
[c4be33a]593 * @param e1000 E1000 data structure
594 * @param position RA register position
[1df224c]595 *
[bf84871]596 */
[c4be33a]597static void e1000_disable_receive_address(e1000_t *e1000, unsigned int position)
[bf84871]598{
[c4be33a]599 uint32_t rah = E1000_REG_READ(e1000, E1000_RAH_ARRAY(position));
[bf84871]600 rah = rah & ~RAH_AV;
[c4be33a]601 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(position), rah);
[bf84871]602}
603
[1df224c]604/** Clear all unicast addresses from RA registers
605 *
[c4be33a]606 * @param e1000 E1000 data structure
[bf84871]607 *
608 */
[c4be33a]609static void e1000_clear_unicast_receive_addresses(e1000_t *e1000)
[bf84871]610{
[1df224c]611 for (unsigned int ra_num = 1;
[c4be33a]612 ra_num <= e1000->unicast_ra_count;
[1df224c]613 ra_num++)
[c4be33a]614 e1000_disable_receive_address(e1000, ra_num);
[a35b458]615
[c4be33a]616 e1000->unicast_ra_count = 0;
[bf84871]617}
618
[1df224c]619/** Clear all multicast addresses from RA registers
620 *
[c4be33a]621 * @param e1000 E1000 data structure
[bf84871]622 *
623 */
[c4be33a]624static void e1000_clear_multicast_receive_addresses(e1000_t *e1000)
[bf84871]625{
[1df224c]626 unsigned int first_multicast_ra_num =
[c4be33a]627 E1000_RECEIVE_ADDRESS - e1000->multicast_ra_count;
[a35b458]628
[1df224c]629 for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1;
630 ra_num >= first_multicast_ra_num;
631 ra_num--)
[c4be33a]632 e1000_disable_receive_address(e1000, ra_num);
[a35b458]633
[c4be33a]634 e1000->multicast_ra_count = 0;
[bf84871]635}
636
[1df224c]637/** Return receive address filter positions count usable for unicast
638 *
[c4be33a]639 * @param e1000 E1000 data structure
[bf84871]640 *
641 * @return receive address filter positions count usable for unicast
[1df224c]642 *
[bf84871]643 */
[c4be33a]644static unsigned int get_free_unicast_address_count(e1000_t *e1000)
[bf84871]645{
[c4be33a]646 return E1000_RECEIVE_ADDRESS - 1 - e1000->multicast_ra_count;
[bf84871]647}
648
[1df224c]649/** Return receive address filter positions count usable for multicast
650 *
[c4be33a]651 * @param e1000 E1000 data structure
[bf84871]652 *
653 * @return receive address filter positions count usable for multicast
[1df224c]654 *
[bf84871]655 */
[c4be33a]656static unsigned int get_free_multicast_address_count(e1000_t *e1000)
[bf84871]657{
[c4be33a]658 return E1000_RECEIVE_ADDRESS - 1 - e1000->unicast_ra_count;
[bf84871]659}
660
[1df224c]661/** Write unicast receive addresses to receive address filter registers
662 *
[c4be33a]663 * @param e1000 E1000 data structure
664 * @param addr Pointer to address array
665 * @param addr_cnt Address array count
[bf84871]666 *
667 */
[c4be33a]668static void e1000_add_unicast_receive_addresses(e1000_t *e1000,
[1df224c]669 const nic_address_t *addr, size_t addr_cnt)
[bf84871]670{
[c4be33a]671 assert(addr_cnt <= get_free_unicast_address_count(e1000));
[a35b458]672
[1df224c]673 nic_address_t *addr_iterator = (nic_address_t *) addr;
[a35b458]674
[1df224c]675 /* ra_num = 0 is primary address */
676 for (unsigned int ra_num = 1;
677 ra_num <= addr_cnt;
678 ra_num++) {
[c4be33a]679 e1000_write_receive_address(e1000, ra_num, addr_iterator, true);
[bf84871]680 addr_iterator++;
681 }
682}
683
[1df224c]684/** Write multicast receive addresses to receive address filter registers
685 *
[c4be33a]686 * @param e1000 E1000 data structure
687 * @param addr Pointer to address array
688 * @param addr_cnt Address array count
[bf84871]689 *
690 */
[c4be33a]691static void e1000_add_multicast_receive_addresses(e1000_t *e1000,
[1df224c]692 const nic_address_t *addr, size_t addr_cnt)
[bf84871]693{
[c4be33a]694 assert(addr_cnt <= get_free_multicast_address_count(e1000));
[a35b458]695
[1df224c]696 nic_address_t *addr_iterator = (nic_address_t *) addr;
[a35b458]697
[bf84871]698 unsigned int first_multicast_ra_num = E1000_RECEIVE_ADDRESS - addr_cnt;
[1df224c]699 for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1;
700 ra_num >= first_multicast_ra_num;
[9916841]701 ra_num--) {
[c4be33a]702 e1000_write_receive_address(e1000, ra_num, addr_iterator, true);
[bf84871]703 addr_iterator++;
704 }
705}
706
[1bc35b5]707/** Disable receiving frames for default address
[1df224c]708 *
[c4be33a]709 * @param e1000 E1000 data structure
[bf84871]710 *
711 */
[c4be33a]712static void disable_ra0_address_filter(e1000_t *e1000)
[bf84871]713{
[c4be33a]714 uint32_t rah0 = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
[bf84871]715 rah0 = rah0 & ~RAH_AV;
[c4be33a]716 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(0), rah0);
[bf84871]717}
718
[1bc35b5]719/** Enable receiving frames for default address
[1df224c]720 *
[c4be33a]721 * @param e1000 E1000 data structure
[bf84871]722 *
723 */
[c4be33a]724static void enable_ra0_address_filter(e1000_t *e1000)
[bf84871]725{
[c4be33a]726 uint32_t rah0 = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
[bf84871]727 rah0 = rah0 | RAH_AV;
[c4be33a]728 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(0), rah0);
[bf84871]729}
730
[1df224c]731/** Disable unicast promiscuous mode
732 *
[c4be33a]733 * @param e1000 E1000 data structure
[bf84871]734 *
735 */
[c4be33a]736static void e1000_disable_unicast_promisc(e1000_t *e1000)
[bf84871]737{
[c4be33a]738 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
[bf84871]739 rctl = rctl & ~RCTL_UPE;
[c4be33a]740 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
[bf84871]741}
742
[1df224c]743/** Enable unicast promiscuous mode
744 *
[c4be33a]745 * @param e1000 E1000 data structure
[bf84871]746 *
747 */
[c4be33a]748static void e1000_enable_unicast_promisc(e1000_t *e1000)
[bf84871]749{
[c4be33a]750 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
[bf84871]751 rctl = rctl | RCTL_UPE;
[c4be33a]752 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
[bf84871]753}
754
[1df224c]755/** Disable multicast promiscuous mode
756 *
[c4be33a]757 * @param e1000 E1000 data structure
[bf84871]758 *
759 */
[c4be33a]760static void e1000_disable_multicast_promisc(e1000_t *e1000)
[bf84871]761{
[c4be33a]762 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
[bf84871]763 rctl = rctl & ~RCTL_MPE;
[c4be33a]764 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
[bf84871]765}
766
[1df224c]767/** Enable multicast promiscuous mode
768 *
[c4be33a]769 * @param e1000 E1000 data structure
[bf84871]770 *
771 */
[c4be33a]772static void e1000_enable_multicast_promisc(e1000_t *e1000)
[bf84871]773{
[c4be33a]774 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
[bf84871]775 rctl = rctl | RCTL_MPE;
[c4be33a]776 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
[bf84871]777}
778
[1bc35b5]779/** Enable accepting of broadcast frames
[1df224c]780 *
[c4be33a]781 * @param e1000 E1000 data structure
[bf84871]782 *
783 */
[c4be33a]784static void e1000_enable_broadcast_accept(e1000_t *e1000)
[bf84871]785{
[c4be33a]786 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
[bf84871]787 rctl = rctl | RCTL_BAM;
[c4be33a]788 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
[bf84871]789}
790
[1bc35b5]791/** Disable accepting of broadcast frames
[1df224c]792 *
[c4be33a]793 * @param e1000 E1000 data structure
[bf84871]794 *
795 */
[c4be33a]796static void e1000_disable_broadcast_accept(e1000_t *e1000)
[bf84871]797{
[c4be33a]798 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
[bf84871]799 rctl = rctl & ~RCTL_BAM;
[c4be33a]800 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
[bf84871]801}
802
[1df224c]803/** Enable VLAN filtering according to VFTA registers
804 *
[c4be33a]805 * @param e1000 E1000 data structure
[bf84871]806 *
807 */
[c4be33a]808static void e1000_enable_vlan_filter(e1000_t *e1000)
[bf84871]809{
[c4be33a]810 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
[bf84871]811 rctl = rctl | RCTL_VFE;
[c4be33a]812 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
[bf84871]813}
814
[1df224c]815/** Disable VLAN filtering
816 *
[c4be33a]817 * @param e1000 E1000 data structure
[bf84871]818 *
819 */
[c4be33a]820static void e1000_disable_vlan_filter(e1000_t *e1000)
[bf84871]821{
[c4be33a]822 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
[bf84871]823 rctl = rctl & ~RCTL_VFE;
[c4be33a]824 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
[bf84871]825}
826
[1bc35b5]827/** Set multicast frames acceptance mode
[bf84871]828 *
[c4be33a]829 * @param nic NIC device to update
[1df224c]830 * @param mode Mode to set
831 * @param addr Address list (used in mode = NIC_MULTICAST_LIST)
832 * @param addr_cnt Length of address list (used in mode = NIC_MULTICAST_LIST)
833 *
834 * @return EOK
[bf84871]835 *
836 */
[b7fd2a0]837static errno_t e1000_on_multicast_mode_change(nic_t *nic, nic_multicast_mode_t mode,
[c4be33a]838 const nic_address_t *addr, size_t addr_cnt)
[bf84871]839{
[c4be33a]840 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
[b7fd2a0]841 errno_t rc = EOK;
[a35b458]842
[c4be33a]843 fibril_mutex_lock(&e1000->rx_lock);
[a35b458]844
[bf84871]845 switch (mode) {
846 case NIC_MULTICAST_BLOCKED:
[c4be33a]847 e1000_clear_multicast_receive_addresses(e1000);
848 e1000_disable_multicast_promisc(e1000);
849 nic_report_hw_filtering(nic, -1, 1, -1);
[bf84871]850 break;
851 case NIC_MULTICAST_LIST:
[c4be33a]852 e1000_clear_multicast_receive_addresses(e1000);
853 if (addr_cnt > get_free_multicast_address_count(e1000)) {
[1df224c]854 /*
855 * Future work: fill MTA table
856 * Not strictly neccessary, it only saves some compares
857 * in the NIC library.
858 */
[c4be33a]859 e1000_enable_multicast_promisc(e1000);
860 nic_report_hw_filtering(nic, -1, 0, -1);
[bf84871]861 } else {
[c4be33a]862 e1000_disable_multicast_promisc(e1000);
863 e1000_add_multicast_receive_addresses(e1000, addr, addr_cnt);
864 nic_report_hw_filtering(nic, -1, 1, -1);
[bf84871]865 }
866 break;
867 case NIC_MULTICAST_PROMISC:
[c4be33a]868 e1000_enable_multicast_promisc(e1000);
869 e1000_clear_multicast_receive_addresses(e1000);
870 nic_report_hw_filtering(nic, -1, 1, -1);
[bf84871]871 break;
872 default:
873 rc = ENOTSUP;
874 break;
875 }
[a35b458]876
[c4be33a]877 fibril_mutex_unlock(&e1000->rx_lock);
[bf84871]878 return rc;
879}
[1df224c]880
[1bc35b5]881/** Set unicast frames acceptance mode
[bf84871]882 *
[c4be33a]883 * @param nic NIC device to update
[1df224c]884 * @param mode Mode to set
885 * @param addr Address list (used in mode = NIC_MULTICAST_LIST)
886 * @param addr_cnt Length of address list (used in mode = NIC_MULTICAST_LIST)
887 *
888 * @return EOK
[bf84871]889 *
890 */
[b7fd2a0]891static errno_t e1000_on_unicast_mode_change(nic_t *nic, nic_unicast_mode_t mode,
[c4be33a]892 const nic_address_t *addr, size_t addr_cnt)
[bf84871]893{
[c4be33a]894 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
[b7fd2a0]895 errno_t rc = EOK;
[a35b458]896
[c4be33a]897 fibril_mutex_lock(&e1000->rx_lock);
[a35b458]898
[bf84871]899 switch (mode) {
900 case NIC_UNICAST_BLOCKED:
[c4be33a]901 disable_ra0_address_filter(e1000);
902 e1000_clear_unicast_receive_addresses(e1000);
903 e1000_disable_unicast_promisc(e1000);
904 nic_report_hw_filtering(nic, 1, -1, -1);
[bf84871]905 break;
906 case NIC_UNICAST_DEFAULT:
[c4be33a]907 enable_ra0_address_filter(e1000);
908 e1000_clear_unicast_receive_addresses(e1000);
909 e1000_disable_unicast_promisc(e1000);
910 nic_report_hw_filtering(nic, 1, -1, -1);
[bf84871]911 break;
912 case NIC_UNICAST_LIST:
[c4be33a]913 enable_ra0_address_filter(e1000);
914 e1000_clear_unicast_receive_addresses(e1000);
915 if (addr_cnt > get_free_unicast_address_count(e1000)) {
916 e1000_enable_unicast_promisc(e1000);
917 nic_report_hw_filtering(nic, 0, -1, -1);
[bf84871]918 } else {
[c4be33a]919 e1000_disable_unicast_promisc(e1000);
920 e1000_add_unicast_receive_addresses(e1000, addr, addr_cnt);
921 nic_report_hw_filtering(nic, 1, -1, -1);
[bf84871]922 }
923 break;
924 case NIC_UNICAST_PROMISC:
[c4be33a]925 e1000_enable_unicast_promisc(e1000);
926 enable_ra0_address_filter(e1000);
927 e1000_clear_unicast_receive_addresses(e1000);
928 nic_report_hw_filtering(nic, 1, -1, -1);
[bf84871]929 break;
930 default:
931 rc = ENOTSUP;
932 break;
933 }
[a35b458]934
[c4be33a]935 fibril_mutex_unlock(&e1000->rx_lock);
[bf84871]936 return rc;
937}
938
[1bc35b5]939/** Set broadcast frames acceptance mode
[bf84871]940 *
[c4be33a]941 * @param nic NIC device to update
942 * @param mode Mode to set
[1df224c]943 *
944 * @return EOK
[bf84871]945 *
946 */
[b7fd2a0]947static errno_t e1000_on_broadcast_mode_change(nic_t *nic, nic_broadcast_mode_t mode)
[bf84871]948{
[c4be33a]949 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
[b7fd2a0]950 errno_t rc = EOK;
[a35b458]951
[c4be33a]952 fibril_mutex_lock(&e1000->rx_lock);
[a35b458]953
[bf84871]954 switch (mode) {
955 case NIC_BROADCAST_BLOCKED:
[c4be33a]956 e1000_disable_broadcast_accept(e1000);
[bf84871]957 break;
958 case NIC_BROADCAST_ACCEPTED:
[c4be33a]959 e1000_enable_broadcast_accept(e1000);
[bf84871]960 break;
961 default:
962 rc = ENOTSUP;
963 break;
964 }
[a35b458]965
[c4be33a]966 fibril_mutex_unlock(&e1000->rx_lock);
[bf84871]967 return rc;
968}
969
[1df224c]970/** Check if receiving is enabled
971 *
[c4be33a]972 * @param e1000 E1000 data structure
[bf84871]973 *
974 * @return true if receiving is enabled
[1df224c]975 *
[bf84871]976 */
[c4be33a]977static bool e1000_is_rx_enabled(e1000_t *e1000)
[bf84871]978{
[c4be33a]979 if (E1000_REG_READ(e1000, E1000_RCTL) & (RCTL_EN))
[bf84871]980 return true;
[a35b458]981
[1df224c]982 return false;
[bf84871]983}
984
[1df224c]985/** Enable receiving
986 *
[c4be33a]987 * @param e1000 E1000 data structure
[bf84871]988 *
989 */
[c4be33a]990static void e1000_enable_rx(e1000_t *e1000)
[bf84871]991{
[1df224c]992 /* Set Receive Enable Bit */
[c4be33a]993 E1000_REG_WRITE(e1000, E1000_RCTL,
994 E1000_REG_READ(e1000, E1000_RCTL) | (RCTL_EN));
[bf84871]995}
996
[1df224c]997/** Disable receiving
998 *
[c4be33a]999 * @param e1000 E1000 data structure
[bf84871]1000 *
1001 */
[c4be33a]1002static void e1000_disable_rx(e1000_t *e1000)
[bf84871]1003{
[1df224c]1004 /* Clear Receive Enable Bit */
[c4be33a]1005 E1000_REG_WRITE(e1000, E1000_RCTL,
1006 E1000_REG_READ(e1000, E1000_RCTL) & ~(RCTL_EN));
[bf84871]1007}
1008
1009/** Set VLAN mask
1010 *
[c4be33a]1011 * @param nic NIC device to update
[1df224c]1012 * @param vlan_mask VLAN mask
1013 *
[bf84871]1014 */
[c4be33a]1015static void e1000_on_vlan_mask_change(nic_t *nic,
1016 const nic_vlan_mask_t *vlan_mask)
[bf84871]1017{
[c4be33a]1018 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
[a35b458]1019
[c4be33a]1020 fibril_mutex_lock(&e1000->rx_lock);
[a35b458]1021
[bf84871]1022 if (vlan_mask) {
[1df224c]1023 /*
[1bc35b5]1024 * Disable receiving, so that frame matching
[1df224c]1025 * partially written VLAN is not received.
1026 */
[c4be33a]1027 bool rx_enabled = e1000_is_rx_enabled(e1000);
[1df224c]1028 if (rx_enabled)
[c4be33a]1029 e1000_disable_rx(e1000);
[a35b458]1030
[1df224c]1031 for (unsigned int i = 0; i < NIC_VLAN_BITMAP_SIZE; i += 4) {
1032 uint32_t bitmap_part =
1033 ((uint32_t) vlan_mask->bitmap[i]) |
1034 (((uint32_t) vlan_mask->bitmap[i + 1]) << 8) |
1035 (((uint32_t) vlan_mask->bitmap[i + 2]) << 16) |
1036 (((uint32_t) vlan_mask->bitmap[i + 3]) << 24);
[c4be33a]1037 E1000_REG_WRITE(e1000, E1000_VFTA_ARRAY(i / 4), bitmap_part);
[bf84871]1038 }
[a35b458]1039
[c4be33a]1040 e1000_enable_vlan_filter(e1000);
[1df224c]1041 if (rx_enabled)
[c4be33a]1042 e1000_enable_rx(e1000);
[1df224c]1043 } else
[c4be33a]1044 e1000_disable_vlan_filter(e1000);
[a35b458]1045
[c4be33a]1046 fibril_mutex_unlock(&e1000->rx_lock);
[bf84871]1047}
1048
1049/** Set VLAN mask
1050 *
[1df224c]1051 * @param device E1000 device
1052 * @param tag VLAN tag
1053 *
1054 * @return EOK
1055 * @return ENOTSUP
[bf84871]1056 *
1057 */
[b7fd2a0]1058static errno_t e1000_vlan_set_tag(ddf_fun_t *fun, uint16_t tag, bool add,
[1df224c]1059 bool strip)
[bf84871]1060{
[1df224c]1061 /* VLAN CFI bit cannot be set */
1062 if (tag & VLANTAG_CFI)
[bf84871]1063 return ENOTSUP;
[a35b458]1064
[1df224c]1065 /*
1066 * CTRL.VME is neccessary for both strip and add
1067 * but CTRL.VME means stripping tags on receive.
1068 */
1069 if (!strip && add)
[bf84871]1070 return ENOTSUP;
[a35b458]1071
[56fd7cf]1072 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
[a35b458]1073
[c4be33a]1074 e1000->vlan_tag = tag;
1075 e1000->vlan_tag_add = add;
[a35b458]1076
[c4be33a]1077 fibril_mutex_lock(&e1000->ctrl_lock);
[a35b458]1078
[c4be33a]1079 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
[1df224c]1080 if (strip)
[bf84871]1081 ctrl |= CTRL_VME;
[1df224c]1082 else
[bf84871]1083 ctrl &= ~CTRL_VME;
[a35b458]1084
[c4be33a]1085 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
[a35b458]1086
[c4be33a]1087 fibril_mutex_unlock(&e1000->ctrl_lock);
[bf84871]1088 return EOK;
1089}
[1df224c]1090
[1bc35b5]1091/** Fill receive descriptor with new empty buffer
[bf84871]1092 *
[1bc35b5]1093 * Store frame in e1000->rx_frame_phys
[1df224c]1094 *
[c4be33a]1095 * @param nic NIC data stricture
1096 * @param offset Receive descriptor offset
[1df224c]1097 *
[bf84871]1098 */
[c4be33a]1099static void e1000_fill_new_rx_descriptor(nic_t *nic, size_t offset)
[bf84871]1100{
[c4be33a]1101 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
[a35b458]1102
[c4be33a]1103 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1104 (e1000->rx_ring_virt + offset * sizeof(e1000_rx_descriptor_t));
[a35b458]1105
[1bc35b5]1106 rx_descriptor->phys_addr = PTR_TO_U64(e1000->rx_frame_phys[offset]);
[bf84871]1107 rx_descriptor->length = 0;
1108 rx_descriptor->checksum = 0;
1109 rx_descriptor->status = 0;
1110 rx_descriptor->errors = 0;
1111 rx_descriptor->special = 0;
1112}
1113
1114/** Clear receive descriptor
1115 *
[c4be33a]1116 * @param e1000 E1000 data
1117 * @param offset Receive descriptor offset
[1df224c]1118 *
[bf84871]1119 */
[c4be33a]1120static void e1000_clear_rx_descriptor(e1000_t *e1000, unsigned int offset)
[1df224c]1121{
1122 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
[c4be33a]1123 (e1000->rx_ring_virt + offset * sizeof(e1000_rx_descriptor_t));
[a35b458]1124
[bf84871]1125 rx_descriptor->length = 0;
1126 rx_descriptor->checksum = 0;
1127 rx_descriptor->status = 0;
1128 rx_descriptor->errors = 0;
1129 rx_descriptor->special = 0;
1130}
1131
1132/** Clear receive descriptor
1133 *
[c4be33a]1134 * @param nic NIC data
1135 * @param offset Receive descriptor offset
[1df224c]1136 *
[bf84871]1137 */
[c4be33a]1138static void e1000_clear_tx_descriptor(nic_t *nic, unsigned int offset)
[bf84871]1139{
[c4be33a]1140 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
[a35b458]1141
[c4be33a]1142 e1000_tx_descriptor_t *tx_descriptor = (e1000_tx_descriptor_t *)
1143 (e1000->tx_ring_virt + offset * sizeof(e1000_tx_descriptor_t));
[a35b458]1144
[bf84871]1145 tx_descriptor->phys_addr = 0;
1146 tx_descriptor->length = 0;
1147 tx_descriptor->checksum_offset = 0;
1148 tx_descriptor->command = 0;
1149 tx_descriptor->status = 0;
1150 tx_descriptor->checksum_start_field = 0;
1151 tx_descriptor->special = 0;
1152}
1153
1154/** Increment tail pointer for receive or transmit ring
1155 *
[1df224c]1156 * @param tail Old Tail
1157 * @param descriptors_count Ring length
1158 *
1159 * @return New tail
[bf84871]1160 *
1161 */
1162static uint32_t e1000_inc_tail(uint32_t tail, uint32_t descriptors_count)
1163{
[1df224c]1164 if (tail + 1 == descriptors_count)
[bf84871]1165 return 0;
[1df224c]1166 else
[bf84871]1167 return tail + 1;
1168}
1169
[1bc35b5]1170/** Receive frames
[1df224c]1171 *
[c4be33a]1172 * @param nic NIC data
[1df224c]1173 *
[bf84871]1174 */
[1bc35b5]1175static void e1000_receive_frames(nic_t *nic)
[bf84871]1176{
[c4be33a]1177 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
[a35b458]1178
[c4be33a]1179 fibril_mutex_lock(&e1000->rx_lock);
[a35b458]1180
[c4be33a]1181 uint32_t *tail_addr = E1000_REG_ADDR(e1000, E1000_RDT);
[1bc35b5]1182 uint32_t next_tail = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
[a35b458]1183
[1df224c]1184 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
[c4be33a]1185 (e1000->rx_ring_virt + next_tail * sizeof(e1000_rx_descriptor_t));
[a35b458]1186
[1df224c]1187 while (rx_descriptor->status & 0x01) {
[1bc35b5]1188 uint32_t frame_size = rx_descriptor->length - E1000_CRC_SIZE;
[a35b458]1189
[1bc35b5]1190 nic_frame_t *frame = nic_alloc_frame(nic, frame_size);
1191 if (frame != NULL) {
1192 memcpy(frame->data, e1000->rx_frame_virt[next_tail], frame_size);
[17a8fcf]1193
[1bc35b5]1194 nic_received_frame(nic, frame);
1195 } else {
1196 ddf_msg(LVL_ERROR, "Memory allocation failed. Frame dropped.");
1197 }
[a35b458]1198
[c4be33a]1199 e1000_fill_new_rx_descriptor(nic, next_tail);
[a35b458]1200
[1bc35b5]1201 *tail_addr = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1202 next_tail = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
[a35b458]1203
[1df224c]1204 rx_descriptor = (e1000_rx_descriptor_t *)
[c4be33a]1205 (e1000->rx_ring_virt + next_tail * sizeof(e1000_rx_descriptor_t));
[bf84871]1206 }
[a35b458]1207
[c4be33a]1208 fibril_mutex_unlock(&e1000->rx_lock);
[bf84871]1209}
1210
[1df224c]1211/** Enable E1000 interupts
1212 *
[c4be33a]1213 * @param e1000 E1000 data structure
[bf84871]1214 *
1215 */
[c4be33a]1216static void e1000_enable_interrupts(e1000_t *e1000)
[bf84871]1217{
[c4be33a]1218 E1000_REG_WRITE(e1000, E1000_IMS, ICR_RXT0);
[bf84871]1219}
1220
[1df224c]1221/** Disable E1000 interupts
1222 *
[c4be33a]1223 * @param e1000 E1000 data structure
[bf84871]1224 *
1225 */
[c4be33a]1226static void e1000_disable_interrupts(e1000_t *e1000)
[bf84871]1227{
[c4be33a]1228 E1000_REG_WRITE(e1000, E1000_IMS, 0);
[bf84871]1229}
1230
1231/** Interrupt handler implementation
1232 *
[1df224c]1233 * This function is called from e1000_interrupt_handler()
1234 * and e1000_poll()
1235 *
[c4be33a]1236 * @param nic NIC data
1237 * @param icr ICR register value
[1df224c]1238 *
[bf84871]1239 */
[c4be33a]1240static void e1000_interrupt_handler_impl(nic_t *nic, uint32_t icr)
[1df224c]1241{
1242 if (icr & ICR_RXT0)
[1bc35b5]1243 e1000_receive_frames(nic);
[bf84871]1244}
1245
1246/** Handle device interrupt
1247 *
[1df224c]1248 * @param icall IPC call structure
[60744cb]1249 * @param arg Argument (nic_t *)
[1df224c]1250 *
[bf84871]1251 */
[60744cb]1252static void e1000_interrupt_handler(ipc_call_t *icall, void *arg)
[bf84871]1253{
[fafb8e5]1254 uint32_t icr = (uint32_t) ipc_get_arg2(icall);
[60744cb]1255 nic_t *nic = (nic_t *)arg;
[c4be33a]1256 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
[a35b458]1257
[c4be33a]1258 e1000_interrupt_handler_impl(nic, icr);
1259 e1000_enable_interrupts(e1000);
[1df224c]1260}
[bf84871]1261
1262/** Register interrupt handler for the card in the system
1263 *
[1df224c]1264 * Note: The global irq_reg_mutex is locked because of work with global
1265 * structure.
1266 *
[c4be33a]1267 * @param nic Driver data
[1df224c]1268 *
[071a1ddb]1269 * @param[out] handle IRQ capability handle if the handler was registered
1270 *
[cde999a]1271 * @return An error code otherwise
[bf84871]1272 *
1273 */
[eadaeae8]1274inline static errno_t e1000_register_int_handler(nic_t *nic,
1275 cap_irq_handle_t *handle)
[bf84871]1276{
[c4be33a]1277 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
[a35b458]1278
[bf84871]1279 /* Lock the mutex in whole driver while working with global structure */
1280 fibril_mutex_lock(&irq_reg_mutex);
[a35b458]1281
[ec52752]1282 e1000_irq_code.ranges[0].base = (uintptr_t) e1000->reg_base_phys;
1283 e1000_irq_code.cmds[0].addr = e1000->reg_base_phys + E1000_ICR;
[807be7e]1284 e1000_irq_code.cmds[3].addr = e1000->reg_base_phys + E1000_IMC;
[a35b458]1285
[b7fd2a0]1286 errno_t rc = register_interrupt_handler(nic_get_ddf_dev(nic), e1000->irq,
[60744cb]1287 e1000_interrupt_handler, (void *)nic, &e1000_irq_code, handle);
[a35b458]1288
[bf84871]1289 fibril_mutex_unlock(&irq_reg_mutex);
[071a1ddb]1290 return rc;
[bf84871]1291}
1292
[1bc35b5]1293/** Force receiving all frames in the receive buffer
[bf84871]1294 *
[c4be33a]1295 * @param nic NIC data
[1df224c]1296 *
[bf84871]1297 */
[c4be33a]1298static void e1000_poll(nic_t *nic)
[bf84871]1299{
[c4be33a]1300 assert(nic);
[a35b458]1301
[c4be33a]1302 e1000_t *e1000 = nic_get_specific(nic);
1303 assert(e1000);
[a35b458]1304
[c4be33a]1305 uint32_t icr = E1000_REG_READ(e1000, E1000_ICR);
1306 e1000_interrupt_handler_impl(nic, icr);
[bf84871]1307}
1308
[bd41ac52]1309/** Calculates ITR register interrupt from timespec structure
[bf84871]1310 *
[1df224c]1311 * @param period Period
1312 *
[bf84871]1313 */
[bd41ac52]1314static uint16_t e1000_calculate_itr_interval(const struct timespec *period)
[1df224c]1315{
1316 // TODO: use also tv_sec
[bd41ac52]1317 return e1000_calculate_itr_interval_from_usecs(NSEC2USEC(period->tv_nsec));
[bf84871]1318}
1319
1320/** Set polling mode
1321 *
[1df224c]1322 * @param device Device to set
1323 * @param mode Mode to set
1324 * @param period Period for NIC_POLL_PERIODIC
1325 *
1326 * @return EOK if succeed
1327 * @return ENOTSUP if the mode is not supported
[bf84871]1328 *
1329 */
[b7fd2a0]1330static errno_t e1000_poll_mode_change(nic_t *nic, nic_poll_mode_t mode,
[bd41ac52]1331 const struct timespec *period)
[bf84871]1332{
[c4be33a]1333 assert(nic);
[a35b458]1334
[c4be33a]1335 e1000_t *e1000 = nic_get_specific(nic);
1336 assert(e1000);
[a35b458]1337
[1df224c]1338 switch (mode) {
[bf84871]1339 case NIC_POLL_IMMEDIATE:
[c4be33a]1340 E1000_REG_WRITE(e1000, E1000_ITR, 0);
1341 e1000_enable_interrupts(e1000);
[bf84871]1342 break;
1343 case NIC_POLL_ON_DEMAND:
[c4be33a]1344 e1000_disable_interrupts(e1000);
[bf84871]1345 break;
1346 case NIC_POLL_PERIODIC:
1347 assert(period);
1348 uint16_t itr_interval = e1000_calculate_itr_interval(period);
[c4be33a]1349 E1000_REG_WRITE(e1000, E1000_ITR, (uint32_t) itr_interval);
1350 e1000_enable_interrupts(e1000);
[bf84871]1351 break;
1352 default:
1353 return ENOTSUP;
1354 }
[a35b458]1355
[bf84871]1356 return EOK;
1357}
1358
[1df224c]1359/** Initialize receive registers
1360 *
[c4be33a]1361 * @param e1000 E1000 data structure
[bf84871]1362 *
1363 */
[c4be33a]1364static void e1000_initialize_rx_registers(e1000_t *e1000)
[bf84871]1365{
[1bc35b5]1366 E1000_REG_WRITE(e1000, E1000_RDLEN, E1000_RX_FRAME_COUNT * 16);
[c4be33a]1367 E1000_REG_WRITE(e1000, E1000_RDH, 0);
[a35b458]1368
[1df224c]1369 /* It is not posible to let HW use all descriptors */
[1bc35b5]1370 E1000_REG_WRITE(e1000, E1000_RDT, E1000_RX_FRAME_COUNT - 1);
[a35b458]1371
[1df224c]1372 /* Set Broadcast Enable Bit */
[c4be33a]1373 E1000_REG_WRITE(e1000, E1000_RCTL, RCTL_BAM);
[bf84871]1374}
1375
[1df224c]1376/** Initialize receive structure
1377 *
[c4be33a]1378 * @param nic NIC data
[1df224c]1379 *
1380 * @return EOK if succeed
[cde999a]1381 * @return An error code otherwise
[bf84871]1382 *
1383 */
[b7fd2a0]1384static errno_t e1000_initialize_rx_structure(nic_t *nic)
[bf84871]1385{
[c4be33a]1386 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1387 fibril_mutex_lock(&e1000->rx_lock);
[a35b458]1388
[bf9cb2f]1389 e1000->rx_ring_virt = AS_AREA_ANY;
[b7fd2a0]1390 errno_t rc = dmamem_map_anonymous(
[1bc35b5]1391 E1000_RX_FRAME_COUNT * sizeof(e1000_rx_descriptor_t),
[8442d10]1392 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0,
1393 &e1000->rx_ring_phys, &e1000->rx_ring_virt);
[1df224c]1394 if (rc != EOK)
[bf84871]1395 return rc;
[a35b458]1396
[c4be33a]1397 E1000_REG_WRITE(e1000, E1000_RDBAH,
1398 (uint32_t) (PTR_TO_U64(e1000->rx_ring_phys) >> 32));
1399 E1000_REG_WRITE(e1000, E1000_RDBAL,
1400 (uint32_t) PTR_TO_U64(e1000->rx_ring_phys));
[a35b458]1401
[8442d10]1402 e1000->rx_frame_phys = (uintptr_t *)
1403 calloc(E1000_RX_FRAME_COUNT, sizeof(uintptr_t));
[1bc35b5]1404 e1000->rx_frame_virt =
1405 calloc(E1000_RX_FRAME_COUNT, sizeof(void *));
[8442d10]1406 if ((e1000->rx_frame_phys == NULL) || (e1000->rx_frame_virt == NULL)) {
[1bc35b5]1407 rc = ENOMEM;
1408 goto error;
1409 }
[a35b458]1410
[bf9cb2f]1411 for (size_t i = 0; i < E1000_RX_FRAME_COUNT; i++) {
1412 uintptr_t frame_phys;
1413 void *frame_virt = AS_AREA_ANY;
[a35b458]1414
[8442d10]1415 rc = dmamem_map_anonymous(E1000_MAX_SEND_FRAME_SIZE,
1416 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0,
1417 &frame_phys, &frame_virt);
[1bc35b5]1418 if (rc != EOK)
1419 goto error;
[a35b458]1420
[1bc35b5]1421 e1000->rx_frame_phys[i] = frame_phys;
[8442d10]1422 e1000->rx_frame_virt[i] = frame_virt;
[1bc35b5]1423 }
[a35b458]1424
[1df224c]1425 /* Write descriptor */
[bf9cb2f]1426 for (size_t i = 0; i < E1000_RX_FRAME_COUNT; i++)
[1bc35b5]1427 e1000_fill_new_rx_descriptor(nic, i);
[a35b458]1428
[c4be33a]1429 e1000_initialize_rx_registers(e1000);
[a35b458]1430
[c4be33a]1431 fibril_mutex_unlock(&e1000->rx_lock);
[bf84871]1432 return EOK;
[a35b458]1433
[1bc35b5]1434error:
[bf9cb2f]1435 for (size_t i = 0; i < E1000_RX_FRAME_COUNT; i++) {
[1bc35b5]1436 if (e1000->rx_frame_virt[i] != NULL) {
1437 dmamem_unmap_anonymous(e1000->rx_frame_virt[i]);
[8442d10]1438 e1000->rx_frame_phys[i] = 0;
[1bc35b5]1439 e1000->rx_frame_virt[i] = NULL;
1440 }
1441 }
[a35b458]1442
[1bc35b5]1443 if (e1000->rx_frame_phys != NULL) {
1444 free(e1000->rx_frame_phys);
1445 e1000->rx_frame_phys = NULL;
1446 }
[a35b458]1447
[1bc35b5]1448 if (e1000->rx_frame_virt != NULL) {
1449 free(e1000->rx_frame_virt);
[8442d10]1450 e1000->rx_frame_virt = NULL;
[1bc35b5]1451 }
[a35b458]1452
[1bc35b5]1453 return rc;
[bf84871]1454}
1455
[1df224c]1456/** Uninitialize receive structure
1457 *
[c4be33a]1458 * @param nic NIC data
[bf84871]1459 *
1460 */
[c4be33a]1461static void e1000_uninitialize_rx_structure(nic_t *nic)
[bf84871]1462{
[c4be33a]1463 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
[a35b458]1464
[1df224c]1465 /* Write descriptor */
[1bc35b5]1466 for (unsigned int offset = 0; offset < E1000_RX_FRAME_COUNT; offset++) {
1467 dmamem_unmap_anonymous(e1000->rx_frame_virt[offset]);
[8442d10]1468 e1000->rx_frame_phys[offset] = 0;
[1bc35b5]1469 e1000->rx_frame_virt[offset] = NULL;
[bf84871]1470 }
[a35b458]1471
[1bc35b5]1472 free(e1000->rx_frame_virt);
[a35b458]1473
[1bc35b5]1474 e1000->rx_frame_phys = NULL;
[8442d10]1475 e1000->rx_frame_virt = NULL;
[a35b458]1476
[c4be33a]1477 dmamem_unmap_anonymous(e1000->rx_ring_virt);
[bf84871]1478}
1479
1480/** Clear receive descriptor ring
1481 *
[c4be33a]1482 * @param e1000 E1000 data
[1df224c]1483 *
[bf84871]1484 */
[c4be33a]1485static void e1000_clear_rx_ring(e1000_t *e1000)
[bf84871]1486{
[1df224c]1487 /* Write descriptor */
1488 for (unsigned int offset = 0;
[1bc35b5]1489 offset < E1000_RX_FRAME_COUNT;
[1df224c]1490 offset++)
[c4be33a]1491 e1000_clear_rx_descriptor(e1000, offset);
[bf84871]1492}
1493
1494/** Initialize filters
1495 *
[c4be33a]1496 * @param e1000 E1000 data
[1df224c]1497 *
[bf84871]1498 */
[c4be33a]1499static void e1000_initialize_filters(e1000_t *e1000)
[bf84871]1500{
[1df224c]1501 /* Initialize address filter */
[c4be33a]1502 e1000->unicast_ra_count = 0;
1503 e1000->multicast_ra_count = 0;
1504 e1000_clear_unicast_receive_addresses(e1000);
[bf84871]1505}
1506
1507/** Initialize VLAN
1508 *
[c4be33a]1509 * @param e1000 E1000 data
[1df224c]1510 *
[bf84871]1511 */
[c4be33a]1512static void e1000_initialize_vlan(e1000_t *e1000)
[bf84871]1513{
[c4be33a]1514 e1000->vlan_tag_add = false;
[bf84871]1515}
1516
[1df224c]1517/** Fill MAC address from EEPROM to RA[0] register
1518 *
[c4be33a]1519 * @param e1000 E1000 data
[bf84871]1520 *
1521 */
[c4be33a]1522static void e1000_fill_mac_from_eeprom(e1000_t *e1000)
[bf84871]1523{
[1df224c]1524 /* MAC address from eeprom to RA[0] */
[bf84871]1525 nic_address_t address;
[c4be33a]1526 e1000_eeprom_get_address(e1000, &address);
1527 e1000_write_receive_address(e1000, 0, &address, true);
[bf84871]1528}
1529
[1df224c]1530/** Initialize other registers
1531 *
1532 * @param dev E1000 data.
1533 *
1534 * @return EOK if succeed
[cde999a]1535 * @return An error code otherwise
[bf84871]1536 *
1537 */
[c4be33a]1538static void e1000_initialize_registers(e1000_t *e1000)
[bf84871]1539{
[c4be33a]1540 E1000_REG_WRITE(e1000, E1000_ITR,
[1df224c]1541 e1000_calculate_itr_interval_from_usecs(
[9916841]1542 E1000_DEFAULT_INTERRUPT_INTERVAL_USEC));
[c4be33a]1543 E1000_REG_WRITE(e1000, E1000_FCAH, 0);
1544 E1000_REG_WRITE(e1000, E1000_FCAL, 0);
1545 E1000_REG_WRITE(e1000, E1000_FCT, 0);
1546 E1000_REG_WRITE(e1000, E1000_FCTTV, 0);
1547 E1000_REG_WRITE(e1000, E1000_VET, VET_VALUE);
1548 E1000_REG_WRITE(e1000, E1000_CTRL, CTRL_ASDE);
[bf84871]1549}
1550
[1df224c]1551/** Initialize transmit registers
1552 *
[c4be33a]1553 * @param e1000 E1000 data.
[bf84871]1554 *
1555 */
[c4be33a]1556static void e1000_initialize_tx_registers(e1000_t *e1000)
[bf84871]1557{
[1bc35b5]1558 E1000_REG_WRITE(e1000, E1000_TDLEN, E1000_TX_FRAME_COUNT * 16);
[c4be33a]1559 E1000_REG_WRITE(e1000, E1000_TDH, 0);
1560 E1000_REG_WRITE(e1000, E1000_TDT, 0);
[a35b458]1561
[c4be33a]1562 E1000_REG_WRITE(e1000, E1000_TIPG,
[1df224c]1563 10 << TIPG_IPGT_SHIFT |
1564 8 << TIPG_IPGR1_SHIFT |
1565 6 << TIPG_IPGR2_SHIFT);
[a35b458]1566
[c4be33a]1567 E1000_REG_WRITE(e1000, E1000_TCTL,
[1df224c]1568 0x0F << TCTL_CT_SHIFT /* Collision Threshold */ |
1569 0x40 << TCTL_COLD_SHIFT /* Collision Distance */ |
1570 TCTL_PSP /* Pad Short Packets */);
[bf84871]1571}
1572
1573/** Initialize transmit structure
1574 *
[c4be33a]1575 * @param e1000 E1000 data.
[1df224c]1576 *
[bf84871]1577 */
[b7fd2a0]1578static errno_t e1000_initialize_tx_structure(e1000_t *e1000)
[bf84871]1579{
[6d8455d]1580 size_t i;
[a35b458]1581
[c4be33a]1582 fibril_mutex_lock(&e1000->tx_lock);
[a35b458]1583
[8442d10]1584 e1000->tx_ring_phys = 0;
[bf9cb2f]1585 e1000->tx_ring_virt = AS_AREA_ANY;
[a35b458]1586
[6d8455d]1587 e1000->tx_frame_phys = NULL;
1588 e1000->tx_frame_virt = NULL;
[a35b458]1589
[b7fd2a0]1590 errno_t rc = dmamem_map_anonymous(
[1bc35b5]1591 E1000_TX_FRAME_COUNT * sizeof(e1000_tx_descriptor_t),
[8442d10]1592 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0,
1593 &e1000->tx_ring_phys, &e1000->tx_ring_virt);
[1df224c]1594 if (rc != EOK)
[6d8455d]1595 goto error;
[a35b458]1596
[acdb5bac]1597 memset(e1000->tx_ring_virt, 0,
[1bc35b5]1598 E1000_TX_FRAME_COUNT * sizeof(e1000_tx_descriptor_t));
[a35b458]1599
[8442d10]1600 e1000->tx_frame_phys = (uintptr_t *)
1601 calloc(E1000_TX_FRAME_COUNT, sizeof(uintptr_t));
1602 e1000->tx_frame_virt =
1603 calloc(E1000_TX_FRAME_COUNT, sizeof(void *));
[6d8455d]1604
[8442d10]1605 if ((e1000->tx_frame_phys == NULL) || (e1000->tx_frame_virt == NULL)) {
[6d8455d]1606 rc = ENOMEM;
1607 goto error;
1608 }
[a35b458]1609
[1bc35b5]1610 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
[bf9cb2f]1611 e1000->tx_frame_virt[i] = AS_AREA_ANY;
[8442d10]1612 rc = dmamem_map_anonymous(E1000_MAX_SEND_FRAME_SIZE,
1613 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE,
[6d8455d]1614 0, &e1000->tx_frame_phys[i], &e1000->tx_frame_virt[i]);
1615 if (rc != EOK)
1616 goto error;
1617 }
[a35b458]1618
[c4be33a]1619 E1000_REG_WRITE(e1000, E1000_TDBAH,
1620 (uint32_t) (PTR_TO_U64(e1000->tx_ring_phys) >> 32));
1621 E1000_REG_WRITE(e1000, E1000_TDBAL,
1622 (uint32_t) PTR_TO_U64(e1000->tx_ring_phys));
[a35b458]1623
[c4be33a]1624 e1000_initialize_tx_registers(e1000);
[a35b458]1625
[c4be33a]1626 fibril_mutex_unlock(&e1000->tx_lock);
[bf84871]1627 return EOK;
[a35b458]1628
[6d8455d]1629error:
1630 if (e1000->tx_ring_virt != NULL) {
1631 dmamem_unmap_anonymous(e1000->tx_ring_virt);
1632 e1000->tx_ring_virt = NULL;
1633 }
[a35b458]1634
[8442d10]1635 if ((e1000->tx_frame_phys != NULL) && (e1000->tx_frame_virt != NULL)) {
[1bc35b5]1636 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
[6d8455d]1637 if (e1000->tx_frame_virt[i] != NULL) {
1638 dmamem_unmap_anonymous(e1000->tx_frame_virt[i]);
[8442d10]1639 e1000->tx_frame_phys[i] = 0;
[6d8455d]1640 e1000->tx_frame_virt[i] = NULL;
1641 }
1642 }
1643 }
[a35b458]1644
[6d8455d]1645 if (e1000->tx_frame_phys != NULL) {
1646 free(e1000->tx_frame_phys);
1647 e1000->tx_frame_phys = NULL;
1648 }
[a35b458]1649
[6d8455d]1650 if (e1000->tx_frame_virt != NULL) {
1651 free(e1000->tx_frame_virt);
[8442d10]1652 e1000->tx_frame_virt = NULL;
[6d8455d]1653 }
[a35b458]1654
[6d8455d]1655 return rc;
[bf84871]1656}
1657
[1df224c]1658/** Uninitialize transmit structure
1659 *
[c4be33a]1660 * @param nic NIC data
[bf84871]1661 *
1662 */
[c4be33a]1663static void e1000_uninitialize_tx_structure(e1000_t *e1000)
[bf84871]1664{
[6d8455d]1665 size_t i;
[a35b458]1666
[1bc35b5]1667 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
[6d8455d]1668 dmamem_unmap_anonymous(e1000->tx_frame_virt[i]);
[8442d10]1669 e1000->tx_frame_phys[i] = 0;
[6d8455d]1670 e1000->tx_frame_virt[i] = NULL;
1671 }
[a35b458]1672
[6d8455d]1673 if (e1000->tx_frame_phys != NULL) {
1674 free(e1000->tx_frame_phys);
1675 e1000->tx_frame_phys = NULL;
1676 }
[a35b458]1677
[6d8455d]1678 if (e1000->tx_frame_virt != NULL) {
1679 free(e1000->tx_frame_virt);
[8442d10]1680 e1000->tx_frame_virt = NULL;
[6d8455d]1681 }
[a35b458]1682
[c4be33a]1683 dmamem_unmap_anonymous(e1000->tx_ring_virt);
[bf84871]1684}
1685
1686/** Clear transmit descriptor ring
1687 *
[c4be33a]1688 * @param nic NIC data
[1df224c]1689 *
[bf84871]1690 */
[c4be33a]1691static void e1000_clear_tx_ring(nic_t *nic)
[bf84871]1692{
[1df224c]1693 /* Write descriptor */
1694 for (unsigned int offset = 0;
[1bc35b5]1695 offset < E1000_TX_FRAME_COUNT;
[1df224c]1696 offset++)
[c4be33a]1697 e1000_clear_tx_descriptor(nic, offset);
[bf84871]1698}
1699
1700/** Enable transmit
1701 *
[c4be33a]1702 * @param e1000 E1000 data
[1df224c]1703 *
[bf84871]1704 */
[c4be33a]1705static void e1000_enable_tx(e1000_t *e1000)
[bf84871]1706{
[1df224c]1707 /* Set Transmit Enable Bit */
[c4be33a]1708 E1000_REG_WRITE(e1000, E1000_TCTL,
1709 E1000_REG_READ(e1000, E1000_TCTL) | (TCTL_EN));
[bf84871]1710}
1711
1712/** Disable transmit
1713 *
[c4be33a]1714 * @param e1000 E1000 data
[1df224c]1715 *
[bf84871]1716 */
[c4be33a]1717static void e1000_disable_tx(e1000_t *e1000)
[bf84871]1718{
[1df224c]1719 /* Clear Transmit Enable Bit */
[c4be33a]1720 E1000_REG_WRITE(e1000, E1000_TCTL,
1721 E1000_REG_READ(e1000, E1000_TCTL) & ~(TCTL_EN));
[bf84871]1722}
1723
1724/** Reset E1000 device
1725 *
[c4be33a]1726 * @param e1000 The E1000 data
[1df224c]1727 *
[bf84871]1728 */
[b7fd2a0]1729static errno_t e1000_reset(nic_t *nic)
[bf84871]1730{
[c4be33a]1731 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
[a35b458]1732
[c4be33a]1733 E1000_REG_WRITE(e1000, E1000_CTRL, CTRL_RST);
[a35b458]1734
[1df224c]1735 /* Wait for the reset */
[5f97ef44]1736 fibril_usleep(20);
[a35b458]1737
[1df224c]1738 /* check if RST_BIT cleared */
[c4be33a]1739 if (E1000_REG_READ(e1000, E1000_CTRL) & (CTRL_RST))
[1df224c]1740 return EINVAL;
[a35b458]1741
[c4be33a]1742 e1000_initialize_registers(e1000);
1743 e1000_initialize_rx_registers(e1000);
1744 e1000_initialize_tx_registers(e1000);
1745 e1000_fill_mac_from_eeprom(e1000);
1746 e1000_initialize_filters(e1000);
1747 e1000_initialize_vlan(e1000);
[a35b458]1748
[bf84871]1749 return EOK;
1750}
1751
[1bc35b5]1752/** Activate the device to receive and transmit frames
[bf84871]1753 *
[c4be33a]1754 * @param nic NIC driver data
[1df224c]1755 *
1756 * @return EOK if activated successfully
1757 * @return Error code otherwise
1758 *
[bf84871]1759 */
[b7fd2a0]1760static errno_t e1000_on_activating(nic_t *nic)
[bf84871]1761{
[c4be33a]1762 assert(nic);
[a35b458]1763
[c4be33a]1764 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
[a35b458]1765
[c4be33a]1766 fibril_mutex_lock(&e1000->rx_lock);
1767 fibril_mutex_lock(&e1000->tx_lock);
1768 fibril_mutex_lock(&e1000->ctrl_lock);
[a35b458]1769
[c4be33a]1770 e1000_enable_interrupts(e1000);
[a35b458]1771
[b7fd2a0]1772 errno_t rc = hw_res_enable_interrupt(e1000->parent_sess, e1000->irq);
[e5424e9]1773 if (rc != EOK) {
1774 e1000_disable_interrupts(e1000);
1775 fibril_mutex_unlock(&e1000->ctrl_lock);
1776 fibril_mutex_unlock(&e1000->tx_lock);
1777 fibril_mutex_unlock(&e1000->rx_lock);
1778 return rc;
1779 }
[a35b458]1780
[c4be33a]1781 e1000_clear_rx_ring(e1000);
1782 e1000_enable_rx(e1000);
[a35b458]1783
[c4be33a]1784 e1000_clear_tx_ring(nic);
1785 e1000_enable_tx(e1000);
[a35b458]1786
[c4be33a]1787 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
[bf84871]1788 ctrl |= CTRL_SLU;
[c4be33a]1789 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
[a35b458]1790
[c4be33a]1791 fibril_mutex_unlock(&e1000->ctrl_lock);
1792 fibril_mutex_unlock(&e1000->tx_lock);
1793 fibril_mutex_unlock(&e1000->rx_lock);
[a35b458]1794
[bf84871]1795 return EOK;
1796}
1797
1798/** Callback for NIC_STATE_DOWN change
1799 *
[c4be33a]1800 * @param nic NIC driver data
[1df224c]1801 *
1802 * @return EOK if succeed
1803 * @return Error code otherwise
1804 *
[bf84871]1805 */
[b7fd2a0]1806static errno_t e1000_on_down_unlocked(nic_t *nic)
[bf84871]1807{
[c4be33a]1808 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
[a35b458]1809
[c4be33a]1810 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
[bf84871]1811 ctrl &= ~CTRL_SLU;
[c4be33a]1812 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
[a35b458]1813
[c4be33a]1814 e1000_disable_tx(e1000);
1815 e1000_disable_rx(e1000);
[a35b458]1816
[d51838f]1817 hw_res_disable_interrupt(e1000->parent_sess, e1000->irq);
[c4be33a]1818 e1000_disable_interrupts(e1000);
[a35b458]1819
[1df224c]1820 /*
1821 * Wait for the for the end of all data
1822 * transfers to descriptors.
1823 */
[5f97ef44]1824 fibril_usleep(100);
[a35b458]1825
[bf84871]1826 return EOK;
1827}
1828
1829/** Callback for NIC_STATE_DOWN change
1830 *
[c4be33a]1831 * @param nic NIC driver data
[1df224c]1832 *
1833 * @return EOK if succeed
1834 * @return Error code otherwise
1835 *
[bf84871]1836 */
[b7fd2a0]1837static errno_t e1000_on_down(nic_t *nic)
[bf84871]1838{
[c4be33a]1839 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
[a35b458]1840
[c4be33a]1841 fibril_mutex_lock(&e1000->rx_lock);
1842 fibril_mutex_lock(&e1000->tx_lock);
1843 fibril_mutex_lock(&e1000->ctrl_lock);
[a35b458]1844
[b7fd2a0]1845 errno_t rc = e1000_on_down_unlocked(nic);
[a35b458]1846
[c4be33a]1847 fibril_mutex_unlock(&e1000->ctrl_lock);
1848 fibril_mutex_unlock(&e1000->tx_lock);
1849 fibril_mutex_unlock(&e1000->rx_lock);
[a35b458]1850
[bf84871]1851 return rc;
1852}
1853
1854/** Callback for NIC_STATE_STOPPED change
1855 *
[c4be33a]1856 * @param nic NIC driver data
[1df224c]1857 *
1858 * @return EOK if succeed
1859 * @return Error code otherwise
1860 *
[bf84871]1861 */
[b7fd2a0]1862static errno_t e1000_on_stopping(nic_t *nic)
[bf84871]1863{
[c4be33a]1864 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
[a35b458]1865
[c4be33a]1866 fibril_mutex_lock(&e1000->rx_lock);
1867 fibril_mutex_lock(&e1000->tx_lock);
1868 fibril_mutex_lock(&e1000->ctrl_lock);
[a35b458]1869
[b7fd2a0]1870 errno_t rc = e1000_on_down_unlocked(nic);
[1df224c]1871 if (rc == EOK)
[c4be33a]1872 rc = e1000_reset(nic);
[a35b458]1873
[c4be33a]1874 fibril_mutex_unlock(&e1000->ctrl_lock);
1875 fibril_mutex_unlock(&e1000->tx_lock);
1876 fibril_mutex_unlock(&e1000->rx_lock);
[a35b458]1877
[bf84871]1878 return rc;
1879}
1880
1881/** Create driver data structure
1882 *
[1df224c]1883 * @return Intialized device data structure or NULL
1884 *
[bf84871]1885 */
1886static e1000_t *e1000_create_dev_data(ddf_dev_t *dev)
1887{
[c4be33a]1888 nic_t *nic = nic_create_and_bind(dev);
1889 if (!nic)
[bf84871]1890 return NULL;
[a35b458]1891
[c4be33a]1892 e1000_t *e1000 = malloc(sizeof(e1000_t));
1893 if (!e1000) {
[bf84871]1894 nic_unbind_and_destroy(dev);
1895 return NULL;
1896 }
[a35b458]1897
[acdb5bac]1898 memset(e1000, 0, sizeof(e1000_t));
[d51838f]1899 e1000->dev = dev;
[a35b458]1900
[c4be33a]1901 nic_set_specific(nic, e1000);
[6d8455d]1902 nic_set_send_frame_handler(nic, e1000_send_frame);
[c4be33a]1903 nic_set_state_change_handlers(nic, e1000_on_activating,
[1df224c]1904 e1000_on_down, e1000_on_stopping);
[c4be33a]1905 nic_set_filtering_change_handlers(nic,
[1df224c]1906 e1000_on_unicast_mode_change, e1000_on_multicast_mode_change,
1907 e1000_on_broadcast_mode_change, NULL, e1000_on_vlan_mask_change);
[c4be33a]1908 nic_set_poll_handlers(nic, e1000_poll_mode_change, e1000_poll);
[a35b458]1909
[c4be33a]1910 fibril_mutex_initialize(&e1000->ctrl_lock);
1911 fibril_mutex_initialize(&e1000->rx_lock);
1912 fibril_mutex_initialize(&e1000->tx_lock);
1913 fibril_mutex_initialize(&e1000->eeprom_lock);
[a35b458]1914
[c4be33a]1915 return e1000;
[bf84871]1916}
1917
[1df224c]1918/** Delete driver data structure
1919 *
1920 * @param data E1000 device data structure
[bf84871]1921 *
1922 */
1923inline static void e1000_delete_dev_data(ddf_dev_t *dev)
1924{
1925 assert(dev);
[a35b458]1926
[56fd7cf]1927 if (ddf_dev_data_get(dev) != NULL)
[bf84871]1928 nic_unbind_and_destroy(dev);
1929}
1930
[1df224c]1931/** Clean up the E1000 device structure.
1932 *
1933 * @param dev Device structure.
[bf84871]1934 *
1935 */
1936static void e1000_dev_cleanup(ddf_dev_t *dev)
1937{
1938 assert(dev);
[a35b458]1939
[bf84871]1940 e1000_delete_dev_data(dev);
1941}
1942
1943/** Fill the irq and io_addr part of device data structure
1944 *
[1df224c]1945 * The hw_resources must be obtained before calling this function
1946 *
1947 * @param dev Device structure
1948 * @param hw_resources Hardware resources obtained from the parent device
1949 *
1950 * @return EOK if succeed
[cde999a]1951 * @return An error code otherwise
[bf84871]1952 *
1953 */
[b7fd2a0]1954static errno_t e1000_fill_resource_info(ddf_dev_t *dev,
[1df224c]1955 const hw_res_list_parsed_t *hw_resources)
[bf84871]1956{
[c4be33a]1957 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
[a35b458]1958
[1df224c]1959 if (hw_resources->irqs.count != 1)
[bf84871]1960 return EINVAL;
[a35b458]1961
[c4be33a]1962 e1000->irq = hw_resources->irqs.irqs[0];
1963 e1000->reg_base_phys =
[7de1988c]1964 MEMADDR_TO_PTR(RNGABS(hw_resources->mem_ranges.ranges[0]));
[a35b458]1965
[bf84871]1966 return EOK;
1967}
1968
1969/** Obtain information about hardware resources of the device
1970 *
[1df224c]1971 * The device must be connected to the parent
1972 *
1973 * @param dev Device structure
1974 *
1975 * @return EOK if succeed
[cde999a]1976 * @return An error code otherwise
[bf84871]1977 *
1978 */
[b7fd2a0]1979static errno_t e1000_get_resource_info(ddf_dev_t *dev)
[bf84871]1980{
1981 assert(dev != NULL);
1982 assert(NIC_DATA_DEV(dev) != NULL);
[a35b458]1983
[bf84871]1984 hw_res_list_parsed_t hw_res_parsed;
1985 hw_res_list_parsed_init(&hw_res_parsed);
[a35b458]1986
[bf84871]1987 /* Get hw resources form parent driver */
[b7fd2a0]1988 errno_t rc = nic_get_resources(NIC_DATA_DEV(dev), &hw_res_parsed);
[bf84871]1989 if (rc != EOK)
1990 return rc;
[a35b458]1991
[bf84871]1992 /* Fill resources information to the device */
1993 rc = e1000_fill_resource_info(dev, &hw_res_parsed);
1994 hw_res_list_parsed_clean(&hw_res_parsed);
[a35b458]1995
[bf84871]1996 return rc;
1997}
1998
[1df224c]1999/** Initialize the E1000 device structure
2000 *
2001 * @param dev Device information
2002 *
2003 * @return EOK if succeed
[cde999a]2004 * @return An error code otherwise
[bf84871]2005 *
2006 */
[b7fd2a0]2007static errno_t e1000_device_initialize(ddf_dev_t *dev)
[bf84871]2008{
2009 /* Allocate driver data for the device. */
[c4be33a]2010 e1000_t *e1000 = e1000_create_dev_data(dev);
[77c2b02]2011 if (e1000 == NULL) {
2012 ddf_msg(LVL_ERROR, "Unable to allocate device softstate");
[bf84871]2013 return ENOMEM;
[77c2b02]2014 }
[a35b458]2015
[d51838f]2016 e1000->parent_sess = ddf_dev_parent_sess_get(dev);
2017 if (e1000->parent_sess == NULL) {
2018 ddf_msg(LVL_ERROR, "Failed connecting parent device.");
2019 return EIO;
2020 }
[a35b458]2021
[bf84871]2022 /* Obtain and fill hardware resources info */
[b7fd2a0]2023 errno_t rc = e1000_get_resource_info(dev);
[bf84871]2024 if (rc != EOK) {
[77c2b02]2025 ddf_msg(LVL_ERROR, "Cannot obtain hardware resources");
[1df224c]2026 e1000_dev_cleanup(dev);
2027 return rc;
[bf84871]2028 }
[a35b458]2029
[77c2b02]2030 uint16_t device_id;
[56fd7cf]2031 rc = pci_config_space_read_16(ddf_dev_parent_sess_get(dev), PCI_DEVICE_ID,
[77c2b02]2032 &device_id);
[bf84871]2033 if (rc != EOK) {
[77c2b02]2034 ddf_msg(LVL_ERROR, "Cannot access PCI configuration space");
[1df224c]2035 e1000_dev_cleanup(dev);
2036 return rc;
[bf84871]2037 }
[a35b458]2038
[77c2b02]2039 e1000_board_t board;
2040 switch (device_id) {
[9f0fb84]2041 case 0x100e:
2042 case 0x1015:
2043 case 0x1016:
2044 case 0x1017:
2045 board = E1000_82540;
2046 break;
[77c2b02]2047 case 0x1013:
2048 case 0x1018:
2049 case 0x1078:
2050 board = E1000_82541;
2051 break;
2052 case 0x1076:
2053 case 0x1077:
2054 case 0x107c:
2055 board = E1000_82541REV2;
2056 break;
[9f0fb84]2057 case 0x100f:
2058 case 0x1011:
2059 case 0x1026:
2060 case 0x1027:
2061 case 0x1028:
2062 board = E1000_82545;
2063 break;
2064 case 0x1010:
2065 case 0x1012:
2066 case 0x101d:
2067 case 0x1079:
2068 case 0x107a:
2069 case 0x107b:
2070 board = E1000_82546;
2071 break;
[77c2b02]2072 case 0x1019:
2073 case 0x101a:
2074 board = E1000_82547;
2075 break;
2076 case 0x10b9:
2077 board = E1000_82572;
2078 break;
2079 case 0x1096:
2080 board = E1000_80003ES2;
2081 break;
2082 default:
2083 ddf_msg(LVL_ERROR, "Device not supported (%#" PRIx16 ")",
2084 device_id);
2085 e1000_dev_cleanup(dev);
2086 return ENOTSUP;
2087 }
[a35b458]2088
[77c2b02]2089 switch (board) {
[9f0fb84]2090 case E1000_82540:
[77c2b02]2091 case E1000_82541:
2092 case E1000_82541REV2:
[9f0fb84]2093 case E1000_82545:
2094 case E1000_82546:
[77c2b02]2095 e1000->info.eerd_start = 0x01;
2096 e1000->info.eerd_done = 0x10;
2097 e1000->info.eerd_address_offset = 8;
2098 e1000->info.eerd_data_offset = 16;
2099 break;
2100 case E1000_82547:
[d81eaf94]2101 case E1000_82572:
[77c2b02]2102 case E1000_80003ES2:
2103 e1000->info.eerd_start = 0x01;
2104 e1000->info.eerd_done = 0x02;
2105 e1000->info.eerd_address_offset = 2;
2106 e1000->info.eerd_data_offset = 16;
2107 break;
2108 }
[a35b458]2109
[1df224c]2110 return EOK;
[bf84871]2111}
2112
[1df224c]2113/** Enable the I/O ports of the device.
2114 *
2115 * @param dev E1000 device.
2116 *
2117 * @return EOK if successed
[cde999a]2118 * @return An error code otherwise
[bf84871]2119 *
2120 */
[b7fd2a0]2121static errno_t e1000_pio_enable(ddf_dev_t *dev)
[bf84871]2122{
[c4be33a]2123 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
[a35b458]2124
[b7fd2a0]2125 errno_t rc = pio_enable(e1000->reg_base_phys, 8 * PAGE_SIZE,
[c4be33a]2126 &e1000->reg_base_virt);
[1df224c]2127 if (rc != EOK)
[bf84871]2128 return EADDRNOTAVAIL;
[a35b458]2129
[bf84871]2130 return EOK;
2131}
2132
[9916841]2133/** Probe and initialize the newly added device.
[bf84871]2134 *
[1df224c]2135 * @param dev E1000 device.
2136 *
[bf84871]2137 */
[b7fd2a0]2138errno_t e1000_dev_add(ddf_dev_t *dev)
[bf84871]2139{
[e86b8f0]2140 ddf_fun_t *fun;
[a35b458]2141
[1df224c]2142 /* Initialize device structure for E1000 */
[b7fd2a0]2143 errno_t rc = e1000_device_initialize(dev);
[bf84871]2144 if (rc != EOK)
2145 return rc;
[a35b458]2146
[1df224c]2147 /* Device initialization */
[56fd7cf]2148 nic_t *nic = ddf_dev_data_get(dev);
[c4be33a]2149 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
[a35b458]2150
[bf84871]2151 /* Map registers */
2152 rc = e1000_pio_enable(dev);
2153 if (rc != EOK)
2154 goto err_destroy;
[a35b458]2155
[c4be33a]2156 e1000_initialize_registers(e1000);
2157 rc = e1000_initialize_tx_structure(e1000);
[1df224c]2158 if (rc != EOK)
[bf84871]2159 goto err_pio;
[a35b458]2160
[c4be33a]2161 fibril_mutex_lock(&e1000->rx_lock);
[a35b458]2162
[c4be33a]2163 e1000_fill_mac_from_eeprom(e1000);
2164 e1000_initialize_filters(e1000);
[a35b458]2165
[c4be33a]2166 fibril_mutex_unlock(&e1000->rx_lock);
[a35b458]2167
[c4be33a]2168 e1000_initialize_vlan(e1000);
[a35b458]2169
[e86b8f0]2170 fun = ddf_fun_create(nic_get_ddf_dev(nic), fun_exposed, "port0");
2171 if (fun == NULL)
[bf84871]2172 goto err_tx_structure;
[e86b8f0]2173 nic_set_ddf_fun(nic, fun);
[56fd7cf]2174 ddf_fun_set_ops(fun, &e1000_dev_ops);
[a35b458]2175
[eadaeae8]2176 cap_irq_handle_t irq_handle;
2177 rc = e1000_register_int_handler(nic, &irq_handle);
[071a1ddb]2178 if (rc != EOK) {
[e86b8f0]2179 goto err_fun_create;
[e9d15d9]2180 }
[a35b458]2181
[c4be33a]2182 rc = e1000_initialize_rx_structure(nic);
[1df224c]2183 if (rc != EOK)
[bf84871]2184 goto err_irq;
[a35b458]2185
[bf84871]2186 nic_address_t e1000_address;
[c4be33a]2187 e1000_get_address(e1000, &e1000_address);
2188 rc = nic_report_address(nic, &e1000_address);
[1df224c]2189 if (rc != EOK)
[bf84871]2190 goto err_rx_structure;
[a35b458]2191
[bd41ac52]2192 struct timespec period;
[bf84871]2193 period.tv_sec = 0;
[bd41ac52]2194 period.tv_nsec = USEC2NSEC(E1000_DEFAULT_INTERRUPT_INTERVAL_USEC);
[c4be33a]2195 rc = nic_report_poll_mode(nic, NIC_POLL_PERIODIC, &period);
[1df224c]2196 if (rc != EOK)
[bf84871]2197 goto err_rx_structure;
[a35b458]2198
[e86b8f0]2199 rc = ddf_fun_bind(fun);
2200 if (rc != EOK)
2201 goto err_fun_bind;
[a35b458]2202
[e86b8f0]2203 rc = ddf_fun_add_to_category(fun, DEVICE_CATEGORY_NIC);
2204 if (rc != EOK)
2205 goto err_add_to_cat;
[a35b458]2206
[17a8fcf]2207 rc = ddf_fun_add_to_category(fun, "pcap");
[9ce251c7]2208 if (rc != EOK) {
2209 ddf_msg(LVL_ERROR, "Failed adding function to category pcap");
[17a8fcf]2210 goto err_add_to_cat;
[9ce251c7]2211 }
[17a8fcf]2212
[bf84871]2213 return EOK;
[a35b458]2214
[e86b8f0]2215err_add_to_cat:
2216 ddf_fun_unbind(fun);
2217err_fun_bind:
[bf84871]2218err_rx_structure:
[c4be33a]2219 e1000_uninitialize_rx_structure(nic);
[bf84871]2220err_irq:
[eadaeae8]2221 unregister_interrupt_handler(dev, irq_handle);
[e86b8f0]2222err_fun_create:
2223 ddf_fun_destroy(fun);
2224 nic_set_ddf_fun(nic, NULL);
[bf84871]2225err_tx_structure:
[c4be33a]2226 e1000_uninitialize_tx_structure(e1000);
[bf84871]2227err_pio:
[1df224c]2228 // TODO: e1000_pio_disable(dev);
[bf84871]2229err_destroy:
2230 e1000_dev_cleanup(dev);
2231 return rc;
[1df224c]2232}
[bf84871]2233
2234/** Read 16-bit value from EEPROM of E1000 adapter
[1df224c]2235 *
2236 * Read using the EERD register.
2237 *
2238 * @param device E1000 device
2239 * @param eeprom_address 8-bit EEPROM address
2240 *
2241 * @return 16-bit value from EEPROM
2242 *
[bf84871]2243 */
[c4be33a]2244static uint16_t e1000_eeprom_read(e1000_t *e1000, uint8_t eeprom_address)
[bf84871]2245{
[c4be33a]2246 fibril_mutex_lock(&e1000->eeprom_lock);
[a35b458]2247
[1df224c]2248 /* Write address and START bit to EERD register */
[77c2b02]2249 uint32_t write_data = e1000->info.eerd_start |
2250 (((uint32_t) eeprom_address) <<
2251 e1000->info.eerd_address_offset);
[c4be33a]2252 E1000_REG_WRITE(e1000, E1000_EERD, write_data);
[a35b458]2253
[c4be33a]2254 uint32_t eerd = E1000_REG_READ(e1000, E1000_EERD);
[77c2b02]2255 while ((eerd & e1000->info.eerd_done) == 0) {
[5f97ef44]2256 fibril_usleep(1);
[c4be33a]2257 eerd = E1000_REG_READ(e1000, E1000_EERD);
[bf84871]2258 }
[a35b458]2259
[c4be33a]2260 fibril_mutex_unlock(&e1000->eeprom_lock);
[a35b458]2261
[77c2b02]2262 return (uint16_t) (eerd >> e1000->info.eerd_data_offset);
[bf84871]2263}
2264
2265/** Get MAC address of the E1000 adapter
2266 *
[1df224c]2267 * @param device E1000 device
2268 * @param address Place to store the address
2269 * @param max_len Maximal addresss length to store
2270 *
2271 * @return EOK if succeed
[cde999a]2272 * @return An error code otherwise
[1df224c]2273 *
[bf84871]2274 */
[b7fd2a0]2275static errno_t e1000_get_address(e1000_t *e1000, nic_address_t *address)
[bf84871]2276{
[c4be33a]2277 fibril_mutex_lock(&e1000->rx_lock);
[a35b458]2278
[1df224c]2279 uint8_t *mac0_dest = (uint8_t *) address->address;
2280 uint8_t *mac1_dest = (uint8_t *) address->address + 1;
2281 uint8_t *mac2_dest = (uint8_t *) address->address + 2;
2282 uint8_t *mac3_dest = (uint8_t *) address->address + 3;
2283 uint8_t *mac4_dest = (uint8_t *) address->address + 4;
2284 uint8_t *mac5_dest = (uint8_t *) address->address + 5;
[a35b458]2285
[c4be33a]2286 uint32_t rah = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
2287 uint32_t ral = E1000_REG_READ(e1000, E1000_RAL_ARRAY(0));
[a35b458]2288
[bf84871]2289 *mac0_dest = (uint8_t) ral;
2290 *mac1_dest = (uint8_t) (ral >> 8);
2291 *mac2_dest = (uint8_t) (ral >> 16);
2292 *mac3_dest = (uint8_t) (ral >> 24);
2293 *mac4_dest = (uint8_t) rah;
2294 *mac5_dest = (uint8_t) (rah >> 8);
[a35b458]2295
[c4be33a]2296 fibril_mutex_unlock(&e1000->rx_lock);
[bf84871]2297 return EOK;
[84239b1]2298}
[bf84871]2299
2300/** Set card MAC address
2301 *
[1df224c]2302 * @param device E1000 device
2303 * @param address Address
2304 *
2305 * @return EOK if succeed
[cde999a]2306 * @return An error code otherwise
[bf84871]2307 */
[b7fd2a0]2308static errno_t e1000_set_addr(ddf_fun_t *fun, const nic_address_t *addr)
[bf84871]2309{
[56fd7cf]2310 nic_t *nic = NIC_DATA_FUN(fun);
[c4be33a]2311 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
[a35b458]2312
[c4be33a]2313 fibril_mutex_lock(&e1000->rx_lock);
2314 fibril_mutex_lock(&e1000->tx_lock);
[a35b458]2315
[b7fd2a0]2316 errno_t rc = nic_report_address(nic, addr);
[1df224c]2317 if (rc == EOK)
[c4be33a]2318 e1000_write_receive_address(e1000, 0, addr, false);
[a35b458]2319
[c4be33a]2320 fibril_mutex_unlock(&e1000->tx_lock);
2321 fibril_mutex_unlock(&e1000->rx_lock);
[a35b458]2322
[bf84871]2323 return rc;
2324}
2325
[c4be33a]2326static void e1000_eeprom_get_address(e1000_t *e1000,
[1df224c]2327 nic_address_t *address)
[bf84871]2328{
[1df224c]2329 uint16_t *mac0_dest = (uint16_t *) address->address;
2330 uint16_t *mac2_dest = (uint16_t *) (address->address + 2);
2331 uint16_t *mac4_dest = (uint16_t *) (address->address + 4);
[a35b458]2332
[c4be33a]2333 *mac0_dest = e1000_eeprom_read(e1000, 0);
2334 *mac2_dest = e1000_eeprom_read(e1000, 1);
2335 *mac4_dest = e1000_eeprom_read(e1000, 2);
[bf84871]2336}
2337
[6d8455d]2338/** Send frame
[1df224c]2339 *
[c4be33a]2340 * @param nic NIC driver data structure
[6d8455d]2341 * @param data Frame data
2342 * @param size Frame size in bytes
[bf84871]2343 *
[1df224c]2344 * @return EOK if succeed
2345 * @return Error code in the case of error
[bf84871]2346 *
2347 */
[6d8455d]2348static void e1000_send_frame(nic_t *nic, void *data, size_t size)
[bf84871]2349{
[c4be33a]2350 assert(nic);
[a35b458]2351
[c4be33a]2352 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2353 fibril_mutex_lock(&e1000->tx_lock);
[a35b458]2354
[c4be33a]2355 uint32_t tdt = E1000_REG_READ(e1000, E1000_TDT);
[1df224c]2356 e1000_tx_descriptor_t *tx_descriptor_addr = (e1000_tx_descriptor_t *)
[c4be33a]2357 (e1000->tx_ring_virt + tdt * sizeof(e1000_tx_descriptor_t));
[a35b458]2358
[bf84871]2359 bool descriptor_available = false;
[a35b458]2360
[1df224c]2361 /* Descriptor never used */
2362 if (tx_descriptor_addr->length == 0)
[bf84871]2363 descriptor_available = true;
[a35b458]2364
[1df224c]2365 /* Descriptor done */
[6d8455d]2366 if (tx_descriptor_addr->status & TXDESCRIPTOR_STATUS_DD)
[bf84871]2367 descriptor_available = true;
[a35b458]2368
[1df224c]2369 if (!descriptor_available) {
[1bc35b5]2370 /* Frame lost */
[c4be33a]2371 fibril_mutex_unlock(&e1000->tx_lock);
[bf84871]2372 return;
2373 }
[a35b458]2374
[6d8455d]2375 memcpy(e1000->tx_frame_virt[tdt], data, size);
2376 tx_descriptor_addr->phys_addr = PTR_TO_U64(e1000->tx_frame_phys[tdt]);
2377 tx_descriptor_addr->length = size;
[a35b458]2378
[1df224c]2379 /*
2380 * Report status to STATUS.DD (descriptor done),
2381 * add ethernet CRC, end of packet.
2382 */
2383 tx_descriptor_addr->command = TXDESCRIPTOR_COMMAND_RS |
2384 TXDESCRIPTOR_COMMAND_IFCS |
2385 TXDESCRIPTOR_COMMAND_EOP;
[a35b458]2386
[bf84871]2387 tx_descriptor_addr->checksum_offset = 0;
2388 tx_descriptor_addr->status = 0;
[c4be33a]2389 if (e1000->vlan_tag_add) {
2390 tx_descriptor_addr->special = e1000->vlan_tag;
[bf84871]2391 tx_descriptor_addr->command |= TXDESCRIPTOR_COMMAND_VLE;
[1df224c]2392 } else
2393 tx_descriptor_addr->special = 0;
[a35b458]2394
[bf84871]2395 tx_descriptor_addr->checksum_start_field = 0;
[a35b458]2396
[1df224c]2397 tdt++;
[1bc35b5]2398 if (tdt == E1000_TX_FRAME_COUNT)
[bf84871]2399 tdt = 0;
[a35b458]2400
[c4be33a]2401 E1000_REG_WRITE(e1000, E1000_TDT, tdt);
[a35b458]2402
[c4be33a]2403 fibril_mutex_unlock(&e1000->tx_lock);
[bf84871]2404}
2405
2406int main(void)
2407{
[869d936]2408 printf("%s: HelenOS E1000 network adapter driver\n", NAME);
[a35b458]2409
[869d936]2410 if (nic_driver_init(NAME) != EOK)
2411 return 1;
[a35b458]2412
[c4be33a]2413 nic_driver_implement(&e1000_driver_ops, &e1000_dev_ops,
2414 &e1000_nic_iface);
[a35b458]2415
[267f235]2416 ddf_log_init(NAME);
[bf84871]2417 return ddf_driver_main(&e1000_driver);
2418}
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