source: mainline/uspace/drv/nic/e1k/e1k.c@ 9ce251c7

Last change on this file since 9ce251c7 was 9ce251c7, checked in by Nataliia Korop <n.corop08@…>, 10 months ago

moved to nic, fixed all except addressing
  • Property mode set to 100644
File size: 56.5 KB
Line 
1/*
2 * Copyright (c) 2011 Zdenek Bouska
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @file e1k.c
30 *
31 * Driver for Intel Pro/1000 8254x Family of Gigabit Ethernet Controllers
32 *
33 */
34
35#include <async.h>
36#include <assert.h>
37#include <stdio.h>
38#include <errno.h>
39#include <adt/list.h>
40#include <align.h>
41#include <byteorder.h>
42#include <as.h>
43#include <ddi.h>
44#include <ddf/log.h>
45#include <ddf/interrupt.h>
46#include <device/hw_res.h>
47#include <device/hw_res_parsed.h>
48#include <pci_dev_iface.h>
49#include <nic.h>
50#include <ops/nic.h>
51#include <pcapdump_iface.h>
52#include "e1k.h"
53
54#define NAME "e1k"
55
56#define E1000_DEFAULT_INTERRUPT_INTERVAL_USEC 250
57
58/* Must be power of 8 */
59#define E1000_RX_FRAME_COUNT 128
60#define E1000_TX_FRAME_COUNT 128
61
62#define E1000_RECEIVE_ADDRESS 16
63
64/** Maximum sending frame size */
65#define E1000_MAX_SEND_FRAME_SIZE 2048
66/** Maximum receiving frame size */
67#define E1000_MAX_RECEIVE_FRAME_SIZE 2048
68
69/** nic_driver_data_t* -> e1000_t* cast */
70#define DRIVER_DATA_NIC(nic) \
71 ((e1000_t *) nic_get_specific(nic))
72
73/** ddf_fun_t * -> nic_driver_data_t* cast */
74#define NIC_DATA_FUN(fun) \
75 ((nic_t *) ddf_dev_data_get(ddf_fun_get_dev(fun)))
76
77/** ddf_dev_t * -> nic_driver_data_t* cast */
78#define NIC_DATA_DEV(dev) \
79 ((nic_t *) ddf_dev_data_get(dev))
80
81/** ddf_dev_t * -> e1000_t* cast */
82#define DRIVER_DATA_DEV(dev) \
83 (DRIVER_DATA_NIC(NIC_DATA_DEV(dev)))
84
85/** ddf_fun_t * -> e1000_t* cast */
86#define DRIVER_DATA_FUN(fun) \
87 (DRIVER_DATA_NIC(NIC_DATA_FUN(fun)))
88
89/** Cast pointer to uint64_t
90 *
91 * @param ptr Pointer to cast
92 *
93 * @return The uint64_t pointer representation.
94 *
95 */
96#define PTR_TO_U64(ptr) ((uint64_t) ((uintptr_t) (ptr)))
97
98/** Cast the memaddr part to the void*
99 *
100 * @param memaddr The memaddr value
101 *
102 */
103#define MEMADDR_TO_PTR(memaddr) ((void *) ((size_t) (memaddr)))
104
105#define E1000_REG_BASE(e1000) \
106 ((e1000)->reg_base_virt)
107
108#define E1000_REG_ADDR(e1000, reg) \
109 ((uint32_t *) (E1000_REG_BASE(e1000) + reg))
110
111#define E1000_REG_READ(e1000, reg) \
112 (pio_read_32(E1000_REG_ADDR(e1000, reg)))
113
114#define E1000_REG_WRITE(e1000, reg, value) \
115 (pio_write_32(E1000_REG_ADDR(e1000, reg), value))
116
117/** E1000 device data */
118typedef struct {
119 /** DDF device */
120 ddf_dev_t *dev;
121 /** Parent session */
122 async_sess_t *parent_sess;
123 /** Device configuration */
124 e1000_info_t info;
125
126 /** Physical registers base address */
127 void *reg_base_phys;
128 /** Virtual registers base address */
129 void *reg_base_virt;
130
131 /** Physical tx ring address */
132 uintptr_t tx_ring_phys;
133 /** Virtual tx ring address */
134 void *tx_ring_virt;
135
136 /** Ring of TX frames, physical address */
137 uintptr_t *tx_frame_phys;
138 /** Ring of TX frames, virtual address */
139 void **tx_frame_virt;
140
141 /** Physical rx ring address */
142 uintptr_t rx_ring_phys;
143 /** Virtual rx ring address */
144 void *rx_ring_virt;
145
146 /** Ring of RX frames, physical address */
147 uintptr_t *rx_frame_phys;
148 /** Ring of RX frames, virtual address */
149 void **rx_frame_virt;
150
151 /** VLAN tag */
152 uint16_t vlan_tag;
153
154 /** Add VLAN tag to frame */
155 bool vlan_tag_add;
156
157 /** Used unicast Receive Address count */
158 unsigned int unicast_ra_count;
159
160 /** Used milticast Receive addrress count */
161 unsigned int multicast_ra_count;
162
163 /** The irq assigned */
164 int irq;
165
166 /** Lock for CTRL register */
167 fibril_mutex_t ctrl_lock;
168
169 /** Lock for receiver */
170 fibril_mutex_t rx_lock;
171
172 /** Lock for transmitter */
173 fibril_mutex_t tx_lock;
174
175 /** Lock for EEPROM access */
176 fibril_mutex_t eeprom_lock;
177
178} e1000_t;
179
180/** Global mutex for work with shared irq structure */
181FIBRIL_MUTEX_INITIALIZE(irq_reg_mutex);
182
183static errno_t e1000_get_address(e1000_t *, nic_address_t *);
184static void e1000_eeprom_get_address(e1000_t *, nic_address_t *);
185static errno_t e1000_set_addr(ddf_fun_t *, const nic_address_t *);
186
187static errno_t e1000_defective_get_mode(ddf_fun_t *, uint32_t *);
188static errno_t e1000_defective_set_mode(ddf_fun_t *, uint32_t);
189
190static errno_t e1000_get_cable_state(ddf_fun_t *, nic_cable_state_t *);
191static errno_t e1000_get_device_info(ddf_fun_t *, nic_device_info_t *);
192static errno_t e1000_get_operation_mode(ddf_fun_t *, int *,
193 nic_channel_mode_t *, nic_role_t *);
194static errno_t e1000_set_operation_mode(ddf_fun_t *, int,
195 nic_channel_mode_t, nic_role_t);
196static errno_t e1000_autoneg_enable(ddf_fun_t *, uint32_t);
197static errno_t e1000_autoneg_disable(ddf_fun_t *);
198static errno_t e1000_autoneg_restart(ddf_fun_t *);
199
200static errno_t e1000_vlan_set_tag(ddf_fun_t *, uint16_t, bool, bool);
201
202/** Network interface options for E1000 card driver */
203static nic_iface_t e1000_nic_iface;
204
205/** Network interface options for E1000 card driver */
206static nic_iface_t e1000_nic_iface = {
207 .set_address = &e1000_set_addr,
208 .get_device_info = &e1000_get_device_info,
209 .get_cable_state = &e1000_get_cable_state,
210 .get_operation_mode = &e1000_get_operation_mode,
211 .set_operation_mode = &e1000_set_operation_mode,
212 .autoneg_enable = &e1000_autoneg_enable,
213 .autoneg_disable = &e1000_autoneg_disable,
214 .autoneg_restart = &e1000_autoneg_restart,
215 .vlan_set_tag = &e1000_vlan_set_tag,
216 .defective_get_mode = &e1000_defective_get_mode,
217 .defective_set_mode = &e1000_defective_set_mode,
218};
219
220/** Basic device operations for E1000 driver */
221static ddf_dev_ops_t e1000_dev_ops;
222
223static errno_t e1000_dev_add(ddf_dev_t *);
224
225/** Basic driver operations for E1000 driver */
226static driver_ops_t e1000_driver_ops = {
227 .dev_add = e1000_dev_add
228};
229
230/** Driver structure for E1000 driver */
231static driver_t e1000_driver = {
232 .name = NAME,
233 .driver_ops = &e1000_driver_ops
234};
235
236/* The default implementation callbacks */
237static errno_t e1000_on_activating(nic_t *);
238static errno_t e1000_on_stopping(nic_t *);
239static void e1000_send_frame(nic_t *, void *, size_t);
240
241/** PIO ranges used in the IRQ code. */
242irq_pio_range_t e1000_irq_pio_ranges[] = {
243 {
244 .base = 0,
245 .size = PAGE_SIZE, /* XXX */
246 }
247};
248
249/** Commands to deal with interrupt
250 *
251 */
252irq_cmd_t e1000_irq_commands[] = {
253 {
254 /* Get the interrupt status */
255 .cmd = CMD_PIO_READ_32,
256 .addr = NULL,
257 .dstarg = 2
258 },
259 {
260 .cmd = CMD_AND,
261 .value = ICR_RXT0,
262 .srcarg = 2,
263 .dstarg = 1
264 },
265 {
266 .cmd = CMD_PREDICATE,
267 .value = 2,
268 .srcarg = 1
269 },
270 {
271 /* Disable interrupts until interrupt routine is finished */
272 .cmd = CMD_PIO_WRITE_32,
273 .addr = NULL,
274 .value = 0xffffffff
275 },
276 {
277 .cmd = CMD_ACCEPT
278 }
279};
280
281/** Interrupt code definition */
282irq_code_t e1000_irq_code = {
283 .rangecount = sizeof(e1000_irq_pio_ranges) /
284 sizeof(irq_pio_range_t),
285 .ranges = e1000_irq_pio_ranges,
286 .cmdcount = sizeof(e1000_irq_commands) / sizeof(irq_cmd_t),
287 .cmds = e1000_irq_commands
288};
289
290/** Get the device information
291 *
292 * @param dev NIC device
293 * @param info Information to fill
294 *
295 * @return EOK
296 *
297 */
298static errno_t e1000_get_device_info(ddf_fun_t *dev, nic_device_info_t *info)
299{
300 assert(dev);
301 assert(info);
302
303 memset(info, 0, sizeof(nic_device_info_t));
304
305 info->vendor_id = 0x8086;
306 str_cpy(info->vendor_name, NIC_VENDOR_MAX_LENGTH,
307 "Intel Corporation");
308 str_cpy(info->model_name, NIC_MODEL_MAX_LENGTH,
309 "Intel Pro");
310
311 info->ethernet_support[ETH_10M] = ETH_10BASE_T;
312 info->ethernet_support[ETH_100M] = ETH_100BASE_TX;
313 info->ethernet_support[ETH_1000M] = ETH_1000BASE_T;
314
315 return EOK;
316}
317
318/** Check the cable state
319 *
320 * @param[in] dev device
321 * @param[out] state state to fill
322 *
323 * @return EOK
324 *
325 */
326static errno_t e1000_get_cable_state(ddf_fun_t *fun, nic_cable_state_t *state)
327{
328 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
329 if (E1000_REG_READ(e1000, E1000_STATUS) & (STATUS_LU))
330 *state = NIC_CS_PLUGGED;
331 else
332 *state = NIC_CS_UNPLUGGED;
333
334 return EOK;
335}
336
337static uint16_t e1000_calculate_itr_interval_from_usecs(usec_t useconds)
338{
339 return useconds * 4;
340}
341
342/** Get operation mode of the device
343 *
344 */
345static errno_t e1000_get_operation_mode(ddf_fun_t *fun, int *speed,
346 nic_channel_mode_t *duplex, nic_role_t *role)
347{
348 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
349 uint32_t status = E1000_REG_READ(e1000, E1000_STATUS);
350
351 if (status & STATUS_FD)
352 *duplex = NIC_CM_FULL_DUPLEX;
353 else
354 *duplex = NIC_CM_HALF_DUPLEX;
355
356 uint32_t speed_bits =
357 (status >> STATUS_SPEED_SHIFT) & STATUS_SPEED_ALL;
358
359 if (speed_bits == STATUS_SPEED_10)
360 *speed = 10;
361 else if (speed_bits == STATUS_SPEED_100)
362 *speed = 100;
363 else if ((speed_bits == STATUS_SPEED_1000A) ||
364 (speed_bits == STATUS_SPEED_1000B))
365 *speed = 1000;
366
367 *role = NIC_ROLE_UNKNOWN;
368 return EOK;
369}
370
371static void e1000_link_restart(e1000_t *e1000)
372{
373 fibril_mutex_lock(&e1000->ctrl_lock);
374
375 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
376
377 if (ctrl & CTRL_SLU) {
378 ctrl &= ~(CTRL_SLU);
379 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
380 fibril_mutex_unlock(&e1000->ctrl_lock);
381
382 fibril_usleep(10);
383
384 fibril_mutex_lock(&e1000->ctrl_lock);
385 ctrl = E1000_REG_READ(e1000, E1000_CTRL);
386 ctrl |= CTRL_SLU;
387 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
388 }
389
390 fibril_mutex_unlock(&e1000->ctrl_lock);
391}
392
393/** Set operation mode of the device
394 *
395 */
396static errno_t e1000_set_operation_mode(ddf_fun_t *fun, int speed,
397 nic_channel_mode_t duplex, nic_role_t role)
398{
399 if ((speed != 10) && (speed != 100) && (speed != 1000))
400 return EINVAL;
401
402 if ((duplex != NIC_CM_HALF_DUPLEX) && (duplex != NIC_CM_FULL_DUPLEX))
403 return EINVAL;
404
405 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
406
407 fibril_mutex_lock(&e1000->ctrl_lock);
408 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
409
410 ctrl |= CTRL_FRCSPD;
411 ctrl |= CTRL_FRCDPLX;
412 ctrl &= ~(CTRL_ASDE);
413
414 if (duplex == NIC_CM_FULL_DUPLEX)
415 ctrl |= CTRL_FD;
416 else
417 ctrl &= ~(CTRL_FD);
418
419 ctrl &= ~(CTRL_SPEED_MASK);
420 if (speed == 1000)
421 ctrl |= CTRL_SPEED_1000 << CTRL_SPEED_SHIFT;
422 else if (speed == 100)
423 ctrl |= CTRL_SPEED_100 << CTRL_SPEED_SHIFT;
424 else
425 ctrl |= CTRL_SPEED_10 << CTRL_SPEED_SHIFT;
426
427 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
428
429 fibril_mutex_unlock(&e1000->ctrl_lock);
430
431 e1000_link_restart(e1000);
432
433 return EOK;
434}
435
436/** Enable auto-negotiation
437 *
438 * @param dev Device to update
439 * @param advertisement Ignored on E1000
440 *
441 * @return EOK if advertisement mode set successfully
442 *
443 */
444static errno_t e1000_autoneg_enable(ddf_fun_t *fun, uint32_t advertisement)
445{
446 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
447
448 fibril_mutex_lock(&e1000->ctrl_lock);
449
450 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
451
452 ctrl &= ~(CTRL_FRCSPD);
453 ctrl &= ~(CTRL_FRCDPLX);
454 ctrl |= CTRL_ASDE;
455
456 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
457
458 fibril_mutex_unlock(&e1000->ctrl_lock);
459
460 e1000_link_restart(e1000);
461
462 return EOK;
463}
464
465/** Disable auto-negotiation
466 *
467 * @param dev Device to update
468 *
469 * @return EOK
470 *
471 */
472static errno_t e1000_autoneg_disable(ddf_fun_t *fun)
473{
474 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
475
476 fibril_mutex_lock(&e1000->ctrl_lock);
477
478 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
479
480 ctrl |= CTRL_FRCSPD;
481 ctrl |= CTRL_FRCDPLX;
482 ctrl &= ~(CTRL_ASDE);
483
484 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
485
486 fibril_mutex_unlock(&e1000->ctrl_lock);
487
488 e1000_link_restart(e1000);
489
490 return EOK;
491}
492
493/** Restart auto-negotiation
494 *
495 * @param dev Device to update
496 *
497 * @return EOK if advertisement mode set successfully
498 *
499 */
500static errno_t e1000_autoneg_restart(ddf_fun_t *dev)
501{
502 return e1000_autoneg_enable(dev, 0);
503}
504
505/** Get state of acceptance of weird frames
506 *
507 * @param device Device to check
508 * @param[out] mode Current mode
509 *
510 */
511static errno_t e1000_defective_get_mode(ddf_fun_t *fun, uint32_t *mode)
512{
513 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
514
515 *mode = 0;
516 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
517 if (rctl & RCTL_SBP)
518 *mode = NIC_DEFECTIVE_BAD_CRC | NIC_DEFECTIVE_SHORT;
519
520 return EOK;
521}
522
523/** Set acceptance of weird frames
524 *
525 * @param device Device to update
526 * @param mode Mode to set
527 *
528 * @return ENOTSUP if the mode is not supported
529 * @return EOK of mode was set
530 *
531 */
532static errno_t e1000_defective_set_mode(ddf_fun_t *fun, uint32_t mode)
533{
534 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
535 errno_t rc = EOK;
536
537 fibril_mutex_lock(&e1000->rx_lock);
538
539 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
540 bool short_mode = (mode & NIC_DEFECTIVE_SHORT ? true : false);
541 bool bad_mode = (mode & NIC_DEFECTIVE_BAD_CRC ? true : false);
542
543 if (short_mode && bad_mode)
544 rctl |= RCTL_SBP;
545 else if ((!short_mode) && (!bad_mode))
546 rctl &= ~RCTL_SBP;
547 else
548 rc = ENOTSUP;
549
550 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
551
552 fibril_mutex_unlock(&e1000->rx_lock);
553 return rc;
554}
555
556/** Write receive address to RA registr
557 *
558 * @param e1000 E1000 data structure
559 * @param position RA register position
560 * @param address Ethernet address
561 * @param set_av_bit Set the Addtess Valid bit
562 *
563 */
564static void e1000_write_receive_address(e1000_t *e1000, unsigned int position,
565 const nic_address_t *address, bool set_av_bit)
566{
567 uint8_t *mac0 = (uint8_t *) address->address;
568 uint8_t *mac1 = (uint8_t *) address->address + 1;
569 uint8_t *mac2 = (uint8_t *) address->address + 2;
570 uint8_t *mac3 = (uint8_t *) address->address + 3;
571 uint8_t *mac4 = (uint8_t *) address->address + 4;
572 uint8_t *mac5 = (uint8_t *) address->address + 5;
573
574 uint32_t rah;
575 uint32_t ral;
576
577 ral = ((*mac3) << 24) | ((*mac2) << 16) | ((*mac1) << 8) | (*mac0);
578 rah = ((*mac5) << 8) | ((*mac4));
579
580 if (set_av_bit)
581 rah |= RAH_AV;
582 else
583 rah |= E1000_REG_READ(e1000, E1000_RAH_ARRAY(position)) & RAH_AV;
584
585 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(position), rah);
586 E1000_REG_WRITE(e1000, E1000_RAL_ARRAY(position), ral);
587}
588
589/** Disable receive address in RA registr
590 *
591 * Clear Address Valid bit
592 *
593 * @param e1000 E1000 data structure
594 * @param position RA register position
595 *
596 */
597static void e1000_disable_receive_address(e1000_t *e1000, unsigned int position)
598{
599 uint32_t rah = E1000_REG_READ(e1000, E1000_RAH_ARRAY(position));
600 rah = rah & ~RAH_AV;
601 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(position), rah);
602}
603
604/** Clear all unicast addresses from RA registers
605 *
606 * @param e1000 E1000 data structure
607 *
608 */
609static void e1000_clear_unicast_receive_addresses(e1000_t *e1000)
610{
611 for (unsigned int ra_num = 1;
612 ra_num <= e1000->unicast_ra_count;
613 ra_num++)
614 e1000_disable_receive_address(e1000, ra_num);
615
616 e1000->unicast_ra_count = 0;
617}
618
619/** Clear all multicast addresses from RA registers
620 *
621 * @param e1000 E1000 data structure
622 *
623 */
624static void e1000_clear_multicast_receive_addresses(e1000_t *e1000)
625{
626 unsigned int first_multicast_ra_num =
627 E1000_RECEIVE_ADDRESS - e1000->multicast_ra_count;
628
629 for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1;
630 ra_num >= first_multicast_ra_num;
631 ra_num--)
632 e1000_disable_receive_address(e1000, ra_num);
633
634 e1000->multicast_ra_count = 0;
635}
636
637/** Return receive address filter positions count usable for unicast
638 *
639 * @param e1000 E1000 data structure
640 *
641 * @return receive address filter positions count usable for unicast
642 *
643 */
644static unsigned int get_free_unicast_address_count(e1000_t *e1000)
645{
646 return E1000_RECEIVE_ADDRESS - 1 - e1000->multicast_ra_count;
647}
648
649/** Return receive address filter positions count usable for multicast
650 *
651 * @param e1000 E1000 data structure
652 *
653 * @return receive address filter positions count usable for multicast
654 *
655 */
656static unsigned int get_free_multicast_address_count(e1000_t *e1000)
657{
658 return E1000_RECEIVE_ADDRESS - 1 - e1000->unicast_ra_count;
659}
660
661/** Write unicast receive addresses to receive address filter registers
662 *
663 * @param e1000 E1000 data structure
664 * @param addr Pointer to address array
665 * @param addr_cnt Address array count
666 *
667 */
668static void e1000_add_unicast_receive_addresses(e1000_t *e1000,
669 const nic_address_t *addr, size_t addr_cnt)
670{
671 assert(addr_cnt <= get_free_unicast_address_count(e1000));
672
673 nic_address_t *addr_iterator = (nic_address_t *) addr;
674
675 /* ra_num = 0 is primary address */
676 for (unsigned int ra_num = 1;
677 ra_num <= addr_cnt;
678 ra_num++) {
679 e1000_write_receive_address(e1000, ra_num, addr_iterator, true);
680 addr_iterator++;
681 }
682}
683
684/** Write multicast receive addresses to receive address filter registers
685 *
686 * @param e1000 E1000 data structure
687 * @param addr Pointer to address array
688 * @param addr_cnt Address array count
689 *
690 */
691static void e1000_add_multicast_receive_addresses(e1000_t *e1000,
692 const nic_address_t *addr, size_t addr_cnt)
693{
694 assert(addr_cnt <= get_free_multicast_address_count(e1000));
695
696 nic_address_t *addr_iterator = (nic_address_t *) addr;
697
698 unsigned int first_multicast_ra_num = E1000_RECEIVE_ADDRESS - addr_cnt;
699 for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1;
700 ra_num >= first_multicast_ra_num;
701 ra_num--) {
702 e1000_write_receive_address(e1000, ra_num, addr_iterator, true);
703 addr_iterator++;
704 }
705}
706
707/** Disable receiving frames for default address
708 *
709 * @param e1000 E1000 data structure
710 *
711 */
712static void disable_ra0_address_filter(e1000_t *e1000)
713{
714 uint32_t rah0 = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
715 rah0 = rah0 & ~RAH_AV;
716 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(0), rah0);
717}
718
719/** Enable receiving frames for default address
720 *
721 * @param e1000 E1000 data structure
722 *
723 */
724static void enable_ra0_address_filter(e1000_t *e1000)
725{
726 uint32_t rah0 = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
727 rah0 = rah0 | RAH_AV;
728 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(0), rah0);
729}
730
731/** Disable unicast promiscuous mode
732 *
733 * @param e1000 E1000 data structure
734 *
735 */
736static void e1000_disable_unicast_promisc(e1000_t *e1000)
737{
738 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
739 rctl = rctl & ~RCTL_UPE;
740 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
741}
742
743/** Enable unicast promiscuous mode
744 *
745 * @param e1000 E1000 data structure
746 *
747 */
748static void e1000_enable_unicast_promisc(e1000_t *e1000)
749{
750 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
751 rctl = rctl | RCTL_UPE;
752 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
753}
754
755/** Disable multicast promiscuous mode
756 *
757 * @param e1000 E1000 data structure
758 *
759 */
760static void e1000_disable_multicast_promisc(e1000_t *e1000)
761{
762 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
763 rctl = rctl & ~RCTL_MPE;
764 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
765}
766
767/** Enable multicast promiscuous mode
768 *
769 * @param e1000 E1000 data structure
770 *
771 */
772static void e1000_enable_multicast_promisc(e1000_t *e1000)
773{
774 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
775 rctl = rctl | RCTL_MPE;
776 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
777}
778
779/** Enable accepting of broadcast frames
780 *
781 * @param e1000 E1000 data structure
782 *
783 */
784static void e1000_enable_broadcast_accept(e1000_t *e1000)
785{
786 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
787 rctl = rctl | RCTL_BAM;
788 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
789}
790
791/** Disable accepting of broadcast frames
792 *
793 * @param e1000 E1000 data structure
794 *
795 */
796static void e1000_disable_broadcast_accept(e1000_t *e1000)
797{
798 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
799 rctl = rctl & ~RCTL_BAM;
800 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
801}
802
803/** Enable VLAN filtering according to VFTA registers
804 *
805 * @param e1000 E1000 data structure
806 *
807 */
808static void e1000_enable_vlan_filter(e1000_t *e1000)
809{
810 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
811 rctl = rctl | RCTL_VFE;
812 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
813}
814
815/** Disable VLAN filtering
816 *
817 * @param e1000 E1000 data structure
818 *
819 */
820static void e1000_disable_vlan_filter(e1000_t *e1000)
821{
822 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
823 rctl = rctl & ~RCTL_VFE;
824 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
825}
826
827/** Set multicast frames acceptance mode
828 *
829 * @param nic NIC device to update
830 * @param mode Mode to set
831 * @param addr Address list (used in mode = NIC_MULTICAST_LIST)
832 * @param addr_cnt Length of address list (used in mode = NIC_MULTICAST_LIST)
833 *
834 * @return EOK
835 *
836 */
837static errno_t e1000_on_multicast_mode_change(nic_t *nic, nic_multicast_mode_t mode,
838 const nic_address_t *addr, size_t addr_cnt)
839{
840 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
841 errno_t rc = EOK;
842
843 fibril_mutex_lock(&e1000->rx_lock);
844
845 switch (mode) {
846 case NIC_MULTICAST_BLOCKED:
847 e1000_clear_multicast_receive_addresses(e1000);
848 e1000_disable_multicast_promisc(e1000);
849 nic_report_hw_filtering(nic, -1, 1, -1);
850 break;
851 case NIC_MULTICAST_LIST:
852 e1000_clear_multicast_receive_addresses(e1000);
853 if (addr_cnt > get_free_multicast_address_count(e1000)) {
854 /*
855 * Future work: fill MTA table
856 * Not strictly neccessary, it only saves some compares
857 * in the NIC library.
858 */
859 e1000_enable_multicast_promisc(e1000);
860 nic_report_hw_filtering(nic, -1, 0, -1);
861 } else {
862 e1000_disable_multicast_promisc(e1000);
863 e1000_add_multicast_receive_addresses(e1000, addr, addr_cnt);
864 nic_report_hw_filtering(nic, -1, 1, -1);
865 }
866 break;
867 case NIC_MULTICAST_PROMISC:
868 e1000_enable_multicast_promisc(e1000);
869 e1000_clear_multicast_receive_addresses(e1000);
870 nic_report_hw_filtering(nic, -1, 1, -1);
871 break;
872 default:
873 rc = ENOTSUP;
874 break;
875 }
876
877 fibril_mutex_unlock(&e1000->rx_lock);
878 return rc;
879}
880
881/** Set unicast frames acceptance mode
882 *
883 * @param nic NIC device to update
884 * @param mode Mode to set
885 * @param addr Address list (used in mode = NIC_MULTICAST_LIST)
886 * @param addr_cnt Length of address list (used in mode = NIC_MULTICAST_LIST)
887 *
888 * @return EOK
889 *
890 */
891static errno_t e1000_on_unicast_mode_change(nic_t *nic, nic_unicast_mode_t mode,
892 const nic_address_t *addr, size_t addr_cnt)
893{
894 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
895 errno_t rc = EOK;
896
897 fibril_mutex_lock(&e1000->rx_lock);
898
899 switch (mode) {
900 case NIC_UNICAST_BLOCKED:
901 disable_ra0_address_filter(e1000);
902 e1000_clear_unicast_receive_addresses(e1000);
903 e1000_disable_unicast_promisc(e1000);
904 nic_report_hw_filtering(nic, 1, -1, -1);
905 break;
906 case NIC_UNICAST_DEFAULT:
907 enable_ra0_address_filter(e1000);
908 e1000_clear_unicast_receive_addresses(e1000);
909 e1000_disable_unicast_promisc(e1000);
910 nic_report_hw_filtering(nic, 1, -1, -1);
911 break;
912 case NIC_UNICAST_LIST:
913 enable_ra0_address_filter(e1000);
914 e1000_clear_unicast_receive_addresses(e1000);
915 if (addr_cnt > get_free_unicast_address_count(e1000)) {
916 e1000_enable_unicast_promisc(e1000);
917 nic_report_hw_filtering(nic, 0, -1, -1);
918 } else {
919 e1000_disable_unicast_promisc(e1000);
920 e1000_add_unicast_receive_addresses(e1000, addr, addr_cnt);
921 nic_report_hw_filtering(nic, 1, -1, -1);
922 }
923 break;
924 case NIC_UNICAST_PROMISC:
925 e1000_enable_unicast_promisc(e1000);
926 enable_ra0_address_filter(e1000);
927 e1000_clear_unicast_receive_addresses(e1000);
928 nic_report_hw_filtering(nic, 1, -1, -1);
929 break;
930 default:
931 rc = ENOTSUP;
932 break;
933 }
934
935 fibril_mutex_unlock(&e1000->rx_lock);
936 return rc;
937}
938
939/** Set broadcast frames acceptance mode
940 *
941 * @param nic NIC device to update
942 * @param mode Mode to set
943 *
944 * @return EOK
945 *
946 */
947static errno_t e1000_on_broadcast_mode_change(nic_t *nic, nic_broadcast_mode_t mode)
948{
949 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
950 errno_t rc = EOK;
951
952 fibril_mutex_lock(&e1000->rx_lock);
953
954 switch (mode) {
955 case NIC_BROADCAST_BLOCKED:
956 e1000_disable_broadcast_accept(e1000);
957 break;
958 case NIC_BROADCAST_ACCEPTED:
959 e1000_enable_broadcast_accept(e1000);
960 break;
961 default:
962 rc = ENOTSUP;
963 break;
964 }
965
966 fibril_mutex_unlock(&e1000->rx_lock);
967 return rc;
968}
969
970/** Check if receiving is enabled
971 *
972 * @param e1000 E1000 data structure
973 *
974 * @return true if receiving is enabled
975 *
976 */
977static bool e1000_is_rx_enabled(e1000_t *e1000)
978{
979 if (E1000_REG_READ(e1000, E1000_RCTL) & (RCTL_EN))
980 return true;
981
982 return false;
983}
984
985/** Enable receiving
986 *
987 * @param e1000 E1000 data structure
988 *
989 */
990static void e1000_enable_rx(e1000_t *e1000)
991{
992 /* Set Receive Enable Bit */
993 E1000_REG_WRITE(e1000, E1000_RCTL,
994 E1000_REG_READ(e1000, E1000_RCTL) | (RCTL_EN));
995}
996
997/** Disable receiving
998 *
999 * @param e1000 E1000 data structure
1000 *
1001 */
1002static void e1000_disable_rx(e1000_t *e1000)
1003{
1004 /* Clear Receive Enable Bit */
1005 E1000_REG_WRITE(e1000, E1000_RCTL,
1006 E1000_REG_READ(e1000, E1000_RCTL) & ~(RCTL_EN));
1007}
1008
1009/** Set VLAN mask
1010 *
1011 * @param nic NIC device to update
1012 * @param vlan_mask VLAN mask
1013 *
1014 */
1015static void e1000_on_vlan_mask_change(nic_t *nic,
1016 const nic_vlan_mask_t *vlan_mask)
1017{
1018 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1019
1020 fibril_mutex_lock(&e1000->rx_lock);
1021
1022 if (vlan_mask) {
1023 /*
1024 * Disable receiving, so that frame matching
1025 * partially written VLAN is not received.
1026 */
1027 bool rx_enabled = e1000_is_rx_enabled(e1000);
1028 if (rx_enabled)
1029 e1000_disable_rx(e1000);
1030
1031 for (unsigned int i = 0; i < NIC_VLAN_BITMAP_SIZE; i += 4) {
1032 uint32_t bitmap_part =
1033 ((uint32_t) vlan_mask->bitmap[i]) |
1034 (((uint32_t) vlan_mask->bitmap[i + 1]) << 8) |
1035 (((uint32_t) vlan_mask->bitmap[i + 2]) << 16) |
1036 (((uint32_t) vlan_mask->bitmap[i + 3]) << 24);
1037 E1000_REG_WRITE(e1000, E1000_VFTA_ARRAY(i / 4), bitmap_part);
1038 }
1039
1040 e1000_enable_vlan_filter(e1000);
1041 if (rx_enabled)
1042 e1000_enable_rx(e1000);
1043 } else
1044 e1000_disable_vlan_filter(e1000);
1045
1046 fibril_mutex_unlock(&e1000->rx_lock);
1047}
1048
1049/** Set VLAN mask
1050 *
1051 * @param device E1000 device
1052 * @param tag VLAN tag
1053 *
1054 * @return EOK
1055 * @return ENOTSUP
1056 *
1057 */
1058static errno_t e1000_vlan_set_tag(ddf_fun_t *fun, uint16_t tag, bool add,
1059 bool strip)
1060{
1061 /* VLAN CFI bit cannot be set */
1062 if (tag & VLANTAG_CFI)
1063 return ENOTSUP;
1064
1065 /*
1066 * CTRL.VME is neccessary for both strip and add
1067 * but CTRL.VME means stripping tags on receive.
1068 */
1069 if (!strip && add)
1070 return ENOTSUP;
1071
1072 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
1073
1074 e1000->vlan_tag = tag;
1075 e1000->vlan_tag_add = add;
1076
1077 fibril_mutex_lock(&e1000->ctrl_lock);
1078
1079 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1080 if (strip)
1081 ctrl |= CTRL_VME;
1082 else
1083 ctrl &= ~CTRL_VME;
1084
1085 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1086
1087 fibril_mutex_unlock(&e1000->ctrl_lock);
1088 return EOK;
1089}
1090
1091/** Fill receive descriptor with new empty buffer
1092 *
1093 * Store frame in e1000->rx_frame_phys
1094 *
1095 * @param nic NIC data stricture
1096 * @param offset Receive descriptor offset
1097 *
1098 */
1099static void e1000_fill_new_rx_descriptor(nic_t *nic, size_t offset)
1100{
1101 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1102
1103 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1104 (e1000->rx_ring_virt + offset * sizeof(e1000_rx_descriptor_t));
1105
1106 rx_descriptor->phys_addr = PTR_TO_U64(e1000->rx_frame_phys[offset]);
1107 rx_descriptor->length = 0;
1108 rx_descriptor->checksum = 0;
1109 rx_descriptor->status = 0;
1110 rx_descriptor->errors = 0;
1111 rx_descriptor->special = 0;
1112}
1113
1114/** Clear receive descriptor
1115 *
1116 * @param e1000 E1000 data
1117 * @param offset Receive descriptor offset
1118 *
1119 */
1120static void e1000_clear_rx_descriptor(e1000_t *e1000, unsigned int offset)
1121{
1122 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1123 (e1000->rx_ring_virt + offset * sizeof(e1000_rx_descriptor_t));
1124
1125 rx_descriptor->length = 0;
1126 rx_descriptor->checksum = 0;
1127 rx_descriptor->status = 0;
1128 rx_descriptor->errors = 0;
1129 rx_descriptor->special = 0;
1130}
1131
1132/** Clear receive descriptor
1133 *
1134 * @param nic NIC data
1135 * @param offset Receive descriptor offset
1136 *
1137 */
1138static void e1000_clear_tx_descriptor(nic_t *nic, unsigned int offset)
1139{
1140 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1141
1142 e1000_tx_descriptor_t *tx_descriptor = (e1000_tx_descriptor_t *)
1143 (e1000->tx_ring_virt + offset * sizeof(e1000_tx_descriptor_t));
1144
1145 tx_descriptor->phys_addr = 0;
1146 tx_descriptor->length = 0;
1147 tx_descriptor->checksum_offset = 0;
1148 tx_descriptor->command = 0;
1149 tx_descriptor->status = 0;
1150 tx_descriptor->checksum_start_field = 0;
1151 tx_descriptor->special = 0;
1152}
1153
1154/** Increment tail pointer for receive or transmit ring
1155 *
1156 * @param tail Old Tail
1157 * @param descriptors_count Ring length
1158 *
1159 * @return New tail
1160 *
1161 */
1162static uint32_t e1000_inc_tail(uint32_t tail, uint32_t descriptors_count)
1163{
1164 if (tail + 1 == descriptors_count)
1165 return 0;
1166 else
1167 return tail + 1;
1168}
1169
1170/** Receive frames
1171 *
1172 * @param nic NIC data
1173 *
1174 */
1175static void e1000_receive_frames(nic_t *nic)
1176{
1177 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1178
1179 fibril_mutex_lock(&e1000->rx_lock);
1180
1181 uint32_t *tail_addr = E1000_REG_ADDR(e1000, E1000_RDT);
1182 uint32_t next_tail = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1183
1184 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1185 (e1000->rx_ring_virt + next_tail * sizeof(e1000_rx_descriptor_t));
1186
1187 while (rx_descriptor->status & 0x01) {
1188 uint32_t frame_size = rx_descriptor->length - E1000_CRC_SIZE;
1189
1190 nic_frame_t *frame = nic_alloc_frame(nic, frame_size);
1191 if (frame != NULL) {
1192 memcpy(frame->data, e1000->rx_frame_virt[next_tail], frame_size);
1193
1194 nic_received_frame(nic, frame);
1195 } else {
1196 ddf_msg(LVL_ERROR, "Memory allocation failed. Frame dropped.");
1197 }
1198
1199 e1000_fill_new_rx_descriptor(nic, next_tail);
1200
1201 *tail_addr = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1202 next_tail = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1203
1204 rx_descriptor = (e1000_rx_descriptor_t *)
1205 (e1000->rx_ring_virt + next_tail * sizeof(e1000_rx_descriptor_t));
1206 }
1207
1208 fibril_mutex_unlock(&e1000->rx_lock);
1209}
1210
1211/** Enable E1000 interupts
1212 *
1213 * @param e1000 E1000 data structure
1214 *
1215 */
1216static void e1000_enable_interrupts(e1000_t *e1000)
1217{
1218 E1000_REG_WRITE(e1000, E1000_IMS, ICR_RXT0);
1219}
1220
1221/** Disable E1000 interupts
1222 *
1223 * @param e1000 E1000 data structure
1224 *
1225 */
1226static void e1000_disable_interrupts(e1000_t *e1000)
1227{
1228 E1000_REG_WRITE(e1000, E1000_IMS, 0);
1229}
1230
1231/** Interrupt handler implementation
1232 *
1233 * This function is called from e1000_interrupt_handler()
1234 * and e1000_poll()
1235 *
1236 * @param nic NIC data
1237 * @param icr ICR register value
1238 *
1239 */
1240static void e1000_interrupt_handler_impl(nic_t *nic, uint32_t icr)
1241{
1242 if (icr & ICR_RXT0)
1243 e1000_receive_frames(nic);
1244}
1245
1246/** Handle device interrupt
1247 *
1248 * @param icall IPC call structure
1249 * @param arg Argument (nic_t *)
1250 *
1251 */
1252static void e1000_interrupt_handler(ipc_call_t *icall, void *arg)
1253{
1254 uint32_t icr = (uint32_t) ipc_get_arg2(icall);
1255 nic_t *nic = (nic_t *)arg;
1256 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1257
1258 e1000_interrupt_handler_impl(nic, icr);
1259 e1000_enable_interrupts(e1000);
1260}
1261
1262/** Register interrupt handler for the card in the system
1263 *
1264 * Note: The global irq_reg_mutex is locked because of work with global
1265 * structure.
1266 *
1267 * @param nic Driver data
1268 *
1269 * @param[out] handle IRQ capability handle if the handler was registered
1270 *
1271 * @return An error code otherwise
1272 *
1273 */
1274inline static errno_t e1000_register_int_handler(nic_t *nic,
1275 cap_irq_handle_t *handle)
1276{
1277 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1278
1279 /* Lock the mutex in whole driver while working with global structure */
1280 fibril_mutex_lock(&irq_reg_mutex);
1281
1282 e1000_irq_code.ranges[0].base = (uintptr_t) e1000->reg_base_phys;
1283 e1000_irq_code.cmds[0].addr = e1000->reg_base_phys + E1000_ICR;
1284 e1000_irq_code.cmds[3].addr = e1000->reg_base_phys + E1000_IMC;
1285
1286 errno_t rc = register_interrupt_handler(nic_get_ddf_dev(nic), e1000->irq,
1287 e1000_interrupt_handler, (void *)nic, &e1000_irq_code, handle);
1288
1289 fibril_mutex_unlock(&irq_reg_mutex);
1290 return rc;
1291}
1292
1293/** Force receiving all frames in the receive buffer
1294 *
1295 * @param nic NIC data
1296 *
1297 */
1298static void e1000_poll(nic_t *nic)
1299{
1300 assert(nic);
1301
1302 e1000_t *e1000 = nic_get_specific(nic);
1303 assert(e1000);
1304
1305 uint32_t icr = E1000_REG_READ(e1000, E1000_ICR);
1306 e1000_interrupt_handler_impl(nic, icr);
1307}
1308
1309/** Calculates ITR register interrupt from timespec structure
1310 *
1311 * @param period Period
1312 *
1313 */
1314static uint16_t e1000_calculate_itr_interval(const struct timespec *period)
1315{
1316 // TODO: use also tv_sec
1317 return e1000_calculate_itr_interval_from_usecs(NSEC2USEC(period->tv_nsec));
1318}
1319
1320/** Set polling mode
1321 *
1322 * @param device Device to set
1323 * @param mode Mode to set
1324 * @param period Period for NIC_POLL_PERIODIC
1325 *
1326 * @return EOK if succeed
1327 * @return ENOTSUP if the mode is not supported
1328 *
1329 */
1330static errno_t e1000_poll_mode_change(nic_t *nic, nic_poll_mode_t mode,
1331 const struct timespec *period)
1332{
1333 assert(nic);
1334
1335 e1000_t *e1000 = nic_get_specific(nic);
1336 assert(e1000);
1337
1338 switch (mode) {
1339 case NIC_POLL_IMMEDIATE:
1340 E1000_REG_WRITE(e1000, E1000_ITR, 0);
1341 e1000_enable_interrupts(e1000);
1342 break;
1343 case NIC_POLL_ON_DEMAND:
1344 e1000_disable_interrupts(e1000);
1345 break;
1346 case NIC_POLL_PERIODIC:
1347 assert(period);
1348 uint16_t itr_interval = e1000_calculate_itr_interval(period);
1349 E1000_REG_WRITE(e1000, E1000_ITR, (uint32_t) itr_interval);
1350 e1000_enable_interrupts(e1000);
1351 break;
1352 default:
1353 return ENOTSUP;
1354 }
1355
1356 return EOK;
1357}
1358
1359/** Initialize receive registers
1360 *
1361 * @param e1000 E1000 data structure
1362 *
1363 */
1364static void e1000_initialize_rx_registers(e1000_t *e1000)
1365{
1366 E1000_REG_WRITE(e1000, E1000_RDLEN, E1000_RX_FRAME_COUNT * 16);
1367 E1000_REG_WRITE(e1000, E1000_RDH, 0);
1368
1369 /* It is not posible to let HW use all descriptors */
1370 E1000_REG_WRITE(e1000, E1000_RDT, E1000_RX_FRAME_COUNT - 1);
1371
1372 /* Set Broadcast Enable Bit */
1373 E1000_REG_WRITE(e1000, E1000_RCTL, RCTL_BAM);
1374}
1375
1376/** Initialize receive structure
1377 *
1378 * @param nic NIC data
1379 *
1380 * @return EOK if succeed
1381 * @return An error code otherwise
1382 *
1383 */
1384static errno_t e1000_initialize_rx_structure(nic_t *nic)
1385{
1386 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1387 fibril_mutex_lock(&e1000->rx_lock);
1388
1389 e1000->rx_ring_virt = AS_AREA_ANY;
1390 errno_t rc = dmamem_map_anonymous(
1391 E1000_RX_FRAME_COUNT * sizeof(e1000_rx_descriptor_t),
1392 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0,
1393 &e1000->rx_ring_phys, &e1000->rx_ring_virt);
1394 if (rc != EOK)
1395 return rc;
1396
1397 E1000_REG_WRITE(e1000, E1000_RDBAH,
1398 (uint32_t) (PTR_TO_U64(e1000->rx_ring_phys) >> 32));
1399 E1000_REG_WRITE(e1000, E1000_RDBAL,
1400 (uint32_t) PTR_TO_U64(e1000->rx_ring_phys));
1401
1402 e1000->rx_frame_phys = (uintptr_t *)
1403 calloc(E1000_RX_FRAME_COUNT, sizeof(uintptr_t));
1404 e1000->rx_frame_virt =
1405 calloc(E1000_RX_FRAME_COUNT, sizeof(void *));
1406 if ((e1000->rx_frame_phys == NULL) || (e1000->rx_frame_virt == NULL)) {
1407 rc = ENOMEM;
1408 goto error;
1409 }
1410
1411 for (size_t i = 0; i < E1000_RX_FRAME_COUNT; i++) {
1412 uintptr_t frame_phys;
1413 void *frame_virt = AS_AREA_ANY;
1414
1415 rc = dmamem_map_anonymous(E1000_MAX_SEND_FRAME_SIZE,
1416 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0,
1417 &frame_phys, &frame_virt);
1418 if (rc != EOK)
1419 goto error;
1420
1421 e1000->rx_frame_phys[i] = frame_phys;
1422 e1000->rx_frame_virt[i] = frame_virt;
1423 }
1424
1425 /* Write descriptor */
1426 for (size_t i = 0; i < E1000_RX_FRAME_COUNT; i++)
1427 e1000_fill_new_rx_descriptor(nic, i);
1428
1429 e1000_initialize_rx_registers(e1000);
1430
1431 fibril_mutex_unlock(&e1000->rx_lock);
1432 return EOK;
1433
1434error:
1435 for (size_t i = 0; i < E1000_RX_FRAME_COUNT; i++) {
1436 if (e1000->rx_frame_virt[i] != NULL) {
1437 dmamem_unmap_anonymous(e1000->rx_frame_virt[i]);
1438 e1000->rx_frame_phys[i] = 0;
1439 e1000->rx_frame_virt[i] = NULL;
1440 }
1441 }
1442
1443 if (e1000->rx_frame_phys != NULL) {
1444 free(e1000->rx_frame_phys);
1445 e1000->rx_frame_phys = NULL;
1446 }
1447
1448 if (e1000->rx_frame_virt != NULL) {
1449 free(e1000->rx_frame_virt);
1450 e1000->rx_frame_virt = NULL;
1451 }
1452
1453 return rc;
1454}
1455
1456/** Uninitialize receive structure
1457 *
1458 * @param nic NIC data
1459 *
1460 */
1461static void e1000_uninitialize_rx_structure(nic_t *nic)
1462{
1463 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1464
1465 /* Write descriptor */
1466 for (unsigned int offset = 0; offset < E1000_RX_FRAME_COUNT; offset++) {
1467 dmamem_unmap_anonymous(e1000->rx_frame_virt[offset]);
1468 e1000->rx_frame_phys[offset] = 0;
1469 e1000->rx_frame_virt[offset] = NULL;
1470 }
1471
1472 free(e1000->rx_frame_virt);
1473
1474 e1000->rx_frame_phys = NULL;
1475 e1000->rx_frame_virt = NULL;
1476
1477 dmamem_unmap_anonymous(e1000->rx_ring_virt);
1478}
1479
1480/** Clear receive descriptor ring
1481 *
1482 * @param e1000 E1000 data
1483 *
1484 */
1485static void e1000_clear_rx_ring(e1000_t *e1000)
1486{
1487 /* Write descriptor */
1488 for (unsigned int offset = 0;
1489 offset < E1000_RX_FRAME_COUNT;
1490 offset++)
1491 e1000_clear_rx_descriptor(e1000, offset);
1492}
1493
1494/** Initialize filters
1495 *
1496 * @param e1000 E1000 data
1497 *
1498 */
1499static void e1000_initialize_filters(e1000_t *e1000)
1500{
1501 /* Initialize address filter */
1502 e1000->unicast_ra_count = 0;
1503 e1000->multicast_ra_count = 0;
1504 e1000_clear_unicast_receive_addresses(e1000);
1505}
1506
1507/** Initialize VLAN
1508 *
1509 * @param e1000 E1000 data
1510 *
1511 */
1512static void e1000_initialize_vlan(e1000_t *e1000)
1513{
1514 e1000->vlan_tag_add = false;
1515}
1516
1517/** Fill MAC address from EEPROM to RA[0] register
1518 *
1519 * @param e1000 E1000 data
1520 *
1521 */
1522static void e1000_fill_mac_from_eeprom(e1000_t *e1000)
1523{
1524 /* MAC address from eeprom to RA[0] */
1525 nic_address_t address;
1526 e1000_eeprom_get_address(e1000, &address);
1527 e1000_write_receive_address(e1000, 0, &address, true);
1528}
1529
1530/** Initialize other registers
1531 *
1532 * @param dev E1000 data.
1533 *
1534 * @return EOK if succeed
1535 * @return An error code otherwise
1536 *
1537 */
1538static void e1000_initialize_registers(e1000_t *e1000)
1539{
1540 E1000_REG_WRITE(e1000, E1000_ITR,
1541 e1000_calculate_itr_interval_from_usecs(
1542 E1000_DEFAULT_INTERRUPT_INTERVAL_USEC));
1543 E1000_REG_WRITE(e1000, E1000_FCAH, 0);
1544 E1000_REG_WRITE(e1000, E1000_FCAL, 0);
1545 E1000_REG_WRITE(e1000, E1000_FCT, 0);
1546 E1000_REG_WRITE(e1000, E1000_FCTTV, 0);
1547 E1000_REG_WRITE(e1000, E1000_VET, VET_VALUE);
1548 E1000_REG_WRITE(e1000, E1000_CTRL, CTRL_ASDE);
1549}
1550
1551/** Initialize transmit registers
1552 *
1553 * @param e1000 E1000 data.
1554 *
1555 */
1556static void e1000_initialize_tx_registers(e1000_t *e1000)
1557{
1558 E1000_REG_WRITE(e1000, E1000_TDLEN, E1000_TX_FRAME_COUNT * 16);
1559 E1000_REG_WRITE(e1000, E1000_TDH, 0);
1560 E1000_REG_WRITE(e1000, E1000_TDT, 0);
1561
1562 E1000_REG_WRITE(e1000, E1000_TIPG,
1563 10 << TIPG_IPGT_SHIFT |
1564 8 << TIPG_IPGR1_SHIFT |
1565 6 << TIPG_IPGR2_SHIFT);
1566
1567 E1000_REG_WRITE(e1000, E1000_TCTL,
1568 0x0F << TCTL_CT_SHIFT /* Collision Threshold */ |
1569 0x40 << TCTL_COLD_SHIFT /* Collision Distance */ |
1570 TCTL_PSP /* Pad Short Packets */);
1571}
1572
1573/** Initialize transmit structure
1574 *
1575 * @param e1000 E1000 data.
1576 *
1577 */
1578static errno_t e1000_initialize_tx_structure(e1000_t *e1000)
1579{
1580 size_t i;
1581
1582 fibril_mutex_lock(&e1000->tx_lock);
1583
1584 e1000->tx_ring_phys = 0;
1585 e1000->tx_ring_virt = AS_AREA_ANY;
1586
1587 e1000->tx_frame_phys = NULL;
1588 e1000->tx_frame_virt = NULL;
1589
1590 errno_t rc = dmamem_map_anonymous(
1591 E1000_TX_FRAME_COUNT * sizeof(e1000_tx_descriptor_t),
1592 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0,
1593 &e1000->tx_ring_phys, &e1000->tx_ring_virt);
1594 if (rc != EOK)
1595 goto error;
1596
1597 memset(e1000->tx_ring_virt, 0,
1598 E1000_TX_FRAME_COUNT * sizeof(e1000_tx_descriptor_t));
1599
1600 e1000->tx_frame_phys = (uintptr_t *)
1601 calloc(E1000_TX_FRAME_COUNT, sizeof(uintptr_t));
1602 e1000->tx_frame_virt =
1603 calloc(E1000_TX_FRAME_COUNT, sizeof(void *));
1604
1605 if ((e1000->tx_frame_phys == NULL) || (e1000->tx_frame_virt == NULL)) {
1606 rc = ENOMEM;
1607 goto error;
1608 }
1609
1610 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1611 e1000->tx_frame_virt[i] = AS_AREA_ANY;
1612 rc = dmamem_map_anonymous(E1000_MAX_SEND_FRAME_SIZE,
1613 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE,
1614 0, &e1000->tx_frame_phys[i], &e1000->tx_frame_virt[i]);
1615 if (rc != EOK)
1616 goto error;
1617 }
1618
1619 E1000_REG_WRITE(e1000, E1000_TDBAH,
1620 (uint32_t) (PTR_TO_U64(e1000->tx_ring_phys) >> 32));
1621 E1000_REG_WRITE(e1000, E1000_TDBAL,
1622 (uint32_t) PTR_TO_U64(e1000->tx_ring_phys));
1623
1624 e1000_initialize_tx_registers(e1000);
1625
1626 fibril_mutex_unlock(&e1000->tx_lock);
1627 return EOK;
1628
1629error:
1630 if (e1000->tx_ring_virt != NULL) {
1631 dmamem_unmap_anonymous(e1000->tx_ring_virt);
1632 e1000->tx_ring_virt = NULL;
1633 }
1634
1635 if ((e1000->tx_frame_phys != NULL) && (e1000->tx_frame_virt != NULL)) {
1636 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1637 if (e1000->tx_frame_virt[i] != NULL) {
1638 dmamem_unmap_anonymous(e1000->tx_frame_virt[i]);
1639 e1000->tx_frame_phys[i] = 0;
1640 e1000->tx_frame_virt[i] = NULL;
1641 }
1642 }
1643 }
1644
1645 if (e1000->tx_frame_phys != NULL) {
1646 free(e1000->tx_frame_phys);
1647 e1000->tx_frame_phys = NULL;
1648 }
1649
1650 if (e1000->tx_frame_virt != NULL) {
1651 free(e1000->tx_frame_virt);
1652 e1000->tx_frame_virt = NULL;
1653 }
1654
1655 return rc;
1656}
1657
1658/** Uninitialize transmit structure
1659 *
1660 * @param nic NIC data
1661 *
1662 */
1663static void e1000_uninitialize_tx_structure(e1000_t *e1000)
1664{
1665 size_t i;
1666
1667 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1668 dmamem_unmap_anonymous(e1000->tx_frame_virt[i]);
1669 e1000->tx_frame_phys[i] = 0;
1670 e1000->tx_frame_virt[i] = NULL;
1671 }
1672
1673 if (e1000->tx_frame_phys != NULL) {
1674 free(e1000->tx_frame_phys);
1675 e1000->tx_frame_phys = NULL;
1676 }
1677
1678 if (e1000->tx_frame_virt != NULL) {
1679 free(e1000->tx_frame_virt);
1680 e1000->tx_frame_virt = NULL;
1681 }
1682
1683 dmamem_unmap_anonymous(e1000->tx_ring_virt);
1684}
1685
1686/** Clear transmit descriptor ring
1687 *
1688 * @param nic NIC data
1689 *
1690 */
1691static void e1000_clear_tx_ring(nic_t *nic)
1692{
1693 /* Write descriptor */
1694 for (unsigned int offset = 0;
1695 offset < E1000_TX_FRAME_COUNT;
1696 offset++)
1697 e1000_clear_tx_descriptor(nic, offset);
1698}
1699
1700/** Enable transmit
1701 *
1702 * @param e1000 E1000 data
1703 *
1704 */
1705static void e1000_enable_tx(e1000_t *e1000)
1706{
1707 /* Set Transmit Enable Bit */
1708 E1000_REG_WRITE(e1000, E1000_TCTL,
1709 E1000_REG_READ(e1000, E1000_TCTL) | (TCTL_EN));
1710}
1711
1712/** Disable transmit
1713 *
1714 * @param e1000 E1000 data
1715 *
1716 */
1717static void e1000_disable_tx(e1000_t *e1000)
1718{
1719 /* Clear Transmit Enable Bit */
1720 E1000_REG_WRITE(e1000, E1000_TCTL,
1721 E1000_REG_READ(e1000, E1000_TCTL) & ~(TCTL_EN));
1722}
1723
1724/** Reset E1000 device
1725 *
1726 * @param e1000 The E1000 data
1727 *
1728 */
1729static errno_t e1000_reset(nic_t *nic)
1730{
1731 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1732
1733 E1000_REG_WRITE(e1000, E1000_CTRL, CTRL_RST);
1734
1735 /* Wait for the reset */
1736 fibril_usleep(20);
1737
1738 /* check if RST_BIT cleared */
1739 if (E1000_REG_READ(e1000, E1000_CTRL) & (CTRL_RST))
1740 return EINVAL;
1741
1742 e1000_initialize_registers(e1000);
1743 e1000_initialize_rx_registers(e1000);
1744 e1000_initialize_tx_registers(e1000);
1745 e1000_fill_mac_from_eeprom(e1000);
1746 e1000_initialize_filters(e1000);
1747 e1000_initialize_vlan(e1000);
1748
1749 return EOK;
1750}
1751
1752/** Activate the device to receive and transmit frames
1753 *
1754 * @param nic NIC driver data
1755 *
1756 * @return EOK if activated successfully
1757 * @return Error code otherwise
1758 *
1759 */
1760static errno_t e1000_on_activating(nic_t *nic)
1761{
1762 assert(nic);
1763
1764 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1765
1766 fibril_mutex_lock(&e1000->rx_lock);
1767 fibril_mutex_lock(&e1000->tx_lock);
1768 fibril_mutex_lock(&e1000->ctrl_lock);
1769
1770 e1000_enable_interrupts(e1000);
1771
1772 errno_t rc = hw_res_enable_interrupt(e1000->parent_sess, e1000->irq);
1773 if (rc != EOK) {
1774 e1000_disable_interrupts(e1000);
1775 fibril_mutex_unlock(&e1000->ctrl_lock);
1776 fibril_mutex_unlock(&e1000->tx_lock);
1777 fibril_mutex_unlock(&e1000->rx_lock);
1778 return rc;
1779 }
1780
1781 e1000_clear_rx_ring(e1000);
1782 e1000_enable_rx(e1000);
1783
1784 e1000_clear_tx_ring(nic);
1785 e1000_enable_tx(e1000);
1786
1787 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1788 ctrl |= CTRL_SLU;
1789 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1790
1791 fibril_mutex_unlock(&e1000->ctrl_lock);
1792 fibril_mutex_unlock(&e1000->tx_lock);
1793 fibril_mutex_unlock(&e1000->rx_lock);
1794
1795 return EOK;
1796}
1797
1798/** Callback for NIC_STATE_DOWN change
1799 *
1800 * @param nic NIC driver data
1801 *
1802 * @return EOK if succeed
1803 * @return Error code otherwise
1804 *
1805 */
1806static errno_t e1000_on_down_unlocked(nic_t *nic)
1807{
1808 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1809
1810 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1811 ctrl &= ~CTRL_SLU;
1812 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1813
1814 e1000_disable_tx(e1000);
1815 e1000_disable_rx(e1000);
1816
1817 hw_res_disable_interrupt(e1000->parent_sess, e1000->irq);
1818 e1000_disable_interrupts(e1000);
1819
1820 /*
1821 * Wait for the for the end of all data
1822 * transfers to descriptors.
1823 */
1824 fibril_usleep(100);
1825
1826 return EOK;
1827}
1828
1829/** Callback for NIC_STATE_DOWN change
1830 *
1831 * @param nic NIC driver data
1832 *
1833 * @return EOK if succeed
1834 * @return Error code otherwise
1835 *
1836 */
1837static errno_t e1000_on_down(nic_t *nic)
1838{
1839 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1840
1841 fibril_mutex_lock(&e1000->rx_lock);
1842 fibril_mutex_lock(&e1000->tx_lock);
1843 fibril_mutex_lock(&e1000->ctrl_lock);
1844
1845 errno_t rc = e1000_on_down_unlocked(nic);
1846
1847 fibril_mutex_unlock(&e1000->ctrl_lock);
1848 fibril_mutex_unlock(&e1000->tx_lock);
1849 fibril_mutex_unlock(&e1000->rx_lock);
1850
1851 return rc;
1852}
1853
1854/** Callback for NIC_STATE_STOPPED change
1855 *
1856 * @param nic NIC driver data
1857 *
1858 * @return EOK if succeed
1859 * @return Error code otherwise
1860 *
1861 */
1862static errno_t e1000_on_stopping(nic_t *nic)
1863{
1864 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1865
1866 fibril_mutex_lock(&e1000->rx_lock);
1867 fibril_mutex_lock(&e1000->tx_lock);
1868 fibril_mutex_lock(&e1000->ctrl_lock);
1869
1870 errno_t rc = e1000_on_down_unlocked(nic);
1871 if (rc == EOK)
1872 rc = e1000_reset(nic);
1873
1874 fibril_mutex_unlock(&e1000->ctrl_lock);
1875 fibril_mutex_unlock(&e1000->tx_lock);
1876 fibril_mutex_unlock(&e1000->rx_lock);
1877
1878 return rc;
1879}
1880
1881/** Create driver data structure
1882 *
1883 * @return Intialized device data structure or NULL
1884 *
1885 */
1886static e1000_t *e1000_create_dev_data(ddf_dev_t *dev)
1887{
1888 nic_t *nic = nic_create_and_bind(dev);
1889 if (!nic)
1890 return NULL;
1891
1892 e1000_t *e1000 = malloc(sizeof(e1000_t));
1893 if (!e1000) {
1894 nic_unbind_and_destroy(dev);
1895 return NULL;
1896 }
1897
1898 memset(e1000, 0, sizeof(e1000_t));
1899 e1000->dev = dev;
1900
1901 nic_set_specific(nic, e1000);
1902 nic_set_send_frame_handler(nic, e1000_send_frame);
1903 nic_set_state_change_handlers(nic, e1000_on_activating,
1904 e1000_on_down, e1000_on_stopping);
1905 nic_set_filtering_change_handlers(nic,
1906 e1000_on_unicast_mode_change, e1000_on_multicast_mode_change,
1907 e1000_on_broadcast_mode_change, NULL, e1000_on_vlan_mask_change);
1908 nic_set_poll_handlers(nic, e1000_poll_mode_change, e1000_poll);
1909
1910 fibril_mutex_initialize(&e1000->ctrl_lock);
1911 fibril_mutex_initialize(&e1000->rx_lock);
1912 fibril_mutex_initialize(&e1000->tx_lock);
1913 fibril_mutex_initialize(&e1000->eeprom_lock);
1914
1915 return e1000;
1916}
1917
1918/** Delete driver data structure
1919 *
1920 * @param data E1000 device data structure
1921 *
1922 */
1923inline static void e1000_delete_dev_data(ddf_dev_t *dev)
1924{
1925 assert(dev);
1926
1927 if (ddf_dev_data_get(dev) != NULL)
1928 nic_unbind_and_destroy(dev);
1929}
1930
1931/** Clean up the E1000 device structure.
1932 *
1933 * @param dev Device structure.
1934 *
1935 */
1936static void e1000_dev_cleanup(ddf_dev_t *dev)
1937{
1938 assert(dev);
1939
1940 e1000_delete_dev_data(dev);
1941}
1942
1943/** Fill the irq and io_addr part of device data structure
1944 *
1945 * The hw_resources must be obtained before calling this function
1946 *
1947 * @param dev Device structure
1948 * @param hw_resources Hardware resources obtained from the parent device
1949 *
1950 * @return EOK if succeed
1951 * @return An error code otherwise
1952 *
1953 */
1954static errno_t e1000_fill_resource_info(ddf_dev_t *dev,
1955 const hw_res_list_parsed_t *hw_resources)
1956{
1957 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
1958
1959 if (hw_resources->irqs.count != 1)
1960 return EINVAL;
1961
1962 e1000->irq = hw_resources->irqs.irqs[0];
1963 e1000->reg_base_phys =
1964 MEMADDR_TO_PTR(RNGABS(hw_resources->mem_ranges.ranges[0]));
1965
1966 return EOK;
1967}
1968
1969/** Obtain information about hardware resources of the device
1970 *
1971 * The device must be connected to the parent
1972 *
1973 * @param dev Device structure
1974 *
1975 * @return EOK if succeed
1976 * @return An error code otherwise
1977 *
1978 */
1979static errno_t e1000_get_resource_info(ddf_dev_t *dev)
1980{
1981 assert(dev != NULL);
1982 assert(NIC_DATA_DEV(dev) != NULL);
1983
1984 hw_res_list_parsed_t hw_res_parsed;
1985 hw_res_list_parsed_init(&hw_res_parsed);
1986
1987 /* Get hw resources form parent driver */
1988 errno_t rc = nic_get_resources(NIC_DATA_DEV(dev), &hw_res_parsed);
1989 if (rc != EOK)
1990 return rc;
1991
1992 /* Fill resources information to the device */
1993 rc = e1000_fill_resource_info(dev, &hw_res_parsed);
1994 hw_res_list_parsed_clean(&hw_res_parsed);
1995
1996 return rc;
1997}
1998
1999/** Initialize the E1000 device structure
2000 *
2001 * @param dev Device information
2002 *
2003 * @return EOK if succeed
2004 * @return An error code otherwise
2005 *
2006 */
2007static errno_t e1000_device_initialize(ddf_dev_t *dev)
2008{
2009 /* Allocate driver data for the device. */
2010 e1000_t *e1000 = e1000_create_dev_data(dev);
2011 if (e1000 == NULL) {
2012 ddf_msg(LVL_ERROR, "Unable to allocate device softstate");
2013 return ENOMEM;
2014 }
2015
2016 e1000->parent_sess = ddf_dev_parent_sess_get(dev);
2017 if (e1000->parent_sess == NULL) {
2018 ddf_msg(LVL_ERROR, "Failed connecting parent device.");
2019 return EIO;
2020 }
2021
2022 /* Obtain and fill hardware resources info */
2023 errno_t rc = e1000_get_resource_info(dev);
2024 if (rc != EOK) {
2025 ddf_msg(LVL_ERROR, "Cannot obtain hardware resources");
2026 e1000_dev_cleanup(dev);
2027 return rc;
2028 }
2029
2030 uint16_t device_id;
2031 rc = pci_config_space_read_16(ddf_dev_parent_sess_get(dev), PCI_DEVICE_ID,
2032 &device_id);
2033 if (rc != EOK) {
2034 ddf_msg(LVL_ERROR, "Cannot access PCI configuration space");
2035 e1000_dev_cleanup(dev);
2036 return rc;
2037 }
2038
2039 e1000_board_t board;
2040 switch (device_id) {
2041 case 0x100e:
2042 case 0x1015:
2043 case 0x1016:
2044 case 0x1017:
2045 board = E1000_82540;
2046 break;
2047 case 0x1013:
2048 case 0x1018:
2049 case 0x1078:
2050 board = E1000_82541;
2051 break;
2052 case 0x1076:
2053 case 0x1077:
2054 case 0x107c:
2055 board = E1000_82541REV2;
2056 break;
2057 case 0x100f:
2058 case 0x1011:
2059 case 0x1026:
2060 case 0x1027:
2061 case 0x1028:
2062 board = E1000_82545;
2063 break;
2064 case 0x1010:
2065 case 0x1012:
2066 case 0x101d:
2067 case 0x1079:
2068 case 0x107a:
2069 case 0x107b:
2070 board = E1000_82546;
2071 break;
2072 case 0x1019:
2073 case 0x101a:
2074 board = E1000_82547;
2075 break;
2076 case 0x10b9:
2077 board = E1000_82572;
2078 break;
2079 case 0x1096:
2080 board = E1000_80003ES2;
2081 break;
2082 default:
2083 ddf_msg(LVL_ERROR, "Device not supported (%#" PRIx16 ")",
2084 device_id);
2085 e1000_dev_cleanup(dev);
2086 return ENOTSUP;
2087 }
2088
2089 switch (board) {
2090 case E1000_82540:
2091 case E1000_82541:
2092 case E1000_82541REV2:
2093 case E1000_82545:
2094 case E1000_82546:
2095 e1000->info.eerd_start = 0x01;
2096 e1000->info.eerd_done = 0x10;
2097 e1000->info.eerd_address_offset = 8;
2098 e1000->info.eerd_data_offset = 16;
2099 break;
2100 case E1000_82547:
2101 case E1000_82572:
2102 case E1000_80003ES2:
2103 e1000->info.eerd_start = 0x01;
2104 e1000->info.eerd_done = 0x02;
2105 e1000->info.eerd_address_offset = 2;
2106 e1000->info.eerd_data_offset = 16;
2107 break;
2108 }
2109
2110 return EOK;
2111}
2112
2113/** Enable the I/O ports of the device.
2114 *
2115 * @param dev E1000 device.
2116 *
2117 * @return EOK if successed
2118 * @return An error code otherwise
2119 *
2120 */
2121static errno_t e1000_pio_enable(ddf_dev_t *dev)
2122{
2123 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
2124
2125 errno_t rc = pio_enable(e1000->reg_base_phys, 8 * PAGE_SIZE,
2126 &e1000->reg_base_virt);
2127 if (rc != EOK)
2128 return EADDRNOTAVAIL;
2129
2130 return EOK;
2131}
2132
2133/** Probe and initialize the newly added device.
2134 *
2135 * @param dev E1000 device.
2136 *
2137 */
2138errno_t e1000_dev_add(ddf_dev_t *dev)
2139{
2140 ddf_fun_t *fun;
2141
2142 /* Initialize device structure for E1000 */
2143 errno_t rc = e1000_device_initialize(dev);
2144 if (rc != EOK)
2145 return rc;
2146
2147 /* Device initialization */
2148 nic_t *nic = ddf_dev_data_get(dev);
2149 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2150
2151 /* Map registers */
2152 rc = e1000_pio_enable(dev);
2153 if (rc != EOK)
2154 goto err_destroy;
2155
2156 e1000_initialize_registers(e1000);
2157 rc = e1000_initialize_tx_structure(e1000);
2158 if (rc != EOK)
2159 goto err_pio;
2160
2161 fibril_mutex_lock(&e1000->rx_lock);
2162
2163 e1000_fill_mac_from_eeprom(e1000);
2164 e1000_initialize_filters(e1000);
2165
2166 fibril_mutex_unlock(&e1000->rx_lock);
2167
2168 e1000_initialize_vlan(e1000);
2169
2170 fun = ddf_fun_create(nic_get_ddf_dev(nic), fun_exposed, "port0");
2171 if (fun == NULL)
2172 goto err_tx_structure;
2173 nic_set_ddf_fun(nic, fun);
2174 ddf_fun_set_ops(fun, &e1000_dev_ops);
2175
2176 cap_irq_handle_t irq_handle;
2177 rc = e1000_register_int_handler(nic, &irq_handle);
2178 if (rc != EOK) {
2179 goto err_fun_create;
2180 }
2181
2182 rc = e1000_initialize_rx_structure(nic);
2183 if (rc != EOK)
2184 goto err_irq;
2185
2186 nic_address_t e1000_address;
2187 e1000_get_address(e1000, &e1000_address);
2188 rc = nic_report_address(nic, &e1000_address);
2189 if (rc != EOK)
2190 goto err_rx_structure;
2191
2192 struct timespec period;
2193 period.tv_sec = 0;
2194 period.tv_nsec = USEC2NSEC(E1000_DEFAULT_INTERRUPT_INTERVAL_USEC);
2195 rc = nic_report_poll_mode(nic, NIC_POLL_PERIODIC, &period);
2196 if (rc != EOK)
2197 goto err_rx_structure;
2198
2199 rc = ddf_fun_bind(fun);
2200 if (rc != EOK)
2201 goto err_fun_bind;
2202
2203 rc = ddf_fun_add_to_category(fun, DEVICE_CATEGORY_NIC);
2204 if (rc != EOK)
2205 goto err_add_to_cat;
2206
2207 rc = ddf_fun_add_to_category(fun, "pcap");
2208 if (rc != EOK) {
2209 ddf_msg(LVL_ERROR, "Failed adding function to category pcap");
2210 goto err_add_to_cat;
2211 }
2212
2213 return EOK;
2214
2215err_add_to_cat:
2216 ddf_fun_unbind(fun);
2217err_fun_bind:
2218err_rx_structure:
2219 e1000_uninitialize_rx_structure(nic);
2220err_irq:
2221 unregister_interrupt_handler(dev, irq_handle);
2222err_fun_create:
2223 ddf_fun_destroy(fun);
2224 nic_set_ddf_fun(nic, NULL);
2225err_tx_structure:
2226 e1000_uninitialize_tx_structure(e1000);
2227err_pio:
2228 // TODO: e1000_pio_disable(dev);
2229err_destroy:
2230 e1000_dev_cleanup(dev);
2231 return rc;
2232}
2233
2234/** Read 16-bit value from EEPROM of E1000 adapter
2235 *
2236 * Read using the EERD register.
2237 *
2238 * @param device E1000 device
2239 * @param eeprom_address 8-bit EEPROM address
2240 *
2241 * @return 16-bit value from EEPROM
2242 *
2243 */
2244static uint16_t e1000_eeprom_read(e1000_t *e1000, uint8_t eeprom_address)
2245{
2246 fibril_mutex_lock(&e1000->eeprom_lock);
2247
2248 /* Write address and START bit to EERD register */
2249 uint32_t write_data = e1000->info.eerd_start |
2250 (((uint32_t) eeprom_address) <<
2251 e1000->info.eerd_address_offset);
2252 E1000_REG_WRITE(e1000, E1000_EERD, write_data);
2253
2254 uint32_t eerd = E1000_REG_READ(e1000, E1000_EERD);
2255 while ((eerd & e1000->info.eerd_done) == 0) {
2256 fibril_usleep(1);
2257 eerd = E1000_REG_READ(e1000, E1000_EERD);
2258 }
2259
2260 fibril_mutex_unlock(&e1000->eeprom_lock);
2261
2262 return (uint16_t) (eerd >> e1000->info.eerd_data_offset);
2263}
2264
2265/** Get MAC address of the E1000 adapter
2266 *
2267 * @param device E1000 device
2268 * @param address Place to store the address
2269 * @param max_len Maximal addresss length to store
2270 *
2271 * @return EOK if succeed
2272 * @return An error code otherwise
2273 *
2274 */
2275static errno_t e1000_get_address(e1000_t *e1000, nic_address_t *address)
2276{
2277 fibril_mutex_lock(&e1000->rx_lock);
2278
2279 uint8_t *mac0_dest = (uint8_t *) address->address;
2280 uint8_t *mac1_dest = (uint8_t *) address->address + 1;
2281 uint8_t *mac2_dest = (uint8_t *) address->address + 2;
2282 uint8_t *mac3_dest = (uint8_t *) address->address + 3;
2283 uint8_t *mac4_dest = (uint8_t *) address->address + 4;
2284 uint8_t *mac5_dest = (uint8_t *) address->address + 5;
2285
2286 uint32_t rah = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
2287 uint32_t ral = E1000_REG_READ(e1000, E1000_RAL_ARRAY(0));
2288
2289 *mac0_dest = (uint8_t) ral;
2290 *mac1_dest = (uint8_t) (ral >> 8);
2291 *mac2_dest = (uint8_t) (ral >> 16);
2292 *mac3_dest = (uint8_t) (ral >> 24);
2293 *mac4_dest = (uint8_t) rah;
2294 *mac5_dest = (uint8_t) (rah >> 8);
2295
2296 fibril_mutex_unlock(&e1000->rx_lock);
2297 return EOK;
2298}
2299
2300/** Set card MAC address
2301 *
2302 * @param device E1000 device
2303 * @param address Address
2304 *
2305 * @return EOK if succeed
2306 * @return An error code otherwise
2307 */
2308static errno_t e1000_set_addr(ddf_fun_t *fun, const nic_address_t *addr)
2309{
2310 nic_t *nic = NIC_DATA_FUN(fun);
2311 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2312
2313 fibril_mutex_lock(&e1000->rx_lock);
2314 fibril_mutex_lock(&e1000->tx_lock);
2315
2316 errno_t rc = nic_report_address(nic, addr);
2317 if (rc == EOK)
2318 e1000_write_receive_address(e1000, 0, addr, false);
2319
2320 fibril_mutex_unlock(&e1000->tx_lock);
2321 fibril_mutex_unlock(&e1000->rx_lock);
2322
2323 return rc;
2324}
2325
2326static void e1000_eeprom_get_address(e1000_t *e1000,
2327 nic_address_t *address)
2328{
2329 uint16_t *mac0_dest = (uint16_t *) address->address;
2330 uint16_t *mac2_dest = (uint16_t *) (address->address + 2);
2331 uint16_t *mac4_dest = (uint16_t *) (address->address + 4);
2332
2333 *mac0_dest = e1000_eeprom_read(e1000, 0);
2334 *mac2_dest = e1000_eeprom_read(e1000, 1);
2335 *mac4_dest = e1000_eeprom_read(e1000, 2);
2336}
2337
2338/** Send frame
2339 *
2340 * @param nic NIC driver data structure
2341 * @param data Frame data
2342 * @param size Frame size in bytes
2343 *
2344 * @return EOK if succeed
2345 * @return Error code in the case of error
2346 *
2347 */
2348static void e1000_send_frame(nic_t *nic, void *data, size_t size)
2349{
2350 assert(nic);
2351
2352 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2353 fibril_mutex_lock(&e1000->tx_lock);
2354
2355 uint32_t tdt = E1000_REG_READ(e1000, E1000_TDT);
2356 e1000_tx_descriptor_t *tx_descriptor_addr = (e1000_tx_descriptor_t *)
2357 (e1000->tx_ring_virt + tdt * sizeof(e1000_tx_descriptor_t));
2358
2359 bool descriptor_available = false;
2360
2361 /* Descriptor never used */
2362 if (tx_descriptor_addr->length == 0)
2363 descriptor_available = true;
2364
2365 /* Descriptor done */
2366 if (tx_descriptor_addr->status & TXDESCRIPTOR_STATUS_DD)
2367 descriptor_available = true;
2368
2369 if (!descriptor_available) {
2370 /* Frame lost */
2371 fibril_mutex_unlock(&e1000->tx_lock);
2372 return;
2373 }
2374
2375 memcpy(e1000->tx_frame_virt[tdt], data, size);
2376 tx_descriptor_addr->phys_addr = PTR_TO_U64(e1000->tx_frame_phys[tdt]);
2377 tx_descriptor_addr->length = size;
2378
2379 /*
2380 * Report status to STATUS.DD (descriptor done),
2381 * add ethernet CRC, end of packet.
2382 */
2383 tx_descriptor_addr->command = TXDESCRIPTOR_COMMAND_RS |
2384 TXDESCRIPTOR_COMMAND_IFCS |
2385 TXDESCRIPTOR_COMMAND_EOP;
2386
2387 tx_descriptor_addr->checksum_offset = 0;
2388 tx_descriptor_addr->status = 0;
2389 if (e1000->vlan_tag_add) {
2390 tx_descriptor_addr->special = e1000->vlan_tag;
2391 tx_descriptor_addr->command |= TXDESCRIPTOR_COMMAND_VLE;
2392 } else
2393 tx_descriptor_addr->special = 0;
2394
2395 tx_descriptor_addr->checksum_start_field = 0;
2396
2397 tdt++;
2398 if (tdt == E1000_TX_FRAME_COUNT)
2399 tdt = 0;
2400
2401 E1000_REG_WRITE(e1000, E1000_TDT, tdt);
2402
2403 fibril_mutex_unlock(&e1000->tx_lock);
2404}
2405
2406int main(void)
2407{
2408 printf("%s: HelenOS E1000 network adapter driver\n", NAME);
2409
2410 if (nic_driver_init(NAME) != EOK)
2411 return 1;
2412
2413 nic_driver_implement(&e1000_driver_ops, &e1000_dev_ops,
2414 &e1000_nic_iface);
2415
2416 ddf_log_init(NAME);
2417 return ddf_driver_main(&e1000_driver);
2418}
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