Context Navigation

source: mainline/uspace/drv/bus/usb/xhci/hc.c@ 17d34a8

Visit:

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export

Last change on this file since 17d34a8 was 19f0048, checked in by Ondřej Hlavatý <aearsis@…>, 8 years ago
xhci: reinitialize in case of HC error
Property mode set to `100644`
File size: 30.2 KB

Line
1	/*
2	* Copyright (c) 2017 Ondrej Hlavaty
3	* All rights reserved.
4	*
5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions
7	* are met:
8	*
9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.
16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/
28
29	/** @addtogroup drvusbxhci
30	* @{
31	*/
32	/** @file
33	* @brief The host controller data bookkeeping.
34	*/
35
36	#include <errno.h>
37	#include <str_error.h>
38	#include <usb/debug.h>
39	#include <usb/host/endpoint.h>
40	#include "debug.h"
41	#include "hc.h"
42	#include "rh.h"
43	#include "hw_struct/trb.h"
44	#include "hw_struct/context.h"
45	#include "endpoint.h"
46	#include "transfers.h"
47	#include "trb_ring.h"
48
49	/**
50	* Default USB Speed ID mapping: Table 157
51	*/
52	#define PSI_TO_BPS(psie, psim) (((uint64_t) psim) << (10 * psie))
53	#define PORT_SPEED(usb, mjr, psie, psim) { \
54	.name = "USB ", \
55	.major = mjr, \
56	.minor = 0, \
57	.usb_speed = USB_SPEED_##usb, \
58	.rx_bps = PSI_TO_BPS(psie, psim), \
59	.tx_bps = PSI_TO_BPS(psie, psim) \
60	}
61
62	static const xhci_port_speed_t default_psiv_to_port_speed [] = {
63	[1] = PORT_SPEED(FULL, 2, 2, 12),
64	[2] = PORT_SPEED(LOW, 2, 1, 1500),
65	[3] = PORT_SPEED(HIGH, 2, 2, 480),
66	[4] = PORT_SPEED(SUPER, 3, 3, 5),
67	};
68
69	static const unsigned usb_speed_to_psiv [] = {
70	[USB_SPEED_FULL] = 1,
71	[USB_SPEED_LOW] = 2,
72	[USB_SPEED_HIGH] = 3,
73	[USB_SPEED_SUPER] = 4,
74	};
75
76	/**
77	* Walk the list of extended capabilities.
78	*
79	* The most interesting thing hidden in extended capabilities is the mapping of
80	* ports to protocol versions and speeds.
81	*/
82	static int hc_parse_ec(xhci_hc_t *hc)
83	{
84	unsigned psic, major, minor;
85	xhci_sp_name_t name;
86
87	xhci_port_speed_t *speeds = hc->speeds;
88
89	for (xhci_extcap_t *ec = hc->xecp; ec; ec = xhci_extcap_next(ec)) {
90	xhci_dump_extcap(ec);
91	switch (XHCI_REG_RD(ec, XHCI_EC_CAP_ID)) {
92	case XHCI_EC_USB_LEGACY:
93	assert(hc->legsup == NULL);
94	hc->legsup = (xhci_legsup_t *) ec;
95	break;
96	case XHCI_EC_SUPPORTED_PROTOCOL:
97	psic = XHCI_REG_RD(ec, XHCI_EC_SP_PSIC);
98	major = XHCI_REG_RD(ec, XHCI_EC_SP_MAJOR);
99	minor = XHCI_REG_RD(ec, XHCI_EC_SP_MINOR);
100	name.packed = host2uint32_t_le(XHCI_REG_RD(ec, XHCI_EC_SP_NAME));
101
102	if (name.packed != xhci_name_usb.packed) {
103	/**
104	* The detection of such protocol would work,
105	* but the rest of the implementation is made
106	* for the USB protocol only.
107	*/
108	usb_log_error("Unknown protocol %.4s.", name.str);
109	return ENOTSUP;
110	}
111
112	unsigned offset = XHCI_REG_RD(ec, XHCI_EC_SP_CP_OFF);
113	unsigned count = XHCI_REG_RD(ec, XHCI_EC_SP_CP_COUNT);
114	xhci_rh_set_ports_protocol(&hc->rh, offset, count, major);
115
116	// "Implied" speed
117	if (psic == 0) {
118	assert(minor == 0);
119
120	if (major == 2) {
121	speeds[1] = default_psiv_to_port_speed[1];
122	speeds[2] = default_psiv_to_port_speed[2];
123	speeds[3] = default_psiv_to_port_speed[3];
124	} else if (major == 3) {
125	speeds[4] = default_psiv_to_port_speed[4];
126	} else {
127	return EINVAL;
128	}
129
130	usb_log_debug("Implied speed of USB %u.0 set up.", major);
131	} else {
132	for (unsigned i = 0; i < psic; i++) {
133	xhci_psi_t *psi = xhci_extcap_psi(ec, i);
134	unsigned sim = XHCI_REG_RD(psi, XHCI_PSI_PSIM);
135	unsigned psiv = XHCI_REG_RD(psi, XHCI_PSI_PSIV);
136	unsigned psie = XHCI_REG_RD(psi, XHCI_PSI_PSIE);
137	unsigned psim = XHCI_REG_RD(psi, XHCI_PSI_PSIM);
138	uint64_t bps = PSI_TO_BPS(psie, psim);
139
140	/*
141	* Speed is not implied, but using one of default PSIV. This
142	* is not clearly stated in xHCI spec. There is a clear
143	* intention to allow xHCI to specify its own speed
144	* parameters, but throughout the document, they used fixed
145	* values for e.g. High-speed (3), without stating the
146	* controller shall have implied default speeds - and for
147	* instance Intel controllers do not. So let's check if the
148	* values match and if so, accept the implied USB speed too.
149	*
150	* The main reason we need this is the usb_speed to have
151	* mapping also for devices connected to hubs.
152	*/
153	if (psiv < ARRAY_SIZE(default_psiv_to_port_speed)
154	&& default_psiv_to_port_speed[psiv].major == major
155	&& default_psiv_to_port_speed[psiv].minor == minor
156	&& default_psiv_to_port_speed[psiv].rx_bps == bps
157	&& default_psiv_to_port_speed[psiv].tx_bps == bps) {
158	speeds[psiv] = default_psiv_to_port_speed[psiv];
159	usb_log_debug("Assumed default %s speed of USB %u.",
160	usb_str_speed(speeds[psiv].usb_speed), major);
161	continue;
162	}
163
164	// Custom speed
165	speeds[psiv].major = major;
166	speeds[psiv].minor = minor;
167	str_ncpy(speeds[psiv].name, 4, name.str, 4);
168	speeds[psiv].usb_speed = USB_SPEED_MAX;
169
170	if (sim == XHCI_PSI_PLT_SYMM \|\| sim == XHCI_PSI_PLT_RX)
171	speeds[psiv].rx_bps = bps;
172	if (sim == XHCI_PSI_PLT_SYMM \|\| sim == XHCI_PSI_PLT_TX) {
173	speeds[psiv].tx_bps = bps;
174	usb_log_debug("Speed %u set up for bps %" PRIu64
175	" / %" PRIu64 ".", psiv, speeds[psiv].rx_bps,
176	speeds[psiv].tx_bps);
177	}
178	}
179	}
180	}
181	}
182	return EOK;
183	}
184
185	/**
186	* Initialize MMIO spaces of xHC.
187	*/
188	int hc_init_mmio(xhci_hc_t hc, const hw_res_list_parsed_t hw_res)
189	{
190	int err;
191
192	if (hw_res->mem_ranges.count != 1) {
193	usb_log_error("Unexpected MMIO area, bailing out.");
194	return EINVAL;
195	}
196
197	hc->mmio_range = hw_res->mem_ranges.ranges[0];
198
199	usb_log_debug("MMIO area at %p (size %zu), IRQ %d.",
200	RNGABSPTR(hc->mmio_range), RNGSZ(hc->mmio_range), hw_res->irqs.irqs[0]);
201
202	if (RNGSZ(hc->mmio_range) < sizeof(xhci_cap_regs_t))
203	return EOVERFLOW;
204
205	void *base;
206	if ((err = pio_enable_range(&hc->mmio_range, &base)))
207	return err;
208
209	hc->reg_base = base;
210	hc->cap_regs = (xhci_cap_regs_t *) base;
211	hc->op_regs = (xhci_op_regs_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_LENGTH));
212	hc->rt_regs = (xhci_rt_regs_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF));
213	hc->db_arry = (xhci_doorbell_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_DBOFF));
214
215	uintptr_t xec_offset = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_XECP) * sizeof(xhci_dword_t);
216	if (xec_offset > 0)
217	hc->xecp = (xhci_extcap_t *) (base + xec_offset);
218
219	usb_log_debug("Initialized MMIO reg areas:");
220	usb_log_debug("\tCapability regs: %p", hc->cap_regs);
221	usb_log_debug("\tOperational regs: %p", hc->op_regs);
222	usb_log_debug("\tRuntime regs: %p", hc->rt_regs);
223	usb_log_debug("\tDoorbell array base: %p", hc->db_arry);
224
225	xhci_dump_cap_regs(hc->cap_regs);
226
227	hc->ac64 = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_AC64);
228	hc->csz = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_CSZ);
229	hc->max_slots = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_MAX_SLOTS);
230
231	struct timeval tv;
232	getuptime(&tv);
233	hc->wrap_time = tv.tv_sec * 1000000 + tv.tv_usec;
234	hc->wrap_count = 0;
235
236	unsigned ist = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_IST);
237	hc->ist = (ist & 0x10 >> 1) * (ist & 0xf);
238
239	if ((err = xhci_rh_init(&hc->rh, hc)))
240	goto err_pio;
241
242	if ((err = hc_parse_ec(hc)))
243	goto err_rh;
244
245	return EOK;
246
247	err_rh:
248	xhci_rh_fini(&hc->rh);
249	err_pio:
250	pio_disable(hc->reg_base, RNGSZ(hc->mmio_range));
251	return err;
252	}
253
254	static int event_worker(void *arg);
255
256	/**
257	* Initialize structures kept in allocated memory.
258	*/
259	int hc_init_memory(xhci_hc_t hc, ddf_dev_t device)
260	{
261	int err = ENOMEM;
262
263	if (dma_buffer_alloc(&hc->dcbaa_dma, (1 + hc->max_slots) * sizeof(uint64_t)))
264	return ENOMEM;
265	hc->dcbaa = hc->dcbaa_dma.virt;
266
267	hc->event_worker = joinable_fibril_create(&event_worker, hc);
268	if (!hc->event_worker)
269	goto err_dcbaa;
270
271	if ((err = xhci_event_ring_init(&hc->event_ring, 1)))
272	goto err_worker;
273
274	if ((err = xhci_scratchpad_alloc(hc)))
275	goto err_event_ring;
276
277	if ((err = xhci_init_commands(hc)))
278	goto err_scratch;
279
280	if ((err = xhci_bus_init(&hc->bus, hc)))
281	goto err_cmd;
282
283	xhci_sw_ring_init(&hc->sw_ring, PAGE_SIZE / sizeof(xhci_trb_t));
284
285	return EOK;
286
287	err_cmd:
288	xhci_fini_commands(hc);
289	err_scratch:
290	xhci_scratchpad_free(hc);
291	err_event_ring:
292	xhci_event_ring_fini(&hc->event_ring);
293	err_worker:
294	joinable_fibril_destroy(hc->event_worker);
295	err_dcbaa:
296	hc->dcbaa = NULL;
297	dma_buffer_free(&hc->dcbaa_dma);
298	return err;
299	}
300
301	/*
302	* Pseudocode:
303	* ip = read(intr[0].iman)
304	* if (ip) {
305	* status = read(usbsts)
306	* assert status
307	* assert ip
308	* accept (passing status)
309	* }
310	* decline
311	*/
312	static const irq_cmd_t irq_commands[] = {
313	{
314	.cmd = CMD_PIO_READ_32,
315	.dstarg = 3,
316	.addr = NULL /* intr[0].iman */
317	},
318	{
319	.cmd = CMD_AND,
320	.srcarg = 3,
321	.dstarg = 4,
322	.value = 0 /* host2xhci(32, 1) */
323	},
324	{
325	.cmd = CMD_PREDICATE,
326	.srcarg = 4,
327	.value = 5
328	},
329	{
330	.cmd = CMD_PIO_READ_32,
331	.dstarg = 1,
332	.addr = NULL /* usbsts */
333	},
334	{
335	.cmd = CMD_AND,
336	.srcarg = 1,
337	.dstarg = 2,
338	.value = 0 /* host2xhci(32, XHCI_STATUS_ACK_MASK) */
339	},
340	{
341	.cmd = CMD_PIO_WRITE_A_32,
342	.srcarg = 2,
343	.addr = NULL /* usbsts */
344	},
345	{
346	.cmd = CMD_PIO_WRITE_A_32,
347	.srcarg = 3,
348	.addr = NULL /* intr[0].iman */
349	},
350	{
351	.cmd = CMD_ACCEPT
352	},
353	{
354	.cmd = CMD_DECLINE
355	}
356	};
357
358
359	/**
360	* Generates code to accept interrupts. The xHCI is designed primarily for
361	* MSI/MSI-X, but we use PCI Interrupt Pin. In this mode, all the Interrupters
362	* (except 0) are disabled.
363	*/
364	int hc_irq_code_gen(irq_code_t code, xhci_hc_t hc, const hw_res_list_parsed_t hw_res, int irq)
365	{
366	assert(code);
367	assert(hw_res);
368
369	if (hw_res->irqs.count != 1) {
370	usb_log_info("Unexpected HW resources to enable interrupts.");
371	return EINVAL;
372	}
373
374	code->ranges = malloc(sizeof(irq_pio_range_t));
375	if (code->ranges == NULL)
376	return ENOMEM;
377
378	code->cmds = malloc(sizeof(irq_commands));
379	if (code->cmds == NULL) {
380	free(code->ranges);
381	return ENOMEM;
382	}
383
384	code->rangecount = 1;
385	code->ranges[0] = (irq_pio_range_t) {
386	.base = RNGABS(hc->mmio_range),
387	.size = RNGSZ(hc->mmio_range),
388	};
389
390	code->cmdcount = ARRAY_SIZE(irq_commands);
391	memcpy(code->cmds, irq_commands, sizeof(irq_commands));
392
393	void *intr0_iman = RNGABSPTR(hc->mmio_range)
394	+ XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF)
395	+ offsetof(xhci_rt_regs_t, ir[0]);
396	void *usbsts = RNGABSPTR(hc->mmio_range)
397	+ XHCI_REG_RD(hc->cap_regs, XHCI_CAP_LENGTH)
398	+ offsetof(xhci_op_regs_t, usbsts);
399
400	code->cmds[0].addr = intr0_iman;
401	code->cmds[1].value = host2xhci(32, 1);
402	code->cmds[3].addr = usbsts;
403	code->cmds[4].value = host2xhci(32, XHCI_STATUS_ACK_MASK);
404	code->cmds[5].addr = usbsts;
405	code->cmds[6].addr = intr0_iman;
406
407	*irq = hw_res->irqs.irqs[0];
408	return EOK;
409	}
410
411	/**
412	* Claim xHC from BIOS. Implements handoff as per Section 4.22.1 of xHCI spec.
413	*/
414	int hc_claim(xhci_hc_t hc, ddf_dev_t dev)
415	{
416	/* No legacy support capability, the controller is solely for us */
417	if (!hc->legsup)
418	return EOK;
419
420	if (xhci_reg_wait(&hc->op_regs->usbsts, XHCI_REG_MASK(XHCI_OP_CNR), 0))
421	return ETIMEOUT;
422
423	usb_log_debug("LEGSUP: bios: %x, os: %x", hc->legsup->sem_bios, hc->legsup->sem_os);
424	XHCI_REG_SET(hc->legsup, XHCI_LEGSUP_SEM_OS, 1);
425	for (int i = 0; i <= (XHCI_LEGSUP_BIOS_TIMEOUT_US / XHCI_LEGSUP_POLLING_DELAY_1MS); i++) {
426	usb_log_debug("LEGSUP: elapsed: %i ms, bios: %x, os: %x", i,
427	XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_BIOS),
428	XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_OS));
429	if (XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_BIOS) == 0) {
430	return XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_OS) == 1 ? EOK : EIO;
431	}
432	async_usleep(XHCI_LEGSUP_POLLING_DELAY_1MS);
433	}
434	usb_log_error("BIOS did not release XHCI legacy hold!");
435
436	return ENOTSUP;
437	}
438
439	/**
440	* Ask the xHC to reset its state. Implements sequence
441	*/
442	static int hc_reset(xhci_hc_t *hc)
443	{
444	if (xhci_reg_wait(&hc->op_regs->usbsts, XHCI_REG_MASK(XHCI_OP_CNR), 0))
445	return ETIMEOUT;
446
447	/* Stop the HC: set R/S to 0 */
448	XHCI_REG_CLR(hc->op_regs, XHCI_OP_RS, 1);
449
450	/* Wait until the HC is halted - it shall take at most 16 ms */
451	if (xhci_reg_wait(&hc->op_regs->usbsts, XHCI_REG_MASK(XHCI_OP_HCH),
452	XHCI_REG_MASK(XHCI_OP_HCH)))
453	return ETIMEOUT;
454
455	/* Reset */
456	XHCI_REG_SET(hc->op_regs, XHCI_OP_HCRST, 1);
457
458	/* Wait until the reset is complete */
459	if (xhci_reg_wait(&hc->op_regs->usbcmd, XHCI_REG_MASK(XHCI_OP_HCRST), 0))
460	return ETIMEOUT;
461
462	return EOK;
463	}
464
465	/**
466	* Initialize the HC: section 4.2
467	*/
468	int hc_start(xhci_hc_t *hc)
469	{
470	int err;
471
472	if ((err = hc_reset(hc)))
473	return err;
474
475	if (xhci_reg_wait(&hc->op_regs->usbsts, XHCI_REG_MASK(XHCI_OP_CNR), 0))
476	return ETIMEOUT;
477
478	uint64_t dcbaaptr = hc->dcbaa_dma.phys;
479	XHCI_REG_WR(hc->op_regs, XHCI_OP_DCBAAP_LO, LOWER32(dcbaaptr));
480	XHCI_REG_WR(hc->op_regs, XHCI_OP_DCBAAP_HI, UPPER32(dcbaaptr));
481	XHCI_REG_WR(hc->op_regs, XHCI_OP_MAX_SLOTS_EN, hc->max_slots);
482
483	uintptr_t crcr;
484	xhci_trb_ring_reset_dequeue_state(&hc->cr.trb_ring, &crcr);
485	XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_LO, LOWER32(crcr));
486	XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_HI, UPPER32(crcr));
487
488	XHCI_REG_SET(hc->op_regs, XHCI_OP_EWE, 1);
489
490	xhci_event_ring_reset(&hc->event_ring);
491
492	xhci_interrupter_regs_t *intr0 = &hc->rt_regs->ir[0];
493	XHCI_REG_WR(intr0, XHCI_INTR_ERSTSZ, hc->event_ring.segment_count);
494	uint64_t erdp = hc->event_ring.dequeue_ptr;
495	XHCI_REG_WR(intr0, XHCI_INTR_ERDP_LO, LOWER32(erdp));
496	XHCI_REG_WR(intr0, XHCI_INTR_ERDP_HI, UPPER32(erdp));
497	uint64_t erstptr = hc->event_ring.erst.phys;
498	XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA_LO, LOWER32(erstptr));
499	XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA_HI, UPPER32(erstptr));
500
501	if (hc->base.irq_cap > 0) {
502	XHCI_REG_SET(intr0, XHCI_INTR_IE, 1);
503	XHCI_REG_SET(hc->op_regs, XHCI_OP_INTE, 1);
504	}
505
506	XHCI_REG_SET(hc->op_regs, XHCI_OP_HSEE, 1);
507
508	xhci_sw_ring_restart(&hc->sw_ring);
509	joinable_fibril_start(hc->event_worker);
510
511	xhci_start_command_ring(hc);
512
513	XHCI_REG_SET(hc->op_regs, XHCI_OP_RS, 1);
514
515	/* RH needs to access port states on startup */
516	xhci_rh_start(&hc->rh);
517
518	return EOK;
519	}
520
521	static void hc_stop(xhci_hc_t *hc)
522	{
523	/* Stop the HC in hardware. */
524	XHCI_REG_CLR(hc->op_regs, XHCI_OP_RS, 1);
525
526	/*
527	* Wait until the HC is halted - it shall take at most 16 ms.
528	* Note that we ignore the return value here.
529	*/
530	xhci_reg_wait(&hc->op_regs->usbsts, XHCI_REG_MASK(XHCI_OP_HCH),
531	XHCI_REG_MASK(XHCI_OP_HCH));
532
533	/* Make sure commands will not block other fibrils. */
534	xhci_nuke_command_ring(hc);
535
536	/* Stop the event worker fibril to restart it */
537	xhci_sw_ring_stop(&hc->sw_ring);
538	joinable_fibril_join(hc->event_worker);
539
540	/* Then, disconnect all roothub devices, which shall trigger
541	* disconnection of everything */
542	xhci_rh_stop(&hc->rh);
543	}
544
545	static void hc_reinitialize(xhci_hc_t *hc)
546	{
547	/* Stop everything. */
548	hc_stop(hc);
549
550	usb_log_info("HC stopped. Starting again...");
551
552	/* The worker fibrils need to be started again */
553	joinable_fibril_recreate(hc->event_worker);
554	joinable_fibril_recreate(hc->rh.event_worker);
555
556	/* Now, the HC shall be stopped and software shall be clean. */
557	hc_start(hc);
558	}
559
560	static bool hc_is_broken(xhci_hc_t *hc)
561	{
562	const uint32_t usbcmd = XHCI_REG_RD_FIELD(&hc->op_regs->usbcmd, 32);
563	const uint32_t usbsts = XHCI_REG_RD_FIELD(&hc->op_regs->usbsts, 32);
564
565	return !(usbcmd & XHCI_REG_MASK(XHCI_OP_RS))
566	\|\| (usbsts & XHCI_REG_MASK(XHCI_OP_HCE))
567	\|\| (usbsts & XHCI_REG_MASK(XHCI_OP_HSE));
568	}
569
570	/**
571	* Used only when polling. Shall supplement the irq_commands.
572	*/
573	int hc_status(bus_t bus, uint32_t status)
574	{
575	xhci_hc_t *hc = bus_to_hc(bus);
576	int ip = XHCI_REG_RD(hc->rt_regs->ir, XHCI_INTR_IP);
577	if (ip) {
578	*status = XHCI_REG_RD(hc->op_regs, XHCI_OP_STATUS);
579	XHCI_REG_WR(hc->op_regs, XHCI_OP_STATUS, *status & XHCI_STATUS_ACK_MASK);
580	XHCI_REG_WR(hc->rt_regs->ir, XHCI_INTR_IP, 1);
581
582	/* interrupt handler expects status from irq_commands, which is
583	* in xhci order. */
584	status = host2xhci(32, status);
585	}
586
587	usb_log_debug("Polled status: %x", *status);
588	return EOK;
589	}
590
591	static int xhci_handle_mfindex_wrap_event(xhci_hc_t hc, xhci_trb_t trb)
592	{
593	struct timeval tv;
594	getuptime(&tv);
595	usb_log_debug("Microframe index wrapped (@%lu.%li, %"PRIu64" total).",
596	tv.tv_sec, tv.tv_usec, hc->wrap_count);
597	hc->wrap_time = ((uint64_t) tv.tv_sec) * 1000000 + ((uint64_t) tv.tv_usec);
598	++hc->wrap_count;
599	return EOK;
600	}
601
602	typedef int (event_handler) (xhci_hc_t , xhci_trb_t *trb);
603
604	/**
605	* These events are handled by separate event handling fibril.
606	*/
607	static event_handler event_handlers [] = {
608	[XHCI_TRB_TYPE_TRANSFER_EVENT] = &xhci_handle_transfer_event,
609	};
610
611	/**
612	* These events are handled directly in the interrupt handler, thus they must
613	* not block waiting for another interrupt.
614	*/
615	static event_handler event_handlers_fast [] = {
616	[XHCI_TRB_TYPE_COMMAND_COMPLETION_EVENT] = &xhci_handle_command_completion,
617	[XHCI_TRB_TYPE_MFINDEX_WRAP_EVENT] = &xhci_handle_mfindex_wrap_event,
618	};
619
620	static int hc_handle_event(xhci_hc_t hc, xhci_trb_t trb)
621	{
622	const unsigned type = TRB_TYPE(*trb);
623
624	if (type <= ARRAY_SIZE(event_handlers_fast) && event_handlers_fast[type])
625	return event_handlers_fast[type](hc, trb);
626
627	if (type <= ARRAY_SIZE(event_handlers) && event_handlers[type])
628	return xhci_sw_ring_enqueue(&hc->sw_ring, trb);
629
630	if (type == XHCI_TRB_TYPE_PORT_STATUS_CHANGE_EVENT)
631	return xhci_sw_ring_enqueue(&hc->rh.event_ring, trb);
632
633	return ENOTSUP;
634	}
635
636	static int event_worker(void *arg)
637	{
638	int err;
639	xhci_trb_t trb;
640	xhci_hc_t * const hc = arg;
641	assert(hc);
642
643	while (xhci_sw_ring_dequeue(&hc->sw_ring, &trb) != EINTR) {
644	const unsigned type = TRB_TYPE(trb);
645
646	if ((err = event_handlers[type](hc, &trb)))
647	usb_log_error("Failed to handle event: %s", str_error(err));
648	}
649
650	return 0;
651	}
652
653	/**
654	* Dequeue from event ring and handle dequeued events.
655	*
656	* As there can be events, that blocks on waiting for subsequent events,
657	* we solve this problem by deferring some types of events to separate fibrils.
658	*/
659	static void hc_run_event_ring(xhci_hc_t hc, xhci_event_ring_t event_ring,
660	xhci_interrupter_regs_t *intr)
661	{
662	int err;
663
664	xhci_trb_t trb;
665	hc->event_handler = fibril_get_id();
666
667	while ((err = xhci_event_ring_dequeue(event_ring, &trb)) != ENOENT) {
668	if ((err = hc_handle_event(hc, &trb)) != EOK) {
669	usb_log_error("Failed to handle event in interrupt: %s", str_error(err));
670	}
671
672	uint64_t erdp = hc->event_ring.dequeue_ptr;
673	XHCI_REG_WR(intr, XHCI_INTR_ERDP_LO, LOWER32(erdp));
674	XHCI_REG_WR(intr, XHCI_INTR_ERDP_HI, UPPER32(erdp));
675	}
676
677	hc->event_handler = 0;
678
679	uint64_t erdp = hc->event_ring.dequeue_ptr;
680	erdp \|= XHCI_REG_MASK(XHCI_INTR_ERDP_EHB);
681	XHCI_REG_WR(intr, XHCI_INTR_ERDP_LO, LOWER32(erdp));
682	XHCI_REG_WR(intr, XHCI_INTR_ERDP_HI, UPPER32(erdp));
683
684	usb_log_debug2("Event ring run finished.");
685	}
686
687	/**
688	* Handle an interrupt request from xHC. Resolve all situations that trigger an
689	* interrupt separately.
690	*
691	* Note that all RW1C bits in USBSTS register are cleared at the time of
692	* handling the interrupt in irq_code. This method is the top-half.
693	*
694	* @param status contents of USBSTS register at the time of the interrupt.
695	*/
696	void hc_interrupt(bus_t *bus, uint32_t status)
697	{
698	xhci_hc_t *hc = bus_to_hc(bus);
699	status = xhci2host(32, status);
700
701	if (status & XHCI_REG_MASK(XHCI_OP_HSE)) {
702	usb_log_error("Host system error occured. Aren't we supposed to be dead already?");
703	return;
704	}
705
706	if (status & XHCI_REG_MASK(XHCI_OP_HCE)) {
707	usb_log_error("Host controller error occured. Reinitializing...");
708	hc_reinitialize(hc);
709	return;
710	}
711
712	if (status & XHCI_REG_MASK(XHCI_OP_EINT)) {
713	usb_log_debug2("Event interrupt, running the event ring.");
714	hc_run_event_ring(hc, &hc->event_ring, &hc->rt_regs->ir[0]);
715	status &= ~XHCI_REG_MASK(XHCI_OP_EINT);
716	}
717
718	if (status & XHCI_REG_MASK(XHCI_OP_SRE)) {
719	usb_log_error("Save/Restore error occured. WTF, "
720	"S/R mechanism not implemented!");
721	status &= ~XHCI_REG_MASK(XHCI_OP_SRE);
722	}
723
724	/* According to Note on p. 302, we may safely ignore the PCD bit. */
725	status &= ~XHCI_REG_MASK(XHCI_OP_PCD);
726
727	if (status) {
728	usb_log_error("Non-zero status after interrupt handling (%08x) "
729	" - missing something?", status);
730	}
731	}
732
733	/**
734	* Tear down all in-memory structures.
735	*/
736	void hc_fini(xhci_hc_t *hc)
737	{
738	hc_stop(hc);
739
740	xhci_sw_ring_fini(&hc->sw_ring);
741	joinable_fibril_destroy(hc->event_worker);
742	xhci_bus_fini(&hc->bus);
743	xhci_event_ring_fini(&hc->event_ring);
744	xhci_scratchpad_free(hc);
745	dma_buffer_free(&hc->dcbaa_dma);
746	xhci_fini_commands(hc);
747	xhci_rh_fini(&hc->rh);
748	pio_disable(hc->reg_base, RNGSZ(hc->mmio_range));
749	usb_log_info("Finalized.");
750	}
751
752	unsigned hc_speed_to_psiv(usb_speed_t speed)
753	{
754	assert(speed < ARRAY_SIZE(usb_speed_to_psiv));
755	return usb_speed_to_psiv[speed];
756	}
757
758	/**
759	* Ring a xHC Doorbell. Implements section 4.7.
760	*/
761	void hc_ring_doorbell(xhci_hc_t *hc, unsigned doorbell, unsigned target)
762	{
763	assert(hc);
764	uint32_t v = host2xhci(32, target & BIT_RRANGE(uint32_t, 7));
765	pio_write_32(&hc->db_arry[doorbell], v);
766	usb_log_debug2("Ringing doorbell %d (target: %d)", doorbell, target);
767	}
768
769	/**
770	* Return an index to device context.
771	*/
772	static uint8_t endpoint_dci(xhci_endpoint_t *ep)
773	{
774	return (2 * ep->base.endpoint) +
775	(ep->base.transfer_type == USB_TRANSFER_CONTROL
776	\|\| ep->base.direction == USB_DIRECTION_IN);
777	}
778
779	void hc_ring_ep_doorbell(xhci_endpoint_t *ep, uint32_t stream_id)
780	{
781	xhci_device_t * const dev = xhci_ep_to_dev(ep);
782	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
783	const uint8_t dci = endpoint_dci(ep);
784	const uint32_t target = (stream_id << 16) \| (dci & 0x1ff);
785	hc_ring_doorbell(hc, dev->slot_id, target);
786	}
787
788	/**
789	* Issue an Enable Slot command. Allocate memory for the slot and fill the
790	* DCBAA with the newly created slot.
791	*/
792	int hc_enable_slot(xhci_device_t *dev)
793	{
794	int err;
795	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
796
797	/* Prepare memory for the context */
798	if ((err = dma_buffer_alloc(&dev->dev_ctx, XHCI_DEVICE_CTX_SIZE(hc))))
799	return err;
800	memset(dev->dev_ctx.virt, 0, XHCI_DEVICE_CTX_SIZE(hc));
801
802	/* Get the slot number */
803	xhci_cmd_t cmd;
804	xhci_cmd_init(&cmd, XHCI_CMD_ENABLE_SLOT);
805
806	err = xhci_cmd_sync(hc, &cmd);
807
808	/* Link them together */
809	if (err == EOK) {
810	dev->slot_id = cmd.slot_id;
811	hc->dcbaa[dev->slot_id] = host2xhci(64, dev->dev_ctx.phys);
812	}
813
814	xhci_cmd_fini(&cmd);
815
816	if (err)
817	dma_buffer_free(&dev->dev_ctx);
818
819	return err;
820	}
821
822	/**
823	* Issue a Disable Slot command for a slot occupied by device.
824	* Frees the device context.
825	*/
826	int hc_disable_slot(xhci_device_t *dev)
827	{
828	int err;
829	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
830
831	if ((err = xhci_cmd_sync_inline(hc, DISABLE_SLOT, .slot_id = dev->slot_id))) {
832	return err;
833	}
834
835	/* Free the device context. */
836	hc->dcbaa[dev->slot_id] = 0;
837	dma_buffer_free(&dev->dev_ctx);
838
839	/* Mark the slot as invalid. */
840	dev->slot_id = 0;
841
842	return EOK;
843	}
844
845	/**
846	* Prepare an empty Endpoint Input Context inside a dma buffer.
847	*/
848	static int create_configure_ep_input_ctx(xhci_device_t dev, dma_buffer_t dma_buf)
849	{
850	const xhci_hc_t * hc = bus_to_hc(dev->base.bus);
851	const int err = dma_buffer_alloc(dma_buf, XHCI_INPUT_CTX_SIZE(hc));
852	if (err)
853	return err;
854
855	xhci_input_ctx_t *ictx = dma_buf->virt;
856	memset(ictx, 0, XHCI_INPUT_CTX_SIZE(hc));
857
858	// Quoting sec. 4.6.5 and 4.6.6: A1, D0, D1 are down (already zeroed), A0 is up.
859	XHCI_INPUT_CTRL_CTX_ADD_SET(*XHCI_GET_CTRL_CTX(ictx, hc), 0);
860	xhci_slot_ctx_t *slot_ctx = XHCI_GET_SLOT_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc);
861	xhci_setup_slot_context(dev, slot_ctx);
862
863	return EOK;
864	}
865
866	/**
867	* Initialize a device, assigning it an address. Implements section 4.3.4.
868	*
869	* @param dev Device to assing an address (unconfigured yet)
870	*/
871	int hc_address_device(xhci_device_t *dev)
872	{
873	int err = ENOMEM;
874	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
875	xhci_endpoint_t *ep0 = xhci_endpoint_get(dev->base.endpoints[0]);
876
877	/* Although we have the precise PSIV value on devices of tier 1,
878	* we have to rely on reverse mapping on others. */
879	if (!usb_speed_to_psiv[dev->base.speed]) {
880	usb_log_error("Device reported an USB speed (%s) that cannot be mapped "
881	"to HC port speed.", usb_str_speed(dev->base.speed));
882	return EINVAL;
883	}
884
885	/* Issue configure endpoint command (sec 4.3.5). */
886	dma_buffer_t ictx_dma_buf;
887	if ((err = create_configure_ep_input_ctx(dev, &ictx_dma_buf)))
888	return err;
889	xhci_input_ctx_t *ictx = ictx_dma_buf.virt;
890
891	/* Copy endpoint 0 context and set A1 flag. */
892	XHCI_INPUT_CTRL_CTX_ADD_SET(*XHCI_GET_CTRL_CTX(ictx, hc), 1);
893	xhci_ep_ctx_t *ep_ctx = XHCI_GET_EP_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc, 1);
894	xhci_setup_endpoint_context(ep0, ep_ctx);
895
896	/* Address device needs Ctx entries set to 1 only */
897	xhci_slot_ctx_t *slot_ctx = XHCI_GET_SLOT_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc);
898	XHCI_SLOT_CTX_ENTRIES_SET(*slot_ctx, 1);
899
900	/* Issue Address Device command. */
901	if ((err = xhci_cmd_sync_inline(hc, ADDRESS_DEVICE,
902	.slot_id = dev->slot_id,
903	.input_ctx = ictx_dma_buf
904	)))
905	return err;
906
907	xhci_device_ctx_t *device_ctx = dev->dev_ctx.virt;
908	dev->base.address = XHCI_SLOT_DEVICE_ADDRESS(*XHCI_GET_SLOT_CTX(device_ctx, hc));
909	usb_log_debug("Obtained USB address: %d.", dev->base.address);
910
911	return EOK;
912	}
913
914	/**
915	* Issue a Configure Device command for a device in slot.
916	*
917	* @param slot_id Slot ID assigned to the device.
918	*/
919	int hc_configure_device(xhci_device_t *dev)
920	{
921	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
922
923	/* Issue configure endpoint command (sec 4.3.5). */
924	dma_buffer_t ictx_dma_buf;
925	const int err = create_configure_ep_input_ctx(dev, &ictx_dma_buf);
926	if (err)
927	return err;
928
929	return xhci_cmd_sync_inline(hc, CONFIGURE_ENDPOINT,
930	.slot_id = dev->slot_id,
931	.input_ctx = ictx_dma_buf
932	);
933	}
934
935	/**
936	* Issue a Deconfigure Device command for a device in slot.
937	*
938	* @param dev The owner of the device
939	*/
940	int hc_deconfigure_device(xhci_device_t *dev)
941	{
942	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
943
944	if (hc_is_broken(hc))
945	return EOK;
946
947	/* Issue configure endpoint command (sec 4.3.5) with the DC flag. */
948	return xhci_cmd_sync_inline(hc, CONFIGURE_ENDPOINT,
949	.slot_id = dev->slot_id,
950	.deconfigure = true
951	);
952	}
953
954	/**
955	* Instruct xHC to add an endpoint with supplied endpoint context.
956	*
957	* @param dev The owner of the device
958	* @param ep_idx Endpoint DCI in question
959	* @param ep_ctx Endpoint context of the endpoint
960	*/
961	int hc_add_endpoint(xhci_endpoint_t *ep)
962	{
963	xhci_device_t * const dev = xhci_ep_to_dev(ep);
964	const unsigned dci = endpoint_dci(ep);
965
966	/* Issue configure endpoint command (sec 4.3.5). */
967	dma_buffer_t ictx_dma_buf;
968	const int err = create_configure_ep_input_ctx(dev, &ictx_dma_buf);
969	if (err)
970	return err;
971
972	xhci_input_ctx_t *ictx = ictx_dma_buf.virt;
973
974	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
975	XHCI_INPUT_CTRL_CTX_ADD_SET(*XHCI_GET_CTRL_CTX(ictx, hc), dci);
976
977	xhci_ep_ctx_t *ep_ctx = XHCI_GET_EP_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc, dci);
978	xhci_setup_endpoint_context(ep, ep_ctx);
979
980	return xhci_cmd_sync_inline(hc, CONFIGURE_ENDPOINT,
981	.slot_id = dev->slot_id,
982	.input_ctx = ictx_dma_buf
983	);
984	}
985
986	/**
987	* Instruct xHC to drop an endpoint.
988	*
989	* @param dev The owner of the endpoint
990	* @param ep_idx Endpoint DCI in question
991	*/
992	int hc_drop_endpoint(xhci_endpoint_t *ep)
993	{
994	xhci_device_t * const dev = xhci_ep_to_dev(ep);
995	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
996	const unsigned dci = endpoint_dci(ep);
997
998	if (hc_is_broken(hc))
999	return EOK;
1000
1001	/* Issue configure endpoint command (sec 4.3.5). */
1002	dma_buffer_t ictx_dma_buf;
1003	const int err = create_configure_ep_input_ctx(dev, &ictx_dma_buf);
1004	if (err)
1005	return err;
1006
1007	xhci_input_ctx_t *ictx = ictx_dma_buf.virt;
1008	XHCI_INPUT_CTRL_CTX_DROP_SET(*XHCI_GET_CTRL_CTX(ictx, hc), dci);
1009
1010	return xhci_cmd_sync_inline(hc, CONFIGURE_ENDPOINT,
1011	.slot_id = dev->slot_id,
1012	.input_ctx = ictx_dma_buf
1013	);
1014	}
1015
1016	/**
1017	* Instruct xHC to update information about an endpoint, using supplied
1018	* endpoint context.
1019	*
1020	* @param dev The owner of the endpoint
1021	* @param ep_idx Endpoint DCI in question
1022	* @param ep_ctx Endpoint context of the endpoint
1023	*/
1024	int hc_update_endpoint(xhci_endpoint_t *ep)
1025	{
1026	xhci_device_t * const dev = xhci_ep_to_dev(ep);
1027	const unsigned dci = endpoint_dci(ep);
1028
1029	dma_buffer_t ictx_dma_buf;
1030	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
1031
1032	const int err = dma_buffer_alloc(&ictx_dma_buf, XHCI_INPUT_CTX_SIZE(hc));
1033	if (err)
1034	return err;
1035
1036	xhci_input_ctx_t *ictx = ictx_dma_buf.virt;
1037	memset(ictx, 0, XHCI_INPUT_CTX_SIZE(hc));
1038
1039	XHCI_INPUT_CTRL_CTX_ADD_SET(*XHCI_GET_CTRL_CTX(ictx, hc), dci);
1040	xhci_ep_ctx_t *ep_ctx = XHCI_GET_EP_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc, dci);
1041	xhci_setup_endpoint_context(ep, ep_ctx);
1042
1043	return xhci_cmd_sync_inline(hc, EVALUATE_CONTEXT,
1044	.slot_id = dev->slot_id,
1045	.input_ctx = ictx_dma_buf
1046	);
1047	}
1048
1049	/**
1050	* Instruct xHC to stop running a transfer ring on an endpoint.
1051	*
1052	* @param dev The owner of the endpoint
1053	* @param ep_idx Endpoint DCI in question
1054	*/
1055	int hc_stop_endpoint(xhci_endpoint_t *ep)
1056	{
1057	xhci_device_t * const dev = xhci_ep_to_dev(ep);
1058	const unsigned dci = endpoint_dci(ep);
1059	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
1060
1061	if (hc_is_broken(hc))
1062	return EOK;
1063
1064	return xhci_cmd_sync_inline(hc, STOP_ENDPOINT,
1065	.slot_id = dev->slot_id,
1066	.endpoint_id = dci
1067	);
1068	}
1069
1070	/**
1071	* Instruct xHC to reset halted endpoint.
1072	*
1073	* @param dev The owner of the endpoint
1074	* @param ep_idx Endpoint DCI in question
1075	*/
1076	int hc_reset_endpoint(xhci_endpoint_t *ep)
1077	{
1078	xhci_device_t * const dev = xhci_ep_to_dev(ep);
1079	const unsigned dci = endpoint_dci(ep);
1080	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
1081	return xhci_cmd_sync_inline(hc, RESET_ENDPOINT,
1082	.slot_id = dev->slot_id,
1083	.endpoint_id = dci
1084	);
1085	}
1086
1087	/**
1088	* Reset a ring position in both software and hardware.
1089	*
1090	* @param dev The owner of the endpoint
1091	*/
1092	int hc_reset_ring(xhci_endpoint_t *ep, uint32_t stream_id)
1093	{
1094	xhci_device_t * const dev = xhci_ep_to_dev(ep);
1095	const unsigned dci = endpoint_dci(ep);
1096	uintptr_t addr;
1097
1098	xhci_trb_ring_t *ring = xhci_endpoint_get_ring(ep, stream_id);
1099	xhci_trb_ring_reset_dequeue_state(ring, &addr);
1100
1101	xhci_hc_t * const hc = bus_to_hc(endpoint_get_bus(&ep->base));
1102	return xhci_cmd_sync_inline(hc, SET_TR_DEQUEUE_POINTER,
1103	.slot_id = dev->slot_id,
1104	.endpoint_id = dci,
1105	.stream_id = stream_id,
1106	.dequeue_ptr = addr,
1107	);
1108	}
1109
1110	/**
1111	* @}
1112	*/

Note: See TracBrowser for help on using the repository browser.

Download in other formats: