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hc.c

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Last change on this file was 8300c72, checked in by Jiri Svoboda <jiri@…>, 4 months ago

Quiesce devices before proceeding with shutdown.

Only implemented for e1k, uhci and xhci.

Property mode set to 100644

File size: 31.1 KB

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1	/*
2	* Copyright (c) 2025 Jiri Svoboda
3	* Copyright (c) 2018 Ondrej Hlavaty, Petr Manek, Jaroslav Jindrak, Jan Hrach, Michal Staruch
4	* All rights reserved.
5	*
6	* Redistribution and use in source and binary forms, with or without
7	* modification, are permitted provided that the following conditions
8	* are met:
9	*
10	* - Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.
12	* - Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.
15	* - The name of the author may not be used to endorse or promote products
16	* derived from this software without specific prior written permission.
17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28	*/
29
30	/** @addtogroup drvusbxhci
31	* @{
32	*/
33	/** @file
34	* @brief The host controller data bookkeeping.
35	*/
36
37	#include <errno.h>
38	#include <str_error.h>
39	#include <usb/debug.h>
40	#include <usb/host/endpoint.h>
41	#include "debug.h"
42	#include "hc.h"
43	#include "rh.h"
44	#include "hw_struct/trb.h"
45	#include "hw_struct/context.h"
46	#include "endpoint.h"
47	#include "transfers.h"
48	#include "trb_ring.h"
49
50	/**
51	* Default USB Speed ID mapping: Table 157
52	*/
53	#define PSI_TO_BPS(psie, psim) (((uint64_t) psim) << (10 * psie))
54	#define PORT_SPEED(usb, mjr, psie, psim) { \
55	.name = "USB ", \
56	.major = mjr, \
57	.minor = 0, \
58	.usb_speed = USB_SPEED_##usb, \
59	.rx_bps = PSI_TO_BPS(psie, psim), \
60	.tx_bps = PSI_TO_BPS(psie, psim) \
61	}
62
63	static const xhci_port_speed_t default_psiv_to_port_speed [] = {
64	[1] = PORT_SPEED(FULL, 2, 2, 12),
65	[2] = PORT_SPEED(LOW, 2, 1, 1500),
66	[3] = PORT_SPEED(HIGH, 2, 2, 480),
67	[4] = PORT_SPEED(SUPER, 3, 3, 5),
68	};
69
70	static const unsigned usb_speed_to_psiv [] = {
71	[USB_SPEED_FULL] = 1,
72	[USB_SPEED_LOW] = 2,
73	[USB_SPEED_HIGH] = 3,
74	[USB_SPEED_SUPER] = 4,
75	};
76
77	/**
78	* Walk the list of extended capabilities.
79	*
80	* The most interesting thing hidden in extended capabilities is the mapping of
81	* ports to protocol versions and speeds.
82	*/
83	static errno_t hc_parse_ec(xhci_hc_t *hc)
84	{
85	unsigned psic, major, minor;
86	xhci_sp_name_t name;
87
88	xhci_port_speed_t *speeds = hc->speeds;
89
90	for (xhci_extcap_t *ec = hc->xecp; ec; ec = xhci_extcap_next(ec)) {
91	xhci_dump_extcap(ec);
92	switch (XHCI_REG_RD(ec, XHCI_EC_CAP_ID)) {
93	case XHCI_EC_USB_LEGACY:
94	assert(hc->legsup == NULL);
95	hc->legsup = (xhci_legsup_t *) ec;
96	break;
97	case XHCI_EC_SUPPORTED_PROTOCOL:
98	psic = XHCI_REG_RD(ec, XHCI_EC_SP_PSIC);
99	major = XHCI_REG_RD(ec, XHCI_EC_SP_MAJOR);
100	minor = XHCI_REG_RD(ec, XHCI_EC_SP_MINOR);
101	name.packed = host2uint32_t_le(XHCI_REG_RD(ec, XHCI_EC_SP_NAME));
102
103	if (name.packed != xhci_name_usb.packed) {
104	/**
105	* The detection of such protocol would work,
106	* but the rest of the implementation is made
107	* for the USB protocol only.
108	*/
109	usb_log_error("Unknown protocol %.4s.", name.str);
110	return ENOTSUP;
111	}
112
113	unsigned offset = XHCI_REG_RD(ec, XHCI_EC_SP_CP_OFF);
114	unsigned count = XHCI_REG_RD(ec, XHCI_EC_SP_CP_COUNT);
115	xhci_rh_set_ports_protocol(&hc->rh, offset, count, major);
116
117	// "Implied" speed
118	if (psic == 0) {
119	assert(minor == 0);
120
121	if (major == 2) {
122	speeds[1] = default_psiv_to_port_speed[1];
123	speeds[2] = default_psiv_to_port_speed[2];
124	speeds[3] = default_psiv_to_port_speed[3];
125	} else if (major == 3) {
126	speeds[4] = default_psiv_to_port_speed[4];
127	} else {
128	return EINVAL;
129	}
130
131	usb_log_debug("Implied speed of USB %u.0 set up.", major);
132	} else {
133	for (unsigned i = 0; i < psic; i++) {
134	xhci_psi_t *psi = xhci_extcap_psi(ec, i);
135	unsigned sim = XHCI_REG_RD(psi, XHCI_PSI_PSIM);
136	unsigned psiv = XHCI_REG_RD(psi, XHCI_PSI_PSIV);
137	unsigned psie = XHCI_REG_RD(psi, XHCI_PSI_PSIE);
138	unsigned psim = XHCI_REG_RD(psi, XHCI_PSI_PSIM);
139	uint64_t bps = PSI_TO_BPS(psie, psim);
140
141	/*
142	* Speed is not implied, but using one of default PSIV. This
143	* is not clearly stated in xHCI spec. There is a clear
144	* intention to allow xHCI to specify its own speed
145	* parameters, but throughout the document, they used fixed
146	* values for e.g. High-speed (3), without stating the
147	* controller shall have implied default speeds - and for
148	* instance Intel controllers do not. So let's check if the
149	* values match and if so, accept the implied USB speed too.
150	*
151	* The main reason we need this is the usb_speed to have
152	* mapping also for devices connected to hubs.
153	*/
154	if (psiv < ARRAY_SIZE(default_psiv_to_port_speed) &&
155	default_psiv_to_port_speed[psiv].major == major &&
156	default_psiv_to_port_speed[psiv].minor == minor &&
157	default_psiv_to_port_speed[psiv].rx_bps == bps &&
158	default_psiv_to_port_speed[psiv].tx_bps == bps) {
159	speeds[psiv] = default_psiv_to_port_speed[psiv];
160	usb_log_debug("Assumed default %s speed of USB %u.",
161	usb_str_speed(speeds[psiv].usb_speed), major);
162	continue;
163	}
164
165	// Custom speed
166	speeds[psiv].major = major;
167	speeds[psiv].minor = minor;
168	str_ncpy(speeds[psiv].name, 4, name.str, 4);
169	speeds[psiv].usb_speed = USB_SPEED_MAX;
170
171	if (sim == XHCI_PSI_PLT_SYMM \|\| sim == XHCI_PSI_PLT_RX)
172	speeds[psiv].rx_bps = bps;
173	if (sim == XHCI_PSI_PLT_SYMM \|\| sim == XHCI_PSI_PLT_TX) {
174	speeds[psiv].tx_bps = bps;
175	usb_log_debug("Speed %u set up for bps %" PRIu64
176	" / %" PRIu64 ".", psiv, speeds[psiv].rx_bps,
177	speeds[psiv].tx_bps);
178	}
179	}
180	}
181	}
182	}
183	return EOK;
184	}
185
186	/**
187	* Initialize MMIO spaces of xHC.
188	*/
189	errno_t hc_init_mmio(xhci_hc_t hc, const hw_res_list_parsed_t hw_res)
190	{
191	errno_t err;
192
193	if (hw_res->mem_ranges.count != 1) {
194	usb_log_error("Unexpected MMIO area, bailing out.");
195	return EINVAL;
196	}
197
198	hc->mmio_range = hw_res->mem_ranges.ranges[0];
199
200	usb_log_debug("MMIO area at %p (size %zu), IRQ %d.",
201	RNGABSPTR(hc->mmio_range), RNGSZ(hc->mmio_range), hw_res->irqs.irqs[0]);
202
203	if (RNGSZ(hc->mmio_range) < sizeof(xhci_cap_regs_t))
204	return EOVERFLOW;
205
206	void *base;
207	if ((err = pio_enable_range(&hc->mmio_range, &base)))
208	return err;
209
210	hc->reg_base = base;
211	hc->cap_regs = (xhci_cap_regs_t *) base;
212	hc->op_regs = (xhci_op_regs_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_LENGTH));
213	hc->rt_regs = (xhci_rt_regs_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF));
214	hc->db_arry = (xhci_doorbell_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_DBOFF));
215
216	uintptr_t xec_offset = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_XECP) * sizeof(xhci_dword_t);
217	if (xec_offset > 0)
218	hc->xecp = (xhci_extcap_t *) (base + xec_offset);
219
220	usb_log_debug("Initialized MMIO reg areas:");
221	usb_log_debug("\tCapability regs: %p", hc->cap_regs);
222	usb_log_debug("\tOperational regs: %p", hc->op_regs);
223	usb_log_debug("\tRuntime regs: %p", hc->rt_regs);
224	usb_log_debug("\tDoorbell array base: %p", hc->db_arry);
225
226	xhci_dump_cap_regs(hc->cap_regs);
227
228	hc->ac64 = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_AC64);
229	hc->csz = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_CSZ);
230	hc->max_slots = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_MAX_SLOTS);
231
232	struct timespec ts;
233	getuptime(&ts);
234	hc->wrap_time = SEC2USEC(ts.tv_sec) + NSEC2USEC(ts.tv_nsec);
235	hc->wrap_count = 0;
236
237	unsigned ist = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_IST);
238	hc->ist = (ist & 0x10 >> 1) * (ist & 0xf);
239
240	if ((err = xhci_rh_init(&hc->rh, hc)))
241	goto err_pio;
242
243	if ((err = hc_parse_ec(hc)))
244	goto err_rh;
245
246	return EOK;
247
248	err_rh:
249	xhci_rh_fini(&hc->rh);
250	err_pio:
251	pio_disable(hc->reg_base, RNGSZ(hc->mmio_range));
252	return err;
253	}
254
255	static int event_worker(void *arg);
256
257	/**
258	* Initialize structures kept in allocated memory.
259	*/
260	errno_t hc_init_memory(xhci_hc_t hc, ddf_dev_t device)
261	{
262	errno_t err = ENOMEM;
263
264	if (dma_buffer_alloc(&hc->dcbaa_dma, (1 + hc->max_slots) * sizeof(uint64_t)))
265	return ENOMEM;
266	hc->dcbaa = hc->dcbaa_dma.virt;
267
268	hc->event_worker = joinable_fibril_create(&event_worker, hc);
269	if (!hc->event_worker)
270	goto err_dcbaa;
271
272	if ((err = xhci_event_ring_init(&hc->event_ring, 1)))
273	goto err_worker;
274
275	if ((err = xhci_scratchpad_alloc(hc)))
276	goto err_event_ring;
277
278	if ((err = xhci_init_commands(hc)))
279	goto err_scratch;
280
281	if ((err = xhci_bus_init(&hc->bus, hc)))
282	goto err_cmd;
283
284	xhci_sw_ring_init(&hc->sw_ring, PAGE_SIZE / sizeof(xhci_trb_t));
285
286	return EOK;
287
288	err_cmd:
289	xhci_fini_commands(hc);
290	err_scratch:
291	xhci_scratchpad_free(hc);
292	err_event_ring:
293	xhci_event_ring_fini(&hc->event_ring);
294	err_worker:
295	joinable_fibril_destroy(hc->event_worker);
296	err_dcbaa:
297	hc->dcbaa = NULL;
298	dma_buffer_free(&hc->dcbaa_dma);
299	return err;
300	}
301
302	/*
303	* Pseudocode:
304	* ip = read(intr[0].iman)
305	* if (ip) {
306	* status = read(usbsts)
307	* assert status
308	* assert ip
309	* accept (passing status)
310	* }
311	* decline
312	*/
313	static const irq_cmd_t irq_commands[] = {
314	{
315	.cmd = CMD_PIO_READ_32,
316	.dstarg = 3,
317	.addr = NULL /* intr[0].iman */
318	},
319	{
320	.cmd = CMD_AND,
321	.srcarg = 3,
322	.dstarg = 4,
323	.value = 0 /* host2xhci(32, 1) */
324	},
325	{
326	.cmd = CMD_PREDICATE,
327	.srcarg = 4,
328	.value = 5
329	},
330	{
331	.cmd = CMD_PIO_READ_32,
332	.dstarg = 1,
333	.addr = NULL /* usbsts */
334	},
335	{
336	.cmd = CMD_AND,
337	.srcarg = 1,
338	.dstarg = 2,
339	.value = 0 /* host2xhci(32, XHCI_STATUS_ACK_MASK) */
340	},
341	{
342	.cmd = CMD_PIO_WRITE_A_32,
343	.srcarg = 2,
344	.addr = NULL /* usbsts */
345	},
346	{
347	.cmd = CMD_PIO_WRITE_A_32,
348	.srcarg = 3,
349	.addr = NULL /* intr[0].iman */
350	},
351	{
352	.cmd = CMD_ACCEPT
353	},
354	{
355	.cmd = CMD_DECLINE
356	}
357	};
358
359	/**
360	* Generates code to accept interrupts. The xHCI is designed primarily for
361	* MSI/MSI-X, but we use PCI Interrupt Pin. In this mode, all the Interrupters
362	* (except 0) are disabled.
363	*/
364	errno_t hc_irq_code_gen(irq_code_t code, xhci_hc_t hc, const hw_res_list_parsed_t hw_res, int irq)
365	{
366	assert(code);
367	assert(hw_res);
368
369	if (hw_res->irqs.count != 1) {
370	usb_log_info("Unexpected HW resources to enable interrupts.");
371	return EINVAL;
372	}
373
374	code->ranges = malloc(sizeof(irq_pio_range_t));
375	if (code->ranges == NULL)
376	return ENOMEM;
377
378	code->cmds = malloc(sizeof(irq_commands));
379	if (code->cmds == NULL) {
380	free(code->ranges);
381	return ENOMEM;
382	}
383
384	code->rangecount = 1;
385	code->ranges[0] = (irq_pio_range_t) {
386	.base = RNGABS(hc->mmio_range),
387	.size = RNGSZ(hc->mmio_range),
388	};
389
390	code->cmdcount = ARRAY_SIZE(irq_commands);
391	memcpy(code->cmds, irq_commands, sizeof(irq_commands));
392
393	void *intr0_iman = RNGABSPTR(hc->mmio_range) +
394	XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF) +
395	offsetof(xhci_rt_regs_t, ir[0]);
396	void *usbsts = RNGABSPTR(hc->mmio_range) +
397	XHCI_REG_RD(hc->cap_regs, XHCI_CAP_LENGTH) +
398	offsetof(xhci_op_regs_t, usbsts);
399
400	code->cmds[0].addr = intr0_iman;
401	code->cmds[1].value = host2xhci(32, 1);
402	code->cmds[3].addr = usbsts;
403	code->cmds[4].value = host2xhci(32, XHCI_STATUS_ACK_MASK);
404	code->cmds[5].addr = usbsts;
405	code->cmds[6].addr = intr0_iman;
406
407	*irq = hw_res->irqs.irqs[0];
408	return EOK;
409	}
410
411	/**
412	* Claim xHC from BIOS. Implements handoff as per Section 4.22.1 of xHCI spec.
413	*/
414	errno_t hc_claim(xhci_hc_t hc, ddf_dev_t dev)
415	{
416	/* No legacy support capability, the controller is solely for us */
417	if (!hc->legsup)
418	return EOK;
419
420	if (xhci_reg_wait(&hc->op_regs->usbsts, XHCI_REG_MASK(XHCI_OP_CNR), 0))
421	return ETIMEOUT;
422
423	usb_log_debug("LEGSUP: bios: %x, os: %x", hc->legsup->sem_bios, hc->legsup->sem_os);
424	XHCI_REG_SET(hc->legsup, XHCI_LEGSUP_SEM_OS, 1);
425	for (int i = 0; i <= (XHCI_LEGSUP_BIOS_TIMEOUT_US / XHCI_LEGSUP_POLLING_DELAY_1MS); i++) {
426	usb_log_debug("LEGSUP: elapsed: %i ms, bios: %x, os: %x", i,
427	XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_BIOS),
428	XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_OS));
429	if (XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_BIOS) == 0) {
430	return XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_OS) == 1 ? EOK : EIO;
431	}
432	fibril_usleep(XHCI_LEGSUP_POLLING_DELAY_1MS);
433	}
434	usb_log_error("BIOS did not release XHCI legacy hold!");
435
436	return ENOTSUP;
437	}
438
439	/**
440	* Ask the xHC to reset its state. Implements sequence
441	*/
442	static errno_t hc_reset(xhci_hc_t *hc)
443	{
444	if (xhci_reg_wait(&hc->op_regs->usbsts, XHCI_REG_MASK(XHCI_OP_CNR), 0))
445	return ETIMEOUT;
446
447	/* Stop the HC: set R/S to 0 */
448	XHCI_REG_CLR(hc->op_regs, XHCI_OP_RS, 1);
449
450	/* Wait until the HC is halted - it shall take at most 16 ms */
451	if (xhci_reg_wait(&hc->op_regs->usbsts, XHCI_REG_MASK(XHCI_OP_HCH),
452	XHCI_REG_MASK(XHCI_OP_HCH)))
453	return ETIMEOUT;
454
455	/* Reset */
456	XHCI_REG_SET(hc->op_regs, XHCI_OP_HCRST, 1);
457
458	/* Wait until the reset is complete */
459	if (xhci_reg_wait(&hc->op_regs->usbcmd, XHCI_REG_MASK(XHCI_OP_HCRST), 0))
460	return ETIMEOUT;
461
462	return EOK;
463	}
464
465	/**
466	* Initialize the HC: section 4.2
467	*/
468	errno_t hc_start(xhci_hc_t *hc)
469	{
470	errno_t err;
471
472	if ((err = hc_reset(hc)))
473	return err;
474
475	if (xhci_reg_wait(&hc->op_regs->usbsts, XHCI_REG_MASK(XHCI_OP_CNR), 0))
476	return ETIMEOUT;
477
478	uintptr_t dcbaa_phys = dma_buffer_phys_base(&hc->dcbaa_dma);
479	XHCI_REG_WR(hc->op_regs, XHCI_OP_DCBAAP, dcbaa_phys);
480	XHCI_REG_WR(hc->op_regs, XHCI_OP_MAX_SLOTS_EN, hc->max_slots);
481
482	uintptr_t crcr;
483	xhci_trb_ring_reset_dequeue_state(&hc->cr.trb_ring, &crcr);
484	XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR, crcr);
485
486	XHCI_REG_SET(hc->op_regs, XHCI_OP_EWE, 1);
487
488	xhci_event_ring_reset(&hc->event_ring);
489
490	xhci_interrupter_regs_t *intr0 = &hc->rt_regs->ir[0];
491	XHCI_REG_WR(intr0, XHCI_INTR_ERSTSZ, hc->event_ring.segment_count);
492	XHCI_REG_WR(intr0, XHCI_INTR_ERDP, hc->event_ring.dequeue_ptr);
493
494	const uintptr_t erstba_phys = dma_buffer_phys_base(&hc->event_ring.erst);
495	XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA, erstba_phys);
496
497	if (cap_handle_valid(hc->base.irq_handle)) {
498	XHCI_REG_SET(intr0, XHCI_INTR_IE, 1);
499	XHCI_REG_SET(hc->op_regs, XHCI_OP_INTE, 1);
500	}
501
502	XHCI_REG_SET(hc->op_regs, XHCI_OP_HSEE, 1);
503
504	xhci_sw_ring_restart(&hc->sw_ring);
505	joinable_fibril_start(hc->event_worker);
506
507	xhci_start_command_ring(hc);
508
509	XHCI_REG_SET(hc->op_regs, XHCI_OP_RS, 1);
510
511	/* RH needs to access port states on startup */
512	xhci_rh_start(&hc->rh);
513
514	return EOK;
515	}
516
517	static void hc_stop(xhci_hc_t *hc)
518	{
519	/* Stop the HC in hardware. */
520	XHCI_REG_CLR(hc->op_regs, XHCI_OP_RS, 1);
521
522	/*
523	* Wait until the HC is halted - it shall take at most 16 ms.
524	* Note that we ignore the return value here.
525	*/
526	xhci_reg_wait(&hc->op_regs->usbsts, XHCI_REG_MASK(XHCI_OP_HCH),
527	XHCI_REG_MASK(XHCI_OP_HCH));
528
529	/* Make sure commands will not block other fibrils. */
530	xhci_nuke_command_ring(hc);
531
532	/* Stop the event worker fibril to restart it */
533	xhci_sw_ring_stop(&hc->sw_ring);
534	joinable_fibril_join(hc->event_worker);
535
536	/*
537	* Then, disconnect all roothub devices, which shall trigger
538	* disconnection of everything
539	*/
540	xhci_rh_stop(&hc->rh);
541	}
542
543	static void hc_reinitialize(xhci_hc_t *hc)
544	{
545	/* Stop everything. */
546	hc_stop(hc);
547
548	usb_log_info("HC stopped. Starting again...");
549
550	/* The worker fibrils need to be started again */
551	joinable_fibril_recreate(hc->event_worker);
552	joinable_fibril_recreate(hc->rh.event_worker);
553
554	/* Now, the HC shall be stopped and software shall be clean. */
555	hc_start(hc);
556	}
557
558	static bool hc_is_broken(xhci_hc_t *hc)
559	{
560	const uint32_t usbcmd = XHCI_REG_RD_FIELD(&hc->op_regs->usbcmd, 32);
561	const uint32_t usbsts = XHCI_REG_RD_FIELD(&hc->op_regs->usbsts, 32);
562
563	return !(usbcmd & XHCI_REG_MASK(XHCI_OP_RS)) \|\|
564	(usbsts & XHCI_REG_MASK(XHCI_OP_HCE)) \|\|
565	(usbsts & XHCI_REG_MASK(XHCI_OP_HSE));
566	}
567
568	/**
569	* Used only when polling. Shall supplement the irq_commands.
570	*/
571	errno_t hc_status(bus_t bus, uint32_t status)
572	{
573	xhci_hc_t *hc = bus_to_hc(bus);
574	int ip = XHCI_REG_RD(hc->rt_regs->ir, XHCI_INTR_IP);
575	if (ip) {
576	*status = XHCI_REG_RD(hc->op_regs, XHCI_OP_STATUS);
577	XHCI_REG_WR(hc->op_regs, XHCI_OP_STATUS, *status & XHCI_STATUS_ACK_MASK);
578	XHCI_REG_WR(hc->rt_regs->ir, XHCI_INTR_IP, 1);
579
580	/*
581	* interrupt handler expects status from irq_commands, which is
582	* in xhci order.
583	*/
584	status = host2xhci(32, status);
585	}
586
587	usb_log_debug("Polled status: %x", *status);
588	return EOK;
589	}
590
591	static errno_t xhci_handle_mfindex_wrap_event(xhci_hc_t hc, xhci_trb_t trb)
592	{
593	struct timespec ts;
594	getuptime(&ts);
595	usb_log_debug("Microframe index wrapped (@%lld.%lld, %" PRIu64 " total).",
596	ts.tv_sec, NSEC2USEC(ts.tv_nsec), hc->wrap_count);
597	hc->wrap_time = SEC2USEC(ts.tv_sec) + NSEC2USEC(ts.tv_nsec);
598	++hc->wrap_count;
599	return EOK;
600	}
601
602	typedef errno_t (event_handler) (xhci_hc_t , xhci_trb_t *trb);
603
604	/**
605	* These events are handled by separate event handling fibril.
606	*/
607	static event_handler event_handlers [] = {
608	[XHCI_TRB_TYPE_TRANSFER_EVENT] = &xhci_handle_transfer_event,
609	};
610
611	/**
612	* These events are handled directly in the interrupt handler, thus they must
613	* not block waiting for another interrupt.
614	*/
615	static event_handler event_handlers_fast [] = {
616	[XHCI_TRB_TYPE_COMMAND_COMPLETION_EVENT] = &xhci_handle_command_completion,
617	[XHCI_TRB_TYPE_MFINDEX_WRAP_EVENT] = &xhci_handle_mfindex_wrap_event,
618	};
619
620	static errno_t hc_handle_event(xhci_hc_t hc, xhci_trb_t trb)
621	{
622	const unsigned type = TRB_TYPE(*trb);
623
624	if (type <= ARRAY_SIZE(event_handlers_fast) && event_handlers_fast[type])
625	return event_handlers_fast[type](hc, trb);
626
627	if (type <= ARRAY_SIZE(event_handlers) && event_handlers[type])
628	return xhci_sw_ring_enqueue(&hc->sw_ring, trb);
629
630	if (type == XHCI_TRB_TYPE_PORT_STATUS_CHANGE_EVENT)
631	return xhci_sw_ring_enqueue(&hc->rh.event_ring, trb);
632
633	return ENOTSUP;
634	}
635
636	static int event_worker(void *arg)
637	{
638	errno_t err;
639	xhci_trb_t trb;
640	xhci_hc_t *const hc = arg;
641	assert(hc);
642
643	while (xhci_sw_ring_dequeue(&hc->sw_ring, &trb) != EINTR) {
644	const unsigned type = TRB_TYPE(trb);
645
646	if ((err = event_handlers[type](hc, &trb)))
647	usb_log_error("Failed to handle event: %s", str_error(err));
648	}
649
650	return 0;
651	}
652
653	/**
654	* Dequeue from event ring and handle dequeued events.
655	*
656	* As there can be events, that blocks on waiting for subsequent events,
657	* we solve this problem by deferring some types of events to separate fibrils.
658	*/
659	static void hc_run_event_ring(xhci_hc_t hc, xhci_event_ring_t event_ring,
660	xhci_interrupter_regs_t *intr)
661	{
662	errno_t err;
663
664	xhci_trb_t trb;
665	hc->event_handler = fibril_get_id();
666
667	while ((err = xhci_event_ring_dequeue(event_ring, &trb)) != ENOENT) {
668	if ((err = hc_handle_event(hc, &trb)) != EOK) {
669	usb_log_error("Failed to handle event in interrupt: %s", str_error(err));
670	}
671
672	XHCI_REG_WR(intr, XHCI_INTR_ERDP, hc->event_ring.dequeue_ptr);
673	}
674
675	hc->event_handler = 0;
676
677	uint64_t erdp = hc->event_ring.dequeue_ptr;
678	erdp \|= XHCI_REG_MASK(XHCI_INTR_ERDP_EHB);
679	XHCI_REG_WR(intr, XHCI_INTR_ERDP, erdp);
680
681	usb_log_debug2("Event ring run finished.");
682	}
683
684	/**
685	* Handle an interrupt request from xHC. Resolve all situations that trigger an
686	* interrupt separately.
687	*
688	* Note that all RW1C bits in USBSTS register are cleared at the time of
689	* handling the interrupt in irq_code. This method is the top-half.
690	*
691	* @param status contents of USBSTS register at the time of the interrupt.
692	*/
693	void hc_interrupt(bus_t *bus, uint32_t status)
694	{
695	xhci_hc_t *hc = bus_to_hc(bus);
696	status = xhci2host(32, status);
697
698	if (status & XHCI_REG_MASK(XHCI_OP_HSE)) {
699	usb_log_error("Host system error occured. Aren't we supposed to be dead already?");
700	return;
701	}
702
703	if (status & XHCI_REG_MASK(XHCI_OP_HCE)) {
704	usb_log_error("Host controller error occured. Reinitializing...");
705	hc_reinitialize(hc);
706	return;
707	}
708
709	if (status & XHCI_REG_MASK(XHCI_OP_EINT)) {
710	usb_log_debug2("Event interrupt, running the event ring.");
711	hc_run_event_ring(hc, &hc->event_ring, &hc->rt_regs->ir[0]);
712	status &= ~XHCI_REG_MASK(XHCI_OP_EINT);
713	}
714
715	if (status & XHCI_REG_MASK(XHCI_OP_SRE)) {
716	usb_log_error("Save/Restore error occured. WTF, "
717	"S/R mechanism not implemented!");
718	status &= ~XHCI_REG_MASK(XHCI_OP_SRE);
719	}
720
721	/* According to Note on p. 302, we may safely ignore the PCD bit. */
722	status &= ~XHCI_REG_MASK(XHCI_OP_PCD);
723
724	if (status) {
725	usb_log_error("Non-zero status after interrupt handling (%08x) "
726	" - missing something?", status);
727	}
728	}
729
730	/**
731	* Tear down all in-memory structures.
732	*/
733	void hc_fini(xhci_hc_t *hc)
734	{
735	hc_stop(hc);
736
737	xhci_sw_ring_fini(&hc->sw_ring);
738	joinable_fibril_destroy(hc->event_worker);
739	xhci_bus_fini(&hc->bus);
740	xhci_event_ring_fini(&hc->event_ring);
741	xhci_scratchpad_free(hc);
742	dma_buffer_free(&hc->dcbaa_dma);
743	xhci_fini_commands(hc);
744	xhci_rh_fini(&hc->rh);
745	pio_disable(hc->reg_base, RNGSZ(hc->mmio_range));
746	usb_log_info("Finalized.");
747	}
748
749	/**
750	* Quiesce host controller.
751	*/
752	errno_t hc_quiesce(xhci_hc_t *hc)
753	{
754	hc_stop(hc);
755	usb_log_info("HC quiesced.");
756	return EOK;
757	}
758
759	unsigned hc_speed_to_psiv(usb_speed_t speed)
760	{
761	assert(speed < ARRAY_SIZE(usb_speed_to_psiv));
762	return usb_speed_to_psiv[speed];
763	}
764
765	/**
766	* Ring a xHC Doorbell. Implements section 4.7.
767	*/
768	void hc_ring_doorbell(xhci_hc_t *hc, unsigned doorbell, unsigned target)
769	{
770	assert(hc);
771	uint32_t v = host2xhci(32, target & BIT_RRANGE(uint32_t, 7));
772	pio_write_32(&hc->db_arry[doorbell], v);
773	usb_log_debug2("Ringing doorbell %d (target: %d)", doorbell, target);
774	}
775
776	/**
777	* Return an index to device context.
778	*/
779	static uint8_t endpoint_dci(xhci_endpoint_t *ep)
780	{
781	return (2 * ep->base.endpoint) +
782	(ep->base.transfer_type == USB_TRANSFER_CONTROL \|\|
783	ep->base.direction == USB_DIRECTION_IN);
784	}
785
786	void hc_ring_ep_doorbell(xhci_endpoint_t *ep, uint32_t stream_id)
787	{
788	xhci_device_t *const dev = xhci_ep_to_dev(ep);
789	xhci_hc_t *const hc = bus_to_hc(dev->base.bus);
790	const uint8_t dci = endpoint_dci(ep);
791	const uint32_t target = (stream_id << 16) \| (dci & 0x1ff);
792	hc_ring_doorbell(hc, dev->slot_id, target);
793	}
794
795	/**
796	* Issue an Enable Slot command. Allocate memory for the slot and fill the
797	* DCBAA with the newly created slot.
798	*/
799	errno_t hc_enable_slot(xhci_device_t *dev)
800	{
801	errno_t err;
802	xhci_hc_t *const hc = bus_to_hc(dev->base.bus);
803
804	/* Prepare memory for the context */
805	if ((err = dma_buffer_alloc(&dev->dev_ctx, XHCI_DEVICE_CTX_SIZE(hc))))
806	return err;
807	memset(dev->dev_ctx.virt, 0, XHCI_DEVICE_CTX_SIZE(hc));
808
809	/* Get the slot number */
810	xhci_cmd_t cmd;
811	xhci_cmd_init(&cmd, XHCI_CMD_ENABLE_SLOT);
812
813	err = xhci_cmd_sync(hc, &cmd);
814
815	/* Link them together */
816	if (err == EOK) {
817	dev->slot_id = cmd.slot_id;
818	hc->dcbaa[dev->slot_id] =
819	host2xhci(64, dma_buffer_phys_base(&dev->dev_ctx));
820	}
821
822	xhci_cmd_fini(&cmd);
823
824	if (err)
825	dma_buffer_free(&dev->dev_ctx);
826
827	return err;
828	}
829
830	/**
831	* Issue a Disable Slot command for a slot occupied by device.
832	* Frees the device context.
833	*/
834	errno_t hc_disable_slot(xhci_device_t *dev)
835	{
836	errno_t err;
837	xhci_hc_t *const hc = bus_to_hc(dev->base.bus);
838	xhci_cmd_t cmd;
839
840	xhci_cmd_init(&cmd, XHCI_CMD_DISABLE_SLOT);
841	cmd.slot_id = dev->slot_id;
842	err = xhci_cmd_sync(hc, &cmd);
843	xhci_cmd_fini(&cmd);
844	if (err != EOK)
845	return err;
846
847	/* Free the device context. */
848	hc->dcbaa[dev->slot_id] = 0;
849	dma_buffer_free(&dev->dev_ctx);
850
851	/* Mark the slot as invalid. */
852	dev->slot_id = 0;
853
854	return EOK;
855	}
856
857	/**
858	* Prepare an empty Endpoint Input Context inside a dma buffer.
859	*/
860	static errno_t create_configure_ep_input_ctx(xhci_device_t dev, dma_buffer_t dma_buf)
861	{
862	const xhci_hc_t *hc = bus_to_hc(dev->base.bus);
863	const errno_t err = dma_buffer_alloc(dma_buf, XHCI_INPUT_CTX_SIZE(hc));
864	if (err)
865	return err;
866
867	xhci_input_ctx_t *ictx = dma_buf->virt;
868	memset(ictx, 0, XHCI_INPUT_CTX_SIZE(hc));
869
870	// Quoting sec. 4.6.5 and 4.6.6: A1, D0, D1 are down (already zeroed), A0 is up.
871	XHCI_INPUT_CTRL_CTX_ADD_SET(*XHCI_GET_CTRL_CTX(ictx, hc), 0);
872	xhci_slot_ctx_t *slot_ctx = XHCI_GET_SLOT_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc);
873	xhci_setup_slot_context(dev, slot_ctx);
874
875	return EOK;
876	}
877
878	/**
879	* Initialize a device, assigning it an address. Implements section 4.3.4.
880	*
881	* @param dev Device to assing an address (unconfigured yet)
882	*/
883	errno_t hc_address_device(xhci_device_t *dev)
884	{
885	errno_t err = ENOMEM;
886	xhci_hc_t *const hc = bus_to_hc(dev->base.bus);
887	xhci_endpoint_t *ep0 = xhci_endpoint_get(dev->base.endpoints[0]);
888
889	/*
890	* Although we have the precise PSIV value on devices of tier 1,
891	* we have to rely on reverse mapping on others.
892	*/
893	if (!usb_speed_to_psiv[dev->base.speed]) {
894	usb_log_error("Device reported an USB speed (%s) that cannot be mapped "
895	"to HC port speed.", usb_str_speed(dev->base.speed));
896	return EINVAL;
897	}
898
899	/* Issue configure endpoint command (sec 4.3.5). */
900	dma_buffer_t ictx_dma_buf;
901	if ((err = create_configure_ep_input_ctx(dev, &ictx_dma_buf)))
902	return err;
903	xhci_input_ctx_t *ictx = ictx_dma_buf.virt;
904
905	/* Copy endpoint 0 context and set A1 flag. */
906	XHCI_INPUT_CTRL_CTX_ADD_SET(*XHCI_GET_CTRL_CTX(ictx, hc), 1);
907	xhci_ep_ctx_t *ep_ctx = XHCI_GET_EP_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc, 1);
908	xhci_setup_endpoint_context(ep0, ep_ctx);
909
910	/* Address device needs Ctx entries set to 1 only */
911	xhci_slot_ctx_t *slot_ctx = XHCI_GET_SLOT_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc);
912	XHCI_SLOT_CTX_ENTRIES_SET(*slot_ctx, 1);
913
914	/* Issue Address Device command. */
915	xhci_cmd_t cmd;
916	xhci_cmd_init(&cmd, XHCI_CMD_ADDRESS_DEVICE);
917	cmd.slot_id = dev->slot_id;
918	cmd.input_ctx = ictx_dma_buf;
919	err = xhci_cmd_sync(hc, &cmd);
920	xhci_cmd_fini(&cmd);
921	if (err != EOK)
922	return err;
923
924	xhci_device_ctx_t *device_ctx = dev->dev_ctx.virt;
925	dev->base.address = XHCI_SLOT_DEVICE_ADDRESS(*XHCI_GET_SLOT_CTX(device_ctx, hc));
926	usb_log_debug("Obtained USB address: %d.", dev->base.address);
927
928	return EOK;
929	}
930
931	/**
932	* Issue a Configure Device command for a device in slot.
933	*
934	* @param slot_id Slot ID assigned to the device.
935	*/
936	errno_t hc_configure_device(xhci_device_t *dev)
937	{
938	xhci_hc_t *const hc = bus_to_hc(dev->base.bus);
939	xhci_cmd_t cmd;
940
941	/* Issue configure endpoint command (sec 4.3.5). */
942	dma_buffer_t ictx_dma_buf;
943	errno_t err = create_configure_ep_input_ctx(dev, &ictx_dma_buf);
944	if (err != EOK)
945	return err;
946
947	xhci_cmd_init(&cmd, XHCI_CMD_CONFIGURE_ENDPOINT);
948	cmd.slot_id = dev->slot_id;
949	cmd.input_ctx = ictx_dma_buf;
950	err = xhci_cmd_sync(hc, &cmd);
951	xhci_cmd_fini(&cmd);
952
953	return err;
954	}
955
956	/**
957	* Issue a Deconfigure Device command for a device in slot.
958	*
959	* @param dev The owner of the device
960	*/
961	errno_t hc_deconfigure_device(xhci_device_t *dev)
962	{
963	xhci_hc_t *const hc = bus_to_hc(dev->base.bus);
964	xhci_cmd_t cmd;
965	errno_t err;
966
967	if (hc_is_broken(hc))
968	return EOK;
969
970	/* Issue configure endpoint command (sec 4.3.5) with the DC flag. */
971	xhci_cmd_init(&cmd, XHCI_CMD_CONFIGURE_ENDPOINT);
972	cmd.slot_id = dev->slot_id;
973	cmd.deconfigure = true;
974
975	err = xhci_cmd_sync(hc, &cmd);
976	xhci_cmd_fini(&cmd);
977
978	return err;
979	}
980
981	/**
982	* Instruct xHC to add an endpoint with supplied endpoint context.
983	*
984	* @param dev The owner of the device
985	* @param ep_idx Endpoint DCI in question
986	* @param ep_ctx Endpoint context of the endpoint
987	*/
988	errno_t hc_add_endpoint(xhci_endpoint_t *ep)
989	{
990	xhci_device_t *const dev = xhci_ep_to_dev(ep);
991	const unsigned dci = endpoint_dci(ep);
992	xhci_cmd_t cmd;
993
994	/* Issue configure endpoint command (sec 4.3.5). */
995	dma_buffer_t ictx_dma_buf;
996	errno_t err = create_configure_ep_input_ctx(dev, &ictx_dma_buf);
997	if (err != EOK)
998	return err;
999
1000	xhci_input_ctx_t *ictx = ictx_dma_buf.virt;
1001
1002	xhci_hc_t *const hc = bus_to_hc(dev->base.bus);
1003	XHCI_INPUT_CTRL_CTX_ADD_SET(*XHCI_GET_CTRL_CTX(ictx, hc), dci);
1004
1005	xhci_ep_ctx_t *ep_ctx = XHCI_GET_EP_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc, dci);
1006	xhci_setup_endpoint_context(ep, ep_ctx);
1007
1008	xhci_cmd_init(&cmd, XHCI_CMD_CONFIGURE_ENDPOINT);
1009	cmd.slot_id = dev->slot_id;
1010	cmd.input_ctx = ictx_dma_buf;
1011	err = xhci_cmd_sync(hc, &cmd);
1012	xhci_cmd_fini(&cmd);
1013
1014	return err;
1015	}
1016
1017	/**
1018	* Instruct xHC to drop an endpoint.
1019	*
1020	* @param dev The owner of the endpoint
1021	* @param ep_idx Endpoint DCI in question
1022	*/
1023	errno_t hc_drop_endpoint(xhci_endpoint_t *ep)
1024	{
1025	xhci_device_t *const dev = xhci_ep_to_dev(ep);
1026	xhci_hc_t *const hc = bus_to_hc(dev->base.bus);
1027	const unsigned dci = endpoint_dci(ep);
1028	xhci_cmd_t cmd;
1029
1030	if (hc_is_broken(hc))
1031	return EOK;
1032
1033	/* Issue configure endpoint command (sec 4.3.5). */
1034	dma_buffer_t ictx_dma_buf;
1035	errno_t err = create_configure_ep_input_ctx(dev, &ictx_dma_buf);
1036	if (err != EOK)
1037	return err;
1038
1039	xhci_input_ctx_t *ictx = ictx_dma_buf.virt;
1040	XHCI_INPUT_CTRL_CTX_DROP_SET(*XHCI_GET_CTRL_CTX(ictx, hc), dci);
1041
1042	xhci_cmd_init(&cmd, XHCI_CMD_CONFIGURE_ENDPOINT);
1043	cmd.slot_id = dev->slot_id;
1044	cmd.input_ctx = ictx_dma_buf;
1045	err = xhci_cmd_sync(hc, &cmd);
1046	xhci_cmd_fini(&cmd);
1047
1048	return err;
1049	}
1050
1051	/**
1052	* Instruct xHC to update information about an endpoint, using supplied
1053	* endpoint context.
1054	*
1055	* @param dev The owner of the endpoint
1056	* @param ep_idx Endpoint DCI in question
1057	* @param ep_ctx Endpoint context of the endpoint
1058	*/
1059	errno_t hc_update_endpoint(xhci_endpoint_t *ep)
1060	{
1061	xhci_device_t *const dev = xhci_ep_to_dev(ep);
1062	const unsigned dci = endpoint_dci(ep);
1063	xhci_cmd_t cmd;
1064
1065	dma_buffer_t ictx_dma_buf;
1066	xhci_hc_t *const hc = bus_to_hc(dev->base.bus);
1067
1068	errno_t err = dma_buffer_alloc(&ictx_dma_buf, XHCI_INPUT_CTX_SIZE(hc));
1069	if (err != EOK)
1070	return err;
1071
1072	xhci_input_ctx_t *ictx = ictx_dma_buf.virt;
1073	memset(ictx, 0, XHCI_INPUT_CTX_SIZE(hc));
1074
1075	XHCI_INPUT_CTRL_CTX_ADD_SET(*XHCI_GET_CTRL_CTX(ictx, hc), dci);
1076	xhci_ep_ctx_t *ep_ctx = XHCI_GET_EP_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc, dci);
1077	xhci_setup_endpoint_context(ep, ep_ctx);
1078
1079	xhci_cmd_init(&cmd, XHCI_CMD_EVALUATE_CONTEXT);
1080	cmd.slot_id = dev->slot_id;
1081	cmd.input_ctx = ictx_dma_buf;
1082	err = xhci_cmd_sync(hc, &cmd);
1083	xhci_cmd_fini(&cmd);
1084
1085	return err;
1086	}
1087
1088	/**
1089	* Instruct xHC to stop running a transfer ring on an endpoint.
1090	*
1091	* @param dev The owner of the endpoint
1092	* @param ep_idx Endpoint DCI in question
1093	*/
1094	errno_t hc_stop_endpoint(xhci_endpoint_t *ep)
1095	{
1096	xhci_device_t *const dev = xhci_ep_to_dev(ep);
1097	const unsigned dci = endpoint_dci(ep);
1098	xhci_hc_t *const hc = bus_to_hc(dev->base.bus);
1099	xhci_cmd_t cmd;
1100	errno_t err;
1101
1102	if (hc_is_broken(hc))
1103	return EOK;
1104
1105	xhci_cmd_init(&cmd, XHCI_CMD_STOP_ENDPOINT);
1106	cmd.slot_id = dev->slot_id;
1107	cmd.endpoint_id = dci;
1108	err = xhci_cmd_sync(hc, &cmd);
1109	xhci_cmd_fini(&cmd);
1110
1111	return err;
1112	}
1113
1114	/**
1115	* Instruct xHC to reset halted endpoint.
1116	*
1117	* @param dev The owner of the endpoint
1118	* @param ep_idx Endpoint DCI in question
1119	*/
1120	errno_t hc_reset_endpoint(xhci_endpoint_t *ep)
1121	{
1122	xhci_device_t *const dev = xhci_ep_to_dev(ep);
1123	const unsigned dci = endpoint_dci(ep);
1124	xhci_hc_t *const hc = bus_to_hc(dev->base.bus);
1125	xhci_cmd_t cmd;
1126	errno_t err;
1127
1128	xhci_cmd_init(&cmd, XHCI_CMD_RESET_ENDPOINT);
1129	cmd.slot_id = dev->slot_id;
1130	cmd.endpoint_id = dci;
1131	err = xhci_cmd_sync(hc, &cmd);
1132	xhci_cmd_fini(&cmd);
1133
1134	return err;
1135	}
1136
1137	/**
1138	* Reset a ring position in both software and hardware.
1139	*
1140	* @param dev The owner of the endpoint
1141	*/
1142	errno_t hc_reset_ring(xhci_endpoint_t *ep, uint32_t stream_id)
1143	{
1144	xhci_device_t *const dev = xhci_ep_to_dev(ep);
1145	const unsigned dci = endpoint_dci(ep);
1146	uintptr_t addr;
1147	xhci_cmd_t cmd;
1148	errno_t err;
1149
1150	xhci_trb_ring_t *ring = xhci_endpoint_get_ring(ep, stream_id);
1151	xhci_trb_ring_reset_dequeue_state(ring, &addr);
1152
1153	xhci_hc_t *const hc = bus_to_hc(endpoint_get_bus(&ep->base));
1154
1155	xhci_cmd_init(&cmd, XHCI_CMD_SET_TR_DEQUEUE_POINTER);
1156	cmd.slot_id = dev->slot_id;
1157	cmd.endpoint_id = dci;
1158	cmd.stream_id = stream_id;
1159	cmd.dequeue_ptr = addr;
1160	err = xhci_cmd_sync(hc, &cmd);
1161	xhci_cmd_fini(&cmd);
1162
1163	return err;
1164	}
1165
1166	/**
1167	* @}
1168	*/

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source: mainline/uspace/drv/bus/usb/xhci/hc.c

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