source: mainline/uspace/drv/bus/usb/xhci/hc.c@ 0247bd2

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 0247bd2 was 0247bd2, checked in by Ondřej Hlavatý <aearsis@…>, 8 years ago

xhci: updated obsolete comment
  • Property mode set to 100644
File size: 29.1 KB
Line 
1/*
2 * Copyright (c) 2017 Ondrej Hlavaty
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbxhci
30 * @{
31 */
32/** @file
33 * @brief The host controller data bookkeeping.
34 */
35
36#include <errno.h>
37#include <str_error.h>
38#include <usb/debug.h>
39#include <usb/host/endpoint.h>
40#include "debug.h"
41#include "hc.h"
42#include "rh.h"
43#include "hw_struct/trb.h"
44#include "hw_struct/context.h"
45#include "endpoint.h"
46#include "transfers.h"
47#include "trb_ring.h"
48
49/**
50 * Default USB Speed ID mapping: Table 157
51 */
52#define PSI_TO_BPS(psie, psim) (((uint64_t) psim) << (10 * psie))
53#define PORT_SPEED(usb, mjr, psie, psim) { \
54 .name = "USB ", \
55 .major = mjr, \
56 .minor = 0, \
57 .usb_speed = USB_SPEED_##usb, \
58 .rx_bps = PSI_TO_BPS(psie, psim), \
59 .tx_bps = PSI_TO_BPS(psie, psim) \
60}
61
62static const xhci_port_speed_t default_psiv_to_port_speed [] = {
63 [1] = PORT_SPEED(FULL, 2, 2, 12),
64 [2] = PORT_SPEED(LOW, 2, 1, 1500),
65 [3] = PORT_SPEED(HIGH, 2, 2, 480),
66 [4] = PORT_SPEED(SUPER, 3, 3, 5),
67};
68
69static const unsigned usb_speed_to_psiv [] = {
70 [USB_SPEED_FULL] = 1,
71 [USB_SPEED_LOW] = 2,
72 [USB_SPEED_HIGH] = 3,
73 [USB_SPEED_SUPER] = 4,
74};
75
76/**
77 * Walk the list of extended capabilities.
78 *
79 * The most interesting thing hidden in extended capabilities is the mapping of
80 * ports to protocol versions and speeds.
81 */
82static int hc_parse_ec(xhci_hc_t *hc)
83{
84 unsigned psic, major, minor;
85 xhci_sp_name_t name;
86
87 xhci_port_speed_t *speeds = hc->speeds;
88
89 for (xhci_extcap_t *ec = hc->xecp; ec; ec = xhci_extcap_next(ec)) {
90 xhci_dump_extcap(ec);
91 switch (XHCI_REG_RD(ec, XHCI_EC_CAP_ID)) {
92 case XHCI_EC_USB_LEGACY:
93 assert(hc->legsup == NULL);
94 hc->legsup = (xhci_legsup_t *) ec;
95 break;
96 case XHCI_EC_SUPPORTED_PROTOCOL:
97 psic = XHCI_REG_RD(ec, XHCI_EC_SP_PSIC);
98 major = XHCI_REG_RD(ec, XHCI_EC_SP_MAJOR);
99 minor = XHCI_REG_RD(ec, XHCI_EC_SP_MINOR);
100 name.packed = host2uint32_t_le(XHCI_REG_RD(ec, XHCI_EC_SP_NAME));
101
102 if (name.packed != xhci_name_usb.packed) {
103 /**
104 * The detection of such protocol would work,
105 * but the rest of the implementation is made
106 * for the USB protocol only.
107 */
108 usb_log_error("Unknown protocol %.4s.", name.str);
109 return ENOTSUP;
110 }
111
112 unsigned offset = XHCI_REG_RD(ec, XHCI_EC_SP_CP_OFF);
113 unsigned count = XHCI_REG_RD(ec, XHCI_EC_SP_CP_COUNT);
114 xhci_rh_set_ports_protocol(&hc->rh, offset, count, major);
115
116 // "Implied" speed
117 if (psic == 0) {
118 assert(minor == 0);
119
120 if (major == 2) {
121 speeds[1] = default_psiv_to_port_speed[1];
122 speeds[2] = default_psiv_to_port_speed[2];
123 speeds[3] = default_psiv_to_port_speed[3];
124 } else if (major == 3) {
125 speeds[4] = default_psiv_to_port_speed[4];
126 } else {
127 return EINVAL;
128 }
129
130 usb_log_debug("Implied speed of USB %u.0 set up.", major);
131 } else {
132 for (unsigned i = 0; i < psic; i++) {
133 xhci_psi_t *psi = xhci_extcap_psi(ec, i);
134 unsigned sim = XHCI_REG_RD(psi, XHCI_PSI_PSIM);
135 unsigned psiv = XHCI_REG_RD(psi, XHCI_PSI_PSIV);
136 unsigned psie = XHCI_REG_RD(psi, XHCI_PSI_PSIE);
137 unsigned psim = XHCI_REG_RD(psi, XHCI_PSI_PSIM);
138 uint64_t bps = PSI_TO_BPS(psie, psim);
139
140 /*
141 * Speed is not implied, but using one of default PSIV. This
142 * is not clearly stated in xHCI spec. There is a clear
143 * intention to allow xHCI to specify its own speed
144 * parameters, but throughout the document, they used fixed
145 * values for e.g. High-speed (3), without stating the
146 * controller shall have implied default speeds - and for
147 * instance Intel controllers do not. So let's check if the
148 * values match and if so, accept the implied USB speed too.
149 *
150 * The main reason we need this is the usb_speed to have
151 * mapping also for devices connected to hubs.
152 */
153 if (psiv < ARRAY_SIZE(default_psiv_to_port_speed)
154 && default_psiv_to_port_speed[psiv].major == major
155 && default_psiv_to_port_speed[psiv].minor == minor
156 && default_psiv_to_port_speed[psiv].rx_bps == bps
157 && default_psiv_to_port_speed[psiv].tx_bps == bps) {
158 speeds[psiv] = default_psiv_to_port_speed[psiv];
159 usb_log_debug("Assumed default %s speed of USB %u.",
160 usb_str_speed(speeds[psiv].usb_speed), major);
161 continue;
162 }
163
164 // Custom speed
165 speeds[psiv].major = major;
166 speeds[psiv].minor = minor;
167 str_ncpy(speeds[psiv].name, 4, name.str, 4);
168 speeds[psiv].usb_speed = USB_SPEED_MAX;
169
170 if (sim == XHCI_PSI_PLT_SYMM || sim == XHCI_PSI_PLT_RX)
171 speeds[psiv].rx_bps = bps;
172 if (sim == XHCI_PSI_PLT_SYMM || sim == XHCI_PSI_PLT_TX) {
173 speeds[psiv].tx_bps = bps;
174 usb_log_debug("Speed %u set up for bps %" PRIu64
175 " / %" PRIu64 ".", psiv, speeds[psiv].rx_bps,
176 speeds[psiv].tx_bps);
177 }
178 }
179 }
180 }
181 }
182 return EOK;
183}
184
185/**
186 * Initialize MMIO spaces of xHC.
187 */
188int hc_init_mmio(xhci_hc_t *hc, const hw_res_list_parsed_t *hw_res)
189{
190 int err;
191
192 if (hw_res->mem_ranges.count != 1) {
193 usb_log_error("Unexpected MMIO area, bailing out.");
194 return EINVAL;
195 }
196
197 hc->mmio_range = hw_res->mem_ranges.ranges[0];
198
199 usb_log_debug("MMIO area at %p (size %zu), IRQ %d.",
200 RNGABSPTR(hc->mmio_range), RNGSZ(hc->mmio_range), hw_res->irqs.irqs[0]);
201
202 if (RNGSZ(hc->mmio_range) < sizeof(xhci_cap_regs_t))
203 return EOVERFLOW;
204
205 void *base;
206 if ((err = pio_enable_range(&hc->mmio_range, &base)))
207 return err;
208
209 hc->reg_base = base;
210 hc->cap_regs = (xhci_cap_regs_t *) base;
211 hc->op_regs = (xhci_op_regs_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_LENGTH));
212 hc->rt_regs = (xhci_rt_regs_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF));
213 hc->db_arry = (xhci_doorbell_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_DBOFF));
214
215 uintptr_t xec_offset = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_XECP) * sizeof(xhci_dword_t);
216 if (xec_offset > 0)
217 hc->xecp = (xhci_extcap_t *) (base + xec_offset);
218
219 usb_log_debug("Initialized MMIO reg areas:");
220 usb_log_debug("\tCapability regs: %p", hc->cap_regs);
221 usb_log_debug("\tOperational regs: %p", hc->op_regs);
222 usb_log_debug("\tRuntime regs: %p", hc->rt_regs);
223 usb_log_debug("\tDoorbell array base: %p", hc->db_arry);
224
225 xhci_dump_cap_regs(hc->cap_regs);
226
227 hc->ac64 = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_AC64);
228 hc->csz = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_CSZ);
229 hc->max_slots = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_MAX_SLOTS);
230
231 struct timeval tv;
232 getuptime(&tv);
233 hc->wrap_time = tv.tv_sec * 1000000 + tv.tv_usec;
234 hc->wrap_count = 0;
235
236 unsigned ist = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_IST);
237 hc->ist = (ist & 0x10 >> 1) * (ist & 0xf);
238
239 if ((err = xhci_rh_init(&hc->rh, hc)))
240 goto err_pio;
241
242 if ((err = hc_parse_ec(hc)))
243 goto err_rh;
244
245 return EOK;
246
247err_rh:
248 xhci_rh_fini(&hc->rh);
249err_pio:
250 pio_disable(hc->reg_base, RNGSZ(hc->mmio_range));
251 return err;
252}
253
254static int event_worker(void *arg);
255
256/**
257 * Initialize structures kept in allocated memory.
258 */
259int hc_init_memory(xhci_hc_t *hc, ddf_dev_t *device)
260{
261 int err;
262
263 if (dma_buffer_alloc(&hc->dcbaa_dma, (1 + hc->max_slots) * sizeof(uint64_t)))
264 return ENOMEM;
265 hc->dcbaa = hc->dcbaa_dma.virt;
266
267 if ((err = xhci_event_ring_init(&hc->event_ring, 1)))
268 goto err_dcbaa;
269
270 if ((err = xhci_scratchpad_alloc(hc)))
271 goto err_event_ring;
272
273 if ((err = xhci_init_commands(hc)))
274 goto err_scratch;
275
276 if ((err = xhci_bus_init(&hc->bus, hc)))
277 goto err_cmd;
278
279 fid_t fid = fibril_create(&event_worker, hc);
280 if (!fid)
281 goto err_bus;
282
283 // TODO: completion_reset
284 hc->event_fibril_completion.active = true;
285 fibril_mutex_initialize(&hc->event_fibril_completion.guard);
286 fibril_condvar_initialize(&hc->event_fibril_completion.cv);
287
288 xhci_sw_ring_init(&hc->sw_ring, PAGE_SIZE / sizeof(xhci_trb_t));
289
290 fibril_add_ready(fid);
291
292 return EOK;
293
294err_bus:
295 xhci_bus_fini(&hc->bus);
296err_cmd:
297 xhci_fini_commands(hc);
298err_scratch:
299 xhci_scratchpad_free(hc);
300err_event_ring:
301 xhci_event_ring_fini(&hc->event_ring);
302err_dcbaa:
303 hc->dcbaa = NULL;
304 dma_buffer_free(&hc->dcbaa_dma);
305 return err;
306}
307
308/*
309 * Pseudocode:
310 * ip = read(intr[0].iman)
311 * if (ip) {
312 * status = read(usbsts)
313 * assert status
314 * assert ip
315 * accept (passing status)
316 * }
317 * decline
318 */
319static const irq_cmd_t irq_commands[] = {
320 {
321 .cmd = CMD_PIO_READ_32,
322 .dstarg = 3,
323 .addr = NULL /* intr[0].iman */
324 },
325 {
326 .cmd = CMD_AND,
327 .srcarg = 3,
328 .dstarg = 4,
329 .value = 0 /* host2xhci(32, 1) */
330 },
331 {
332 .cmd = CMD_PREDICATE,
333 .srcarg = 4,
334 .value = 5
335 },
336 {
337 .cmd = CMD_PIO_READ_32,
338 .dstarg = 1,
339 .addr = NULL /* usbsts */
340 },
341 {
342 .cmd = CMD_AND,
343 .srcarg = 1,
344 .dstarg = 2,
345 .value = 0 /* host2xhci(32, XHCI_STATUS_ACK_MASK) */
346 },
347 {
348 .cmd = CMD_PIO_WRITE_A_32,
349 .srcarg = 2,
350 .addr = NULL /* usbsts */
351 },
352 {
353 .cmd = CMD_PIO_WRITE_A_32,
354 .srcarg = 3,
355 .addr = NULL /* intr[0].iman */
356 },
357 {
358 .cmd = CMD_ACCEPT
359 },
360 {
361 .cmd = CMD_DECLINE
362 }
363};
364
365
366/**
367 * Generates code to accept interrupts. The xHCI is designed primarily for
368 * MSI/MSI-X, but we use PCI Interrupt Pin. In this mode, all the Interrupters
369 * (except 0) are disabled.
370 */
371int hc_irq_code_gen(irq_code_t *code, xhci_hc_t *hc, const hw_res_list_parsed_t *hw_res, int *irq)
372{
373 assert(code);
374 assert(hw_res);
375
376 if (hw_res->irqs.count != 1) {
377 usb_log_info("Unexpected HW resources to enable interrupts.");
378 return EINVAL;
379 }
380
381 code->ranges = malloc(sizeof(irq_pio_range_t));
382 if (code->ranges == NULL)
383 return ENOMEM;
384
385 code->cmds = malloc(sizeof(irq_commands));
386 if (code->cmds == NULL) {
387 free(code->ranges);
388 return ENOMEM;
389 }
390
391 code->rangecount = 1;
392 code->ranges[0] = (irq_pio_range_t) {
393 .base = RNGABS(hc->mmio_range),
394 .size = RNGSZ(hc->mmio_range),
395 };
396
397 code->cmdcount = ARRAY_SIZE(irq_commands);
398 memcpy(code->cmds, irq_commands, sizeof(irq_commands));
399
400 void *intr0_iman = RNGABSPTR(hc->mmio_range)
401 + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF)
402 + offsetof(xhci_rt_regs_t, ir[0]);
403 void *usbsts = RNGABSPTR(hc->mmio_range)
404 + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_LENGTH)
405 + offsetof(xhci_op_regs_t, usbsts);
406
407 code->cmds[0].addr = intr0_iman;
408 code->cmds[1].value = host2xhci(32, 1);
409 code->cmds[3].addr = usbsts;
410 code->cmds[4].value = host2xhci(32, XHCI_STATUS_ACK_MASK);
411 code->cmds[5].addr = usbsts;
412 code->cmds[6].addr = intr0_iman;
413
414 *irq = hw_res->irqs.irqs[0];
415 return EOK;
416}
417
418/**
419 * Claim xHC from BIOS. Implements handoff as per Section 4.22.1 of xHCI spec.
420 */
421int hc_claim(xhci_hc_t *hc, ddf_dev_t *dev)
422{
423 /* No legacy support capability, the controller is solely for us */
424 if (!hc->legsup)
425 return EOK;
426
427 if (xhci_reg_wait(&hc->op_regs->usbsts, XHCI_REG_MASK(XHCI_OP_CNR), 0))
428 return ETIMEOUT;
429
430 usb_log_debug("LEGSUP: bios: %x, os: %x", hc->legsup->sem_bios, hc->legsup->sem_os);
431 XHCI_REG_SET(hc->legsup, XHCI_LEGSUP_SEM_OS, 1);
432 for (int i = 0; i <= (XHCI_LEGSUP_BIOS_TIMEOUT_US / XHCI_LEGSUP_POLLING_DELAY_1MS); i++) {
433 usb_log_debug("LEGSUP: elapsed: %i ms, bios: %x, os: %x", i,
434 XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_BIOS),
435 XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_OS));
436 if (XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_BIOS) == 0) {
437 return XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_OS) == 1 ? EOK : EIO;
438 }
439 async_usleep(XHCI_LEGSUP_POLLING_DELAY_1MS);
440 }
441 usb_log_error("BIOS did not release XHCI legacy hold!");
442
443 return ENOTSUP;
444}
445
446/**
447 * Ask the xHC to reset its state. Implements sequence
448 */
449static int hc_reset(xhci_hc_t *hc)
450{
451 if (xhci_reg_wait(&hc->op_regs->usbsts, XHCI_REG_MASK(XHCI_OP_CNR), 0))
452 return ETIMEOUT;
453
454 /* Stop the HC: set R/S to 0 */
455 XHCI_REG_CLR(hc->op_regs, XHCI_OP_RS, 1);
456
457 /* Wait until the HC is halted - it shall take at most 16 ms */
458 if (xhci_reg_wait(&hc->op_regs->usbsts, XHCI_REG_MASK(XHCI_OP_HCH),
459 XHCI_REG_MASK(XHCI_OP_HCH)))
460 return ETIMEOUT;
461
462 /* Reset */
463 XHCI_REG_SET(hc->op_regs, XHCI_OP_HCRST, 1);
464
465 /* Wait until the reset is complete */
466 if (xhci_reg_wait(&hc->op_regs->usbcmd, XHCI_REG_MASK(XHCI_OP_HCRST), 0))
467 return ETIMEOUT;
468
469 return EOK;
470}
471
472/**
473 * Initialize the HC: section 4.2
474 */
475int hc_start(xhci_hc_t *hc, bool irq)
476{
477 int err;
478
479 if ((err = hc_reset(hc)))
480 return err;
481
482 if (xhci_reg_wait(&hc->op_regs->usbsts, XHCI_REG_MASK(XHCI_OP_CNR), 0))
483 return ETIMEOUT;
484
485 uint64_t dcbaaptr = hc->dcbaa_dma.phys;
486 XHCI_REG_WR(hc->op_regs, XHCI_OP_DCBAAP_LO, LOWER32(dcbaaptr));
487 XHCI_REG_WR(hc->op_regs, XHCI_OP_DCBAAP_HI, UPPER32(dcbaaptr));
488 XHCI_REG_WR(hc->op_regs, XHCI_OP_MAX_SLOTS_EN, hc->max_slots);
489
490 uintptr_t crcr;
491 xhci_trb_ring_reset_dequeue_state(&hc->cr.trb_ring, &crcr);
492 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_LO, LOWER32(crcr));
493 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_HI, UPPER32(crcr));
494
495 XHCI_REG_SET(hc->op_regs, XHCI_OP_EWE, 1);
496
497 xhci_interrupter_regs_t *intr0 = &hc->rt_regs->ir[0];
498 XHCI_REG_WR(intr0, XHCI_INTR_ERSTSZ, hc->event_ring.segment_count);
499 uint64_t erdp = hc->event_ring.dequeue_ptr;
500 XHCI_REG_WR(intr0, XHCI_INTR_ERDP_LO, LOWER32(erdp));
501 XHCI_REG_WR(intr0, XHCI_INTR_ERDP_HI, UPPER32(erdp));
502 uint64_t erstptr = hc->event_ring.erst.phys;
503 XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA_LO, LOWER32(erstptr));
504 XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA_HI, UPPER32(erstptr));
505
506 if (irq) {
507 XHCI_REG_SET(intr0, XHCI_INTR_IE, 1);
508 XHCI_REG_SET(hc->op_regs, XHCI_OP_INTE, 1);
509 }
510
511 XHCI_REG_SET(hc->op_regs, XHCI_OP_HSEE, 1);
512
513 XHCI_REG_SET(hc->op_regs, XHCI_OP_RS, 1);
514
515 xhci_rh_startup(&hc->rh);
516
517 return EOK;
518}
519
520/**
521 * Used only when polling. Shall supplement the irq_commands.
522 */
523int hc_status(bus_t *bus, uint32_t *status)
524{
525 xhci_hc_t *hc = bus_to_hc(bus);
526 int ip = XHCI_REG_RD(hc->rt_regs->ir, XHCI_INTR_IP);
527 if (ip) {
528 *status = XHCI_REG_RD(hc->op_regs, XHCI_OP_STATUS);
529 XHCI_REG_WR(hc->op_regs, XHCI_OP_STATUS, *status & XHCI_STATUS_ACK_MASK);
530 XHCI_REG_WR(hc->rt_regs->ir, XHCI_INTR_IP, 1);
531
532 /* interrupt handler expects status from irq_commands, which is
533 * in xhci order. */
534 *status = host2xhci(32, *status);
535 }
536
537 usb_log_debug("Polled status: %x", *status);
538 return EOK;
539}
540
541static int xhci_handle_mfindex_wrap_event(xhci_hc_t *hc, xhci_trb_t *trb)
542{
543 struct timeval tv;
544 getuptime(&tv);
545 usb_log_debug("Microframe index wrapped (@%lu.%li, %"PRIu64" total).",
546 tv.tv_sec, tv.tv_usec, hc->wrap_count);
547 hc->wrap_time = ((uint64_t) tv.tv_sec) * 1000000 + ((uint64_t) tv.tv_usec);
548 ++hc->wrap_count;
549 return EOK;
550}
551
552typedef int (*event_handler) (xhci_hc_t *, xhci_trb_t *trb);
553
554/**
555 * These events are handled by separate event handling fibril.
556 */
557static event_handler event_handlers [] = {
558 [XHCI_TRB_TYPE_TRANSFER_EVENT] = &xhci_handle_transfer_event,
559};
560
561/**
562 * These events are handled directly in the interrupt handler, thus they must
563 * not block waiting for another interrupt.
564 */
565static event_handler event_handlers_fast [] = {
566 [XHCI_TRB_TYPE_COMMAND_COMPLETION_EVENT] = &xhci_handle_command_completion,
567 [XHCI_TRB_TYPE_MFINDEX_WRAP_EVENT] = &xhci_handle_mfindex_wrap_event,
568};
569
570static int hc_handle_event(xhci_hc_t *hc, xhci_trb_t *trb)
571{
572 const unsigned type = TRB_TYPE(*trb);
573
574 if (type <= ARRAY_SIZE(event_handlers_fast) && event_handlers_fast[type])
575 return event_handlers_fast[type](hc, trb);
576
577 if (type <= ARRAY_SIZE(event_handlers) && event_handlers[type])
578 return xhci_sw_ring_enqueue(&hc->sw_ring, trb);
579
580 if (type == XHCI_TRB_TYPE_PORT_STATUS_CHANGE_EVENT)
581 return xhci_sw_ring_enqueue(&hc->rh.event_ring, trb);
582
583 return ENOTSUP;
584}
585
586static int event_worker(void *arg)
587{
588 int err;
589 xhci_trb_t trb;
590 xhci_hc_t * const hc = arg;
591 assert(hc);
592
593 while (xhci_sw_ring_dequeue(&hc->sw_ring, &trb) != EINTR) {
594 const unsigned type = TRB_TYPE(trb);
595
596 if ((err = event_handlers[type](hc, &trb)))
597 usb_log_error("Failed to handle event: %s", str_error(err));
598 }
599
600 // TODO: completion_complete
601 fibril_mutex_lock(&hc->event_fibril_completion.guard);
602 hc->event_fibril_completion.active = false;
603 fibril_condvar_broadcast(&hc->event_fibril_completion.cv);
604 fibril_mutex_unlock(&hc->event_fibril_completion.guard);
605
606 return EOK;
607}
608
609/**
610 * Dequeue from event ring and handle dequeued events.
611 *
612 * As there can be events, that blocks on waiting for subsequent events,
613 * we solve this problem by deferring some types of events to separate fibrils.
614 */
615static void hc_run_event_ring(xhci_hc_t *hc, xhci_event_ring_t *event_ring,
616 xhci_interrupter_regs_t *intr)
617{
618 int err;
619
620 xhci_trb_t trb;
621 hc->event_handler = fibril_get_id();
622
623 while ((err = xhci_event_ring_dequeue(event_ring, &trb)) != ENOENT) {
624 if ((err = hc_handle_event(hc, &trb)) != EOK) {
625 usb_log_error("Failed to handle event in interrupt: %s", str_error(err));
626 }
627
628 uint64_t erdp = hc->event_ring.dequeue_ptr;
629 XHCI_REG_WR(intr, XHCI_INTR_ERDP_LO, LOWER32(erdp));
630 XHCI_REG_WR(intr, XHCI_INTR_ERDP_HI, UPPER32(erdp));
631 }
632
633 hc->event_handler = 0;
634
635 /* Update the ERDP to make room in the ring. */
636 uint64_t erdp = hc->event_ring.dequeue_ptr;
637 erdp |= XHCI_REG_MASK(XHCI_INTR_ERDP_EHB);
638 XHCI_REG_WR(intr, XHCI_INTR_ERDP_LO, LOWER32(erdp));
639 XHCI_REG_WR(intr, XHCI_INTR_ERDP_HI, UPPER32(erdp));
640
641 usb_log_debug2("Event ring run finished.");
642}
643
644/**
645 * Handle an interrupt request from xHC. Resolve all situations that trigger an
646 * interrupt separately.
647 *
648 * Note that all RW1C bits in USBSTS register are cleared at the time of
649 * handling the interrupt in irq_code. This method is the top-half.
650 *
651 * @param status contents of USBSTS register at the time of the interrupt.
652 */
653void hc_interrupt(bus_t *bus, uint32_t status)
654{
655 xhci_hc_t *hc = bus_to_hc(bus);
656 status = xhci2host(32, status);
657
658 if (status & XHCI_REG_MASK(XHCI_OP_HSE)) {
659 usb_log_error("Host controller error occured. Bad things gonna happen...");
660 status &= ~XHCI_REG_MASK(XHCI_OP_HSE);
661 }
662
663 if (status & XHCI_REG_MASK(XHCI_OP_EINT)) {
664 usb_log_debug2("Event interrupt, running the event ring.");
665 hc_run_event_ring(hc, &hc->event_ring, &hc->rt_regs->ir[0]);
666 status &= ~XHCI_REG_MASK(XHCI_OP_EINT);
667 }
668
669 if (status & XHCI_REG_MASK(XHCI_OP_SRE)) {
670 usb_log_error("Save/Restore error occured. WTF, "
671 "S/R mechanism not implemented!");
672 status &= ~XHCI_REG_MASK(XHCI_OP_SRE);
673 }
674
675 /* According to Note on p. 302, we may safely ignore the PCD bit. */
676 status &= ~XHCI_REG_MASK(XHCI_OP_PCD);
677
678 if (status) {
679 usb_log_error("Non-zero status after interrupt handling (%08x) "
680 " - missing something?", status);
681 }
682}
683
684/**
685 * Tear down all in-memory structures.
686 */
687void hc_fini(xhci_hc_t *hc)
688{
689 xhci_sw_ring_stop(&hc->sw_ring);
690
691 // TODO: completion_wait
692 fibril_mutex_lock(&hc->event_fibril_completion.guard);
693 while (hc->event_fibril_completion.active)
694 fibril_condvar_wait(&hc->event_fibril_completion.cv,
695 &hc->event_fibril_completion.guard);
696 fibril_mutex_unlock(&hc->event_fibril_completion.guard);
697 xhci_sw_ring_fini(&hc->sw_ring);
698
699 xhci_bus_fini(&hc->bus);
700 xhci_event_ring_fini(&hc->event_ring);
701 xhci_scratchpad_free(hc);
702 dma_buffer_free(&hc->dcbaa_dma);
703 xhci_fini_commands(hc);
704 xhci_rh_fini(&hc->rh);
705 pio_disable(hc->reg_base, RNGSZ(hc->mmio_range));
706 usb_log_info("Finalized.");
707}
708
709unsigned hc_speed_to_psiv(usb_speed_t speed)
710{
711 assert(speed < ARRAY_SIZE(usb_speed_to_psiv));
712 return usb_speed_to_psiv[speed];
713}
714
715/**
716 * Ring a xHC Doorbell. Implements section 4.7.
717 */
718void hc_ring_doorbell(xhci_hc_t *hc, unsigned doorbell, unsigned target)
719{
720 assert(hc);
721 uint32_t v = host2xhci(32, target & BIT_RRANGE(uint32_t, 7));
722 pio_write_32(&hc->db_arry[doorbell], v);
723 usb_log_debug2("Ringing doorbell %d (target: %d)", doorbell, target);
724}
725
726/**
727 * Return an index to device context.
728 */
729static uint8_t endpoint_dci(xhci_endpoint_t *ep)
730{
731 return (2 * ep->base.endpoint) +
732 (ep->base.transfer_type == USB_TRANSFER_CONTROL
733 || ep->base.direction == USB_DIRECTION_IN);
734}
735
736void hc_ring_ep_doorbell(xhci_endpoint_t *ep, uint32_t stream_id)
737{
738 xhci_device_t * const dev = xhci_ep_to_dev(ep);
739 xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
740 const uint8_t dci = endpoint_dci(ep);
741 const uint32_t target = (stream_id << 16) | (dci & 0x1ff);
742 hc_ring_doorbell(hc, dev->slot_id, target);
743}
744
745/**
746 * Issue an Enable Slot command. Allocate memory for the slot and fill the
747 * DCBAA with the newly created slot.
748 */
749int hc_enable_slot(xhci_device_t *dev)
750{
751 int err;
752 xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
753
754 /* Prepare memory for the context */
755 if ((err = dma_buffer_alloc(&dev->dev_ctx, XHCI_DEVICE_CTX_SIZE(hc))))
756 return err;
757 memset(dev->dev_ctx.virt, 0, XHCI_DEVICE_CTX_SIZE(hc));
758
759 /* Get the slot number */
760 xhci_cmd_t cmd;
761 xhci_cmd_init(&cmd, XHCI_CMD_ENABLE_SLOT);
762
763 err = xhci_cmd_sync(hc, &cmd);
764
765 /* Link them together */
766 if (err == EOK) {
767 dev->slot_id = cmd.slot_id;
768 hc->dcbaa[dev->slot_id] = host2xhci(64, dev->dev_ctx.phys);
769 }
770
771 xhci_cmd_fini(&cmd);
772
773 if (err)
774 dma_buffer_free(&dev->dev_ctx);
775
776 return err;
777}
778
779/**
780 * Issue a Disable Slot command for a slot occupied by device.
781 * Frees the device context.
782 */
783int hc_disable_slot(xhci_device_t *dev)
784{
785 int err;
786 xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
787
788 if ((err = xhci_cmd_sync_inline(hc, DISABLE_SLOT, .slot_id = dev->slot_id))) {
789 return err;
790 }
791
792 /* Free the device context. */
793 hc->dcbaa[dev->slot_id] = 0;
794 dma_buffer_free(&dev->dev_ctx);
795
796 /* Mark the slot as invalid. */
797 dev->slot_id = 0;
798
799 return EOK;
800}
801
802/**
803 * Prepare an empty Endpoint Input Context inside a dma buffer.
804 */
805static int create_configure_ep_input_ctx(xhci_device_t *dev, dma_buffer_t *dma_buf)
806{
807 const xhci_hc_t * hc = bus_to_hc(dev->base.bus);
808 const int err = dma_buffer_alloc(dma_buf, XHCI_INPUT_CTX_SIZE(hc));
809 if (err)
810 return err;
811
812 xhci_input_ctx_t *ictx = dma_buf->virt;
813 memset(ictx, 0, XHCI_INPUT_CTX_SIZE(hc));
814
815 // Quoting sec. 4.6.5 and 4.6.6: A1, D0, D1 are down (already zeroed), A0 is up.
816 XHCI_INPUT_CTRL_CTX_ADD_SET(*XHCI_GET_CTRL_CTX(ictx, hc), 0);
817 xhci_slot_ctx_t *slot_ctx = XHCI_GET_SLOT_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc);
818 xhci_setup_slot_context(dev, slot_ctx);
819
820 return EOK;
821}
822
823/**
824 * Initialize a device, assigning it an address. Implements section 4.3.4.
825 *
826 * @param dev Device to assing an address (unconfigured yet)
827 */
828int hc_address_device(xhci_device_t *dev)
829{
830 int err = ENOMEM;
831 xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
832 xhci_endpoint_t *ep0 = xhci_endpoint_get(dev->base.endpoints[0]);
833
834 /* Although we have the precise PSIV value on devices of tier 1,
835 * we have to rely on reverse mapping on others. */
836 if (!usb_speed_to_psiv[dev->base.speed]) {
837 usb_log_error("Device reported an USB speed (%s) that cannot be mapped "
838 "to HC port speed.", usb_str_speed(dev->base.speed));
839 return EINVAL;
840 }
841
842 /* Issue configure endpoint command (sec 4.3.5). */
843 dma_buffer_t ictx_dma_buf;
844 if ((err = create_configure_ep_input_ctx(dev, &ictx_dma_buf)))
845 return err;
846 xhci_input_ctx_t *ictx = ictx_dma_buf.virt;
847
848 /* Copy endpoint 0 context and set A1 flag. */
849 XHCI_INPUT_CTRL_CTX_ADD_SET(*XHCI_GET_CTRL_CTX(ictx, hc), 1);
850 xhci_ep_ctx_t *ep_ctx = XHCI_GET_EP_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc, 1);
851 xhci_setup_endpoint_context(ep0, ep_ctx);
852
853 /* Address device needs Ctx entries set to 1 only */
854 xhci_slot_ctx_t *slot_ctx = XHCI_GET_SLOT_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc);
855 XHCI_SLOT_CTX_ENTRIES_SET(*slot_ctx, 1);
856
857 /* Issue Address Device command. */
858 if ((err = xhci_cmd_sync_inline(hc, ADDRESS_DEVICE,
859 .slot_id = dev->slot_id,
860 .input_ctx = ictx_dma_buf
861 )))
862 return err;
863
864 xhci_device_ctx_t *device_ctx = dev->dev_ctx.virt;
865 dev->base.address = XHCI_SLOT_DEVICE_ADDRESS(*XHCI_GET_SLOT_CTX(device_ctx, hc));
866 usb_log_debug("Obtained USB address: %d.", dev->base.address);
867
868 return EOK;
869}
870
871/**
872 * Issue a Configure Device command for a device in slot.
873 *
874 * @param slot_id Slot ID assigned to the device.
875 */
876int hc_configure_device(xhci_device_t *dev)
877{
878 xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
879
880 /* Issue configure endpoint command (sec 4.3.5). */
881 dma_buffer_t ictx_dma_buf;
882 const int err = create_configure_ep_input_ctx(dev, &ictx_dma_buf);
883 if (err)
884 return err;
885
886 return xhci_cmd_sync_inline(hc, CONFIGURE_ENDPOINT,
887 .slot_id = dev->slot_id,
888 .input_ctx = ictx_dma_buf
889 );
890}
891
892/**
893 * Issue a Deconfigure Device command for a device in slot.
894 *
895 * @param dev The owner of the device
896 */
897int hc_deconfigure_device(xhci_device_t *dev)
898{
899 xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
900
901 /* Issue configure endpoint command (sec 4.3.5) with the DC flag. */
902 return xhci_cmd_sync_inline(hc, CONFIGURE_ENDPOINT,
903 .slot_id = dev->slot_id,
904 .deconfigure = true
905 );
906}
907
908/**
909 * Instruct xHC to add an endpoint with supplied endpoint context.
910 *
911 * @param dev The owner of the device
912 * @param ep_idx Endpoint DCI in question
913 * @param ep_ctx Endpoint context of the endpoint
914 */
915int hc_add_endpoint(xhci_endpoint_t *ep)
916{
917 xhci_device_t * const dev = xhci_ep_to_dev(ep);
918 const unsigned dci = endpoint_dci(ep);
919
920 /* Issue configure endpoint command (sec 4.3.5). */
921 dma_buffer_t ictx_dma_buf;
922 const int err = create_configure_ep_input_ctx(dev, &ictx_dma_buf);
923 if (err)
924 return err;
925
926 xhci_input_ctx_t *ictx = ictx_dma_buf.virt;
927
928 xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
929 XHCI_INPUT_CTRL_CTX_ADD_SET(*XHCI_GET_CTRL_CTX(ictx, hc), dci);
930
931 xhci_ep_ctx_t *ep_ctx = XHCI_GET_EP_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc, dci);
932 xhci_setup_endpoint_context(ep, ep_ctx);
933
934 return xhci_cmd_sync_inline(hc, CONFIGURE_ENDPOINT,
935 .slot_id = dev->slot_id,
936 .input_ctx = ictx_dma_buf
937 );
938}
939
940/**
941 * Instruct xHC to drop an endpoint.
942 *
943 * @param dev The owner of the endpoint
944 * @param ep_idx Endpoint DCI in question
945 */
946int hc_drop_endpoint(xhci_endpoint_t *ep)
947{
948 xhci_device_t * const dev = xhci_ep_to_dev(ep);
949 const unsigned dci = endpoint_dci(ep);
950
951 /* Issue configure endpoint command (sec 4.3.5). */
952 dma_buffer_t ictx_dma_buf;
953 const int err = create_configure_ep_input_ctx(dev, &ictx_dma_buf);
954 if (err)
955 return err;
956
957 xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
958 xhci_input_ctx_t *ictx = ictx_dma_buf.virt;
959 XHCI_INPUT_CTRL_CTX_DROP_SET(*XHCI_GET_CTRL_CTX(ictx, hc), dci);
960
961 return xhci_cmd_sync_inline(hc, CONFIGURE_ENDPOINT,
962 .slot_id = dev->slot_id,
963 .input_ctx = ictx_dma_buf
964 );
965}
966
967/**
968 * Instruct xHC to update information about an endpoint, using supplied
969 * endpoint context.
970 *
971 * @param dev The owner of the endpoint
972 * @param ep_idx Endpoint DCI in question
973 * @param ep_ctx Endpoint context of the endpoint
974 */
975int hc_update_endpoint(xhci_endpoint_t *ep)
976{
977 xhci_device_t * const dev = xhci_ep_to_dev(ep);
978 const unsigned dci = endpoint_dci(ep);
979
980 dma_buffer_t ictx_dma_buf;
981 xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
982
983 const int err = dma_buffer_alloc(&ictx_dma_buf, XHCI_INPUT_CTX_SIZE(hc));
984 if (err)
985 return err;
986
987 xhci_input_ctx_t *ictx = ictx_dma_buf.virt;
988 memset(ictx, 0, XHCI_INPUT_CTX_SIZE(hc));
989
990 XHCI_INPUT_CTRL_CTX_ADD_SET(*XHCI_GET_CTRL_CTX(ictx, hc), dci);
991 xhci_ep_ctx_t *ep_ctx = XHCI_GET_EP_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc, dci);
992 xhci_setup_endpoint_context(ep, ep_ctx);
993
994 return xhci_cmd_sync_inline(hc, EVALUATE_CONTEXT,
995 .slot_id = dev->slot_id,
996 .input_ctx = ictx_dma_buf
997 );
998}
999
1000/**
1001 * Instruct xHC to stop running a transfer ring on an endpoint.
1002 *
1003 * @param dev The owner of the endpoint
1004 * @param ep_idx Endpoint DCI in question
1005 */
1006int hc_stop_endpoint(xhci_endpoint_t *ep)
1007{
1008 xhci_device_t * const dev = xhci_ep_to_dev(ep);
1009 const unsigned dci = endpoint_dci(ep);
1010 xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
1011 return xhci_cmd_sync_inline(hc, STOP_ENDPOINT,
1012 .slot_id = dev->slot_id,
1013 .endpoint_id = dci
1014 );
1015}
1016
1017/**
1018 * Instruct xHC to reset halted endpoint.
1019 *
1020 * @param dev The owner of the endpoint
1021 * @param ep_idx Endpoint DCI in question
1022 */
1023int hc_reset_endpoint(xhci_endpoint_t *ep)
1024{
1025 xhci_device_t * const dev = xhci_ep_to_dev(ep);
1026 const unsigned dci = endpoint_dci(ep);
1027 xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
1028 return xhci_cmd_sync_inline(hc, RESET_ENDPOINT,
1029 .slot_id = dev->slot_id,
1030 .endpoint_id = dci
1031 );
1032}
1033
1034/**
1035 * Reset a ring position in both software and hardware.
1036 *
1037 * @param dev The owner of the endpoint
1038 */
1039int hc_reset_ring(xhci_endpoint_t *ep, uint32_t stream_id)
1040{
1041 xhci_device_t * const dev = xhci_ep_to_dev(ep);
1042 const unsigned dci = endpoint_dci(ep);
1043 uintptr_t addr;
1044
1045 xhci_trb_ring_t *ring = xhci_endpoint_get_ring(ep, stream_id);
1046 xhci_trb_ring_reset_dequeue_state(ring, &addr);
1047
1048 xhci_hc_t * const hc = bus_to_hc(endpoint_get_bus(&ep->base));
1049 return xhci_cmd_sync_inline(hc, SET_TR_DEQUEUE_POINTER,
1050 .slot_id = dev->slot_id,
1051 .endpoint_id = dci,
1052 .stream_id = stream_id,
1053 .dequeue_ptr = addr,
1054 );
1055}
1056
1057/**
1058 * @}
1059 */
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