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Last change on this file since da9d6ca was 132ab5d1, checked in by Jenda <jenda.jzqk73@…>, 8 years ago

Merge commit '6a5d05bd2551e64111bea4f9332dd7448c26ce84' into forwardport

Separate return value from error code in gen_irq_code*().

Property mode set to 100644

File size: 29.3 KB

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1	/*
2	* Copyright (c) 2017 Ondrej Hlavaty
3	* All rights reserved.
4	*
5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions
7	* are met:
8	*
9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.
16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/
28
29	/** @addtogroup drvusbxhci
30	* @{
31	*/
32	/** @file
33	* @brief The host controller data bookkeeping.
34	*/
35
36	#include <errno.h>
37	#include <str_error.h>
38	#include <usb/debug.h>
39	#include <usb/host/endpoint.h>
40	#include "debug.h"
41	#include "hc.h"
42	#include "rh.h"
43	#include "hw_struct/trb.h"
44	#include "hw_struct/context.h"
45	#include "endpoint.h"
46	#include "transfers.h"
47	#include "trb_ring.h"
48
49	/**
50	* Default USB Speed ID mapping: Table 157
51	*/
52	#define PSI_TO_BPS(psie, psim) (((uint64_t) psim) << (10 * psie))
53	#define PORT_SPEED(usb, mjr, psie, psim) { \
54	.name = "USB ", \
55	.major = mjr, \
56	.minor = 0, \
57	.usb_speed = USB_SPEED_##usb, \
58	.rx_bps = PSI_TO_BPS(psie, psim), \
59	.tx_bps = PSI_TO_BPS(psie, psim) \
60	}
61
62	static const xhci_port_speed_t default_psiv_to_port_speed [] = {
63	[1] = PORT_SPEED(FULL, 2, 2, 12),
64	[2] = PORT_SPEED(LOW, 2, 1, 1500),
65	[3] = PORT_SPEED(HIGH, 2, 2, 480),
66	[4] = PORT_SPEED(SUPER, 3, 3, 5),
67	};
68
69	static const unsigned usb_speed_to_psiv [] = {
70	[USB_SPEED_FULL] = 1,
71	[USB_SPEED_LOW] = 2,
72	[USB_SPEED_HIGH] = 3,
73	[USB_SPEED_SUPER] = 4,
74	};
75
76	/**
77	* Walk the list of extended capabilities.
78	*
79	* The most interesting thing hidden in extended capabilities is the mapping of
80	* ports to protocol versions and speeds.
81	*/
82	static int hc_parse_ec(xhci_hc_t *hc)
83	{
84	unsigned psic, major, minor;
85	xhci_sp_name_t name;
86
87	xhci_port_speed_t *speeds = hc->speeds;
88
89	for (xhci_extcap_t *ec = hc->xecp; ec; ec = xhci_extcap_next(ec)) {
90	xhci_dump_extcap(ec);
91	switch (XHCI_REG_RD(ec, XHCI_EC_CAP_ID)) {
92	case XHCI_EC_USB_LEGACY:
93	assert(hc->legsup == NULL);
94	hc->legsup = (xhci_legsup_t *) ec;
95	break;
96	case XHCI_EC_SUPPORTED_PROTOCOL:
97	psic = XHCI_REG_RD(ec, XHCI_EC_SP_PSIC);
98	major = XHCI_REG_RD(ec, XHCI_EC_SP_MAJOR);
99	minor = XHCI_REG_RD(ec, XHCI_EC_SP_MINOR);
100	name.packed = host2uint32_t_le(XHCI_REG_RD(ec, XHCI_EC_SP_NAME));
101
102	if (name.packed != xhci_name_usb.packed) {
103	/**
104	* The detection of such protocol would work,
105	* but the rest of the implementation is made
106	* for the USB protocol only.
107	*/
108	usb_log_error("Unknown protocol %.4s.", name.str);
109	return ENOTSUP;
110	}
111
112	unsigned offset = XHCI_REG_RD(ec, XHCI_EC_SP_CP_OFF);
113	unsigned count = XHCI_REG_RD(ec, XHCI_EC_SP_CP_COUNT);
114	xhci_rh_set_ports_protocol(&hc->rh, offset, count, major);
115
116	// "Implied" speed
117	if (psic == 0) {
118	assert(minor == 0);
119
120	if (major == 2) {
121	speeds[1] = default_psiv_to_port_speed[1];
122	speeds[2] = default_psiv_to_port_speed[2];
123	speeds[3] = default_psiv_to_port_speed[3];
124	} else if (major == 3) {
125	speeds[4] = default_psiv_to_port_speed[4];
126	} else {
127	return EINVAL;
128	}
129
130	usb_log_debug("Implied speed of USB %u.0 set up.", major);
131	} else {
132	for (unsigned i = 0; i < psic; i++) {
133	xhci_psi_t *psi = xhci_extcap_psi(ec, i);
134	unsigned sim = XHCI_REG_RD(psi, XHCI_PSI_PSIM);
135	unsigned psiv = XHCI_REG_RD(psi, XHCI_PSI_PSIV);
136	unsigned psie = XHCI_REG_RD(psi, XHCI_PSI_PSIE);
137	unsigned psim = XHCI_REG_RD(psi, XHCI_PSI_PSIM);
138	uint64_t bps = PSI_TO_BPS(psie, psim);
139
140	/*
141	* Speed is not implied, but using one of default PSIV. This
142	* is not clearly stated in xHCI spec. There is a clear
143	* intention to allow xHCI to specify its own speed
144	* parameters, but throughout the document, they used fixed
145	* values for e.g. High-speed (3), without stating the
146	* controller shall have implied default speeds - and for
147	* instance Intel controllers do not. So let's check if the
148	* values match and if so, accept the implied USB speed too.
149	*
150	* The main reason we need this is the usb_speed to have
151	* mapping also for devices connected to hubs.
152	*/
153	if (psiv < ARRAY_SIZE(default_psiv_to_port_speed)
154	&& default_psiv_to_port_speed[psiv].major == major
155	&& default_psiv_to_port_speed[psiv].minor == minor
156	&& default_psiv_to_port_speed[psiv].rx_bps == bps
157	&& default_psiv_to_port_speed[psiv].tx_bps == bps) {
158	speeds[psiv] = default_psiv_to_port_speed[psiv];
159	usb_log_debug("Assumed default %s speed of USB %u.",
160	usb_str_speed(speeds[psiv].usb_speed), major);
161	continue;
162	}
163
164	// Custom speed
165	speeds[psiv].major = major;
166	speeds[psiv].minor = minor;
167	str_ncpy(speeds[psiv].name, 4, name.str, 4);
168	speeds[psiv].usb_speed = USB_SPEED_MAX;
169
170	if (sim == XHCI_PSI_PLT_SYMM \|\| sim == XHCI_PSI_PLT_RX)
171	speeds[psiv].rx_bps = bps;
172	if (sim == XHCI_PSI_PLT_SYMM \|\| sim == XHCI_PSI_PLT_TX) {
173	speeds[psiv].tx_bps = bps;
174	usb_log_debug("Speed %u set up for bps %" PRIu64
175	" / %" PRIu64 ".", psiv, speeds[psiv].rx_bps,
176	speeds[psiv].tx_bps);
177	}
178	}
179	}
180	}
181	}
182	return EOK;
183	}
184
185	/**
186	* Initialize MMIO spaces of xHC.
187	*/
188	int hc_init_mmio(xhci_hc_t hc, const hw_res_list_parsed_t hw_res)
189	{
190	int err;
191
192	if (hw_res->mem_ranges.count != 1) {
193	usb_log_error("Unexpected MMIO area, bailing out.");
194	return EINVAL;
195	}
196
197	hc->mmio_range = hw_res->mem_ranges.ranges[0];
198
199	usb_log_debug("MMIO area at %p (size %zu), IRQ %d.",
200	RNGABSPTR(hc->mmio_range), RNGSZ(hc->mmio_range), hw_res->irqs.irqs[0]);
201
202	if (RNGSZ(hc->mmio_range) < sizeof(xhci_cap_regs_t))
203	return EOVERFLOW;
204
205	void *base;
206	if ((err = pio_enable_range(&hc->mmio_range, &base)))
207	return err;
208
209	hc->reg_base = base;
210	hc->cap_regs = (xhci_cap_regs_t *) base;
211	hc->op_regs = (xhci_op_regs_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_LENGTH));
212	hc->rt_regs = (xhci_rt_regs_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF));
213	hc->db_arry = (xhci_doorbell_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_DBOFF));
214
215	uintptr_t xec_offset = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_XECP) * sizeof(xhci_dword_t);
216	if (xec_offset > 0)
217	hc->xecp = (xhci_extcap_t *) (base + xec_offset);
218
219	usb_log_debug("Initialized MMIO reg areas:");
220	usb_log_debug("\tCapability regs: %p", hc->cap_regs);
221	usb_log_debug("\tOperational regs: %p", hc->op_regs);
222	usb_log_debug("\tRuntime regs: %p", hc->rt_regs);
223	usb_log_debug("\tDoorbell array base: %p", hc->db_arry);
224
225	xhci_dump_cap_regs(hc->cap_regs);
226
227	hc->ac64 = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_AC64);
228	hc->csz = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_CSZ);
229	hc->max_slots = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_MAX_SLOTS);
230
231	struct timeval tv;
232	getuptime(&tv);
233	hc->wrap_time = tv.tv_sec * 1000000 + tv.tv_usec;
234	hc->wrap_count = 0;
235
236	unsigned ist = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_IST);
237	hc->ist = (ist & 0x10 >> 1) * (ist & 0xf);
238
239	if ((err = xhci_rh_init(&hc->rh, hc)))
240	goto err_pio;
241
242	if ((err = hc_parse_ec(hc)))
243	goto err_rh;
244
245	return EOK;
246
247	err_rh:
248	xhci_rh_fini(&hc->rh);
249	err_pio:
250	pio_disable(hc->reg_base, RNGSZ(hc->mmio_range));
251	return err;
252	}
253
254	static int event_worker(void *arg);
255
256	/**
257	* Initialize structures kept in allocated memory.
258	*/
259	int hc_init_memory(xhci_hc_t hc, ddf_dev_t device)
260	{
261	int err;
262
263	if (dma_buffer_alloc(&hc->dcbaa_dma, (1 + hc->max_slots) * sizeof(uint64_t)))
264	return ENOMEM;
265	hc->dcbaa = hc->dcbaa_dma.virt;
266
267	if ((err = xhci_event_ring_init(&hc->event_ring, 1)))
268	goto err_dcbaa;
269
270	if ((err = xhci_scratchpad_alloc(hc)))
271	goto err_event_ring;
272
273	if ((err = xhci_init_commands(hc)))
274	goto err_scratch;
275
276	if ((err = xhci_bus_init(&hc->bus, hc)))
277	goto err_cmd;
278
279	fid_t fid = fibril_create(&event_worker, hc);
280	if (!fid)
281	goto err_bus;
282
283	// TODO: completion_reset
284	hc->event_fibril_completion.active = true;
285	fibril_mutex_initialize(&hc->event_fibril_completion.guard);
286	fibril_condvar_initialize(&hc->event_fibril_completion.cv);
287
288	xhci_sw_ring_init(&hc->sw_ring, PAGE_SIZE / sizeof(xhci_trb_t));
289
290	fibril_add_ready(fid);
291
292	return EOK;
293
294	err_bus:
295	xhci_bus_fini(&hc->bus);
296	err_cmd:
297	xhci_fini_commands(hc);
298	err_scratch:
299	xhci_scratchpad_free(hc);
300	err_event_ring:
301	xhci_event_ring_fini(&hc->event_ring);
302	err_dcbaa:
303	hc->dcbaa = NULL;
304	dma_buffer_free(&hc->dcbaa_dma);
305	return err;
306	}
307
308	/*
309	* Pseudocode:
310	* ip = read(intr[0].iman)
311	* if (ip) {
312	* status = read(usbsts)
313	* assert status
314	* assert ip
315	* accept (passing status)
316	* }
317	* decline
318	*/
319	static const irq_cmd_t irq_commands[] = {
320	{
321	.cmd = CMD_PIO_READ_32,
322	.dstarg = 3,
323	.addr = NULL /* intr[0].iman */
324	},
325	{
326	.cmd = CMD_AND,
327	.srcarg = 3,
328	.dstarg = 4,
329	.value = 0 /* host2xhci(32, 1) */
330	},
331	{
332	.cmd = CMD_PREDICATE,
333	.srcarg = 4,
334	.value = 5
335	},
336	{
337	.cmd = CMD_PIO_READ_32,
338	.dstarg = 1,
339	.addr = NULL /* usbsts */
340	},
341	{
342	.cmd = CMD_AND,
343	.srcarg = 1,
344	.dstarg = 2,
345	.value = 0 /* host2xhci(32, XHCI_STATUS_ACK_MASK) */
346	},
347	{
348	.cmd = CMD_PIO_WRITE_A_32,
349	.srcarg = 2,
350	.addr = NULL /* usbsts */
351	},
352	{
353	.cmd = CMD_PIO_WRITE_A_32,
354	.srcarg = 3,
355	.addr = NULL /* intr[0].iman */
356	},
357	{
358	.cmd = CMD_ACCEPT
359	},
360	{
361	.cmd = CMD_DECLINE
362	}
363	};
364
365
366	/**
367	* Generates code to accept interrupts. The xHCI is designed primarily for
368	* MSI/MSI-X, but we use PCI Interrupt Pin. In this mode, all the Interrupters
369	* (except 0) are disabled.
370	*/
371	int hc_irq_code_gen(irq_code_t code, xhci_hc_t hc, const hw_res_list_parsed_t hw_res, int irq)
372	{
373	assert(code);
374	assert(hw_res);
375
376	if (hw_res->irqs.count != 1) {
377	usb_log_info("Unexpected HW resources to enable interrupts.");
378	return EINVAL;
379	}
380
381	code->ranges = malloc(sizeof(irq_pio_range_t));
382	if (code->ranges == NULL)
383	return ENOMEM;
384
385	code->cmds = malloc(sizeof(irq_commands));
386	if (code->cmds == NULL) {
387	free(code->ranges);
388	return ENOMEM;
389	}
390
391	code->rangecount = 1;
392	code->ranges[0] = (irq_pio_range_t) {
393	.base = RNGABS(hc->mmio_range),
394	.size = RNGSZ(hc->mmio_range),
395	};
396
397	code->cmdcount = ARRAY_SIZE(irq_commands);
398	memcpy(code->cmds, irq_commands, sizeof(irq_commands));
399
400	void *intr0_iman = RNGABSPTR(hc->mmio_range)
401	+ XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF)
402	+ offsetof(xhci_rt_regs_t, ir[0]);
403	void *usbsts = RNGABSPTR(hc->mmio_range)
404	+ XHCI_REG_RD(hc->cap_regs, XHCI_CAP_LENGTH)
405	+ offsetof(xhci_op_regs_t, usbsts);
406
407	code->cmds[0].addr = intr0_iman;
408	code->cmds[1].value = host2xhci(32, 1);
409	code->cmds[3].addr = usbsts;
410	code->cmds[4].value = host2xhci(32, XHCI_STATUS_ACK_MASK);
411	code->cmds[5].addr = usbsts;
412	code->cmds[6].addr = intr0_iman;
413
414	*irq = hw_res->irqs.irqs[0];
415	return EOK;
416	}
417
418	/**
419	* Claim xHC from BIOS. Implements handoff as per Section 4.22.1 of xHCI spec.
420	*/
421	int hc_claim(xhci_hc_t hc, ddf_dev_t dev)
422	{
423	/* No legacy support capability, the controller is solely for us */
424	if (!hc->legsup)
425	return EOK;
426
427	if (xhci_reg_wait(&hc->op_regs->usbsts, XHCI_REG_MASK(XHCI_OP_CNR), 0))
428	return ETIMEOUT;
429
430	usb_log_debug("LEGSUP: bios: %x, os: %x", hc->legsup->sem_bios, hc->legsup->sem_os);
431	XHCI_REG_SET(hc->legsup, XHCI_LEGSUP_SEM_OS, 1);
432	for (int i = 0; i <= (XHCI_LEGSUP_BIOS_TIMEOUT_US / XHCI_LEGSUP_POLLING_DELAY_1MS); i++) {
433	usb_log_debug("LEGSUP: elapsed: %i ms, bios: %x, os: %x", i,
434	XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_BIOS),
435	XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_OS));
436	if (XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_BIOS) == 0) {
437	return XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_OS) == 1 ? EOK : EIO;
438	}
439	async_usleep(XHCI_LEGSUP_POLLING_DELAY_1MS);
440	}
441	usb_log_error("BIOS did not release XHCI legacy hold!");
442
443	return ENOTSUP;
444	}
445
446	/**
447	* Ask the xHC to reset its state. Implements sequence
448	*/
449	static int hc_reset(xhci_hc_t *hc)
450	{
451	if (xhci_reg_wait(&hc->op_regs->usbsts, XHCI_REG_MASK(XHCI_OP_CNR), 0))
452	return ETIMEOUT;
453
454	/* Stop the HC: set R/S to 0 */
455	XHCI_REG_CLR(hc->op_regs, XHCI_OP_RS, 1);
456
457	/* Wait until the HC is halted - it shall take at most 16 ms */
458	if (xhci_reg_wait(&hc->op_regs->usbsts, XHCI_REG_MASK(XHCI_OP_HCH),
459	XHCI_REG_MASK(XHCI_OP_HCH)))
460	return ETIMEOUT;
461
462	/* Reset */
463	XHCI_REG_SET(hc->op_regs, XHCI_OP_HCRST, 1);
464
465	/* Wait until the reset is complete */
466	if (xhci_reg_wait(&hc->op_regs->usbcmd, XHCI_REG_MASK(XHCI_OP_HCRST), 0))
467	return ETIMEOUT;
468
469	return EOK;
470	}
471
472	/**
473	* Initialize the HC: section 4.2
474	*/
475	int hc_start(xhci_hc_t *hc, bool irq)
476	{
477	int err;
478
479	if ((err = hc_reset(hc)))
480	return err;
481
482	if (xhci_reg_wait(&hc->op_regs->usbsts, XHCI_REG_MASK(XHCI_OP_CNR), 0))
483	return ETIMEOUT;
484
485	uint64_t dcbaaptr = hc->dcbaa_dma.phys;
486	XHCI_REG_WR(hc->op_regs, XHCI_OP_DCBAAP_LO, LOWER32(dcbaaptr));
487	XHCI_REG_WR(hc->op_regs, XHCI_OP_DCBAAP_HI, UPPER32(dcbaaptr));
488	XHCI_REG_WR(hc->op_regs, XHCI_OP_MAX_SLOTS_EN, hc->max_slots);
489
490	uintptr_t crcr;
491	xhci_trb_ring_reset_dequeue_state(&hc->cr.trb_ring, &crcr);
492	XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_LO, LOWER32(crcr));
493	XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_HI, UPPER32(crcr));
494
495	XHCI_REG_SET(hc->op_regs, XHCI_OP_EWE, 1);
496
497	xhci_interrupter_regs_t *intr0 = &hc->rt_regs->ir[0];
498	XHCI_REG_WR(intr0, XHCI_INTR_ERSTSZ, hc->event_ring.segment_count);
499	uint64_t erdp = hc->event_ring.dequeue_ptr;
500	XHCI_REG_WR(intr0, XHCI_INTR_ERDP_LO, LOWER32(erdp));
501	XHCI_REG_WR(intr0, XHCI_INTR_ERDP_HI, UPPER32(erdp));
502	uint64_t erstptr = hc->event_ring.erst.phys;
503	XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA_LO, LOWER32(erstptr));
504	XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA_HI, UPPER32(erstptr));
505
506	if (irq) {
507	XHCI_REG_SET(intr0, XHCI_INTR_IE, 1);
508	XHCI_REG_SET(hc->op_regs, XHCI_OP_INTE, 1);
509	}
510
511	XHCI_REG_SET(hc->op_regs, XHCI_OP_HSEE, 1);
512
513	XHCI_REG_SET(hc->op_regs, XHCI_OP_RS, 1);
514
515	xhci_rh_startup(&hc->rh);
516
517	return EOK;
518	}
519
520	/**
521	* Used only when polling. Shall supplement the irq_commands.
522	*/
523	int hc_status(bus_t bus, uint32_t status)
524	{
525	xhci_hc_t *hc = bus_to_hc(bus);
526	int ip = XHCI_REG_RD(hc->rt_regs->ir, XHCI_INTR_IP);
527	if (ip) {
528	*status = XHCI_REG_RD(hc->op_regs, XHCI_OP_STATUS);
529	XHCI_REG_WR(hc->op_regs, XHCI_OP_STATUS, *status & XHCI_STATUS_ACK_MASK);
530	XHCI_REG_WR(hc->rt_regs->ir, XHCI_INTR_IP, 1);
531
532	/* interrupt handler expects status from irq_commands, which is
533	* in xhci order. */
534	status = host2xhci(32, status);
535	}
536
537	usb_log_debug("Polled status: %x", *status);
538	return EOK;
539	}
540
541	static int xhci_handle_mfindex_wrap_event(xhci_hc_t hc, xhci_trb_t trb)
542	{
543	struct timeval tv;
544	getuptime(&tv);
545	usb_log_debug("Microframe index wrapped (@%lu.%li, %"PRIu64" total).",
546	tv.tv_sec, tv.tv_usec, hc->wrap_count);
547	hc->wrap_time = ((uint64_t) tv.tv_sec) * 1000000 + ((uint64_t) tv.tv_usec);
548	++hc->wrap_count;
549	return EOK;
550	}
551
552	typedef int (event_handler) (xhci_hc_t , xhci_trb_t *trb);
553
554	/**
555	* These events are handled by separate event handling fibril.
556	*/
557	static event_handler event_handlers [] = {
558	[XHCI_TRB_TYPE_TRANSFER_EVENT] = &xhci_handle_transfer_event,
559	};
560
561	/**
562	* These events are handled directly in the interrupt handler, thus they must
563	* not block waiting for another interrupt.
564	*/
565	static event_handler event_handlers_fast [] = {
566	[XHCI_TRB_TYPE_COMMAND_COMPLETION_EVENT] = &xhci_handle_command_completion,
567	[XHCI_TRB_TYPE_MFINDEX_WRAP_EVENT] = &xhci_handle_mfindex_wrap_event,
568	};
569
570	static int hc_handle_event(xhci_hc_t hc, xhci_trb_t trb)
571	{
572	const unsigned type = TRB_TYPE(*trb);
573
574	if (type <= ARRAY_SIZE(event_handlers_fast) && event_handlers_fast[type])
575	return event_handlers_fast[type](hc, trb);
576
577	if (type <= ARRAY_SIZE(event_handlers) && event_handlers[type])
578	return xhci_sw_ring_enqueue(&hc->sw_ring, trb);
579
580	if (type == XHCI_TRB_TYPE_PORT_STATUS_CHANGE_EVENT)
581	return xhci_sw_ring_enqueue(&hc->rh.event_ring, trb);
582
583	return ENOTSUP;
584	}
585
586	static int event_worker(void *arg)
587	{
588	int err;
589	xhci_trb_t trb;
590	xhci_hc_t * const hc = arg;
591	assert(hc);
592
593	while (xhci_sw_ring_dequeue(&hc->sw_ring, &trb) != EINTR) {
594	const unsigned type = TRB_TYPE(trb);
595
596	if ((err = event_handlers[type](hc, &trb)))
597	usb_log_error("Failed to handle event: %s", str_error(err));
598	}
599
600	// TODO: completion_complete
601	fibril_mutex_lock(&hc->event_fibril_completion.guard);
602	hc->event_fibril_completion.active = false;
603	fibril_condvar_broadcast(&hc->event_fibril_completion.cv);
604	fibril_mutex_unlock(&hc->event_fibril_completion.guard);
605
606	return EOK;
607	}
608
609	/**
610	* Dequeue from event ring and handle dequeued events.
611	*
612	* As there can be events, that blocks on waiting for subsequent events,
613	* we solve this problem by first copying the event TRBs from the event ring,
614	* then asserting EHB and only after, handling the events.
615	*
616	* Whenever the event handling blocks, it switches fibril, and incoming
617	* IPC notification will create new event handling fibril for us.
618	*/
619	static void hc_run_event_ring(xhci_hc_t hc, xhci_event_ring_t event_ring,
620	xhci_interrupter_regs_t *intr)
621	{
622	int err;
623
624	xhci_trb_t trb;
625	hc->event_handler = fibril_get_id();
626
627	while ((err = xhci_event_ring_dequeue(event_ring, &trb)) != ENOENT) {
628	if ((err = hc_handle_event(hc, &trb)) != EOK) {
629	usb_log_error("Failed to handle event in interrupt: %s", str_error(err));
630	}
631
632	uint64_t erdp = hc->event_ring.dequeue_ptr;
633	XHCI_REG_WR(intr, XHCI_INTR_ERDP_LO, LOWER32(erdp));
634	XHCI_REG_WR(intr, XHCI_INTR_ERDP_HI, UPPER32(erdp));
635	}
636
637	hc->event_handler = 0;
638
639	/* Update the ERDP to make room in the ring. */
640	uint64_t erdp = hc->event_ring.dequeue_ptr;
641	erdp \|= XHCI_REG_MASK(XHCI_INTR_ERDP_EHB);
642	XHCI_REG_WR(intr, XHCI_INTR_ERDP_LO, LOWER32(erdp));
643	XHCI_REG_WR(intr, XHCI_INTR_ERDP_HI, UPPER32(erdp));
644
645	usb_log_debug2("Event ring run finished.");
646	}
647
648	/**
649	* Handle an interrupt request from xHC. Resolve all situations that trigger an
650	* interrupt separately.
651	*
652	* Note that all RW1C bits in USBSTS register are cleared at the time of
653	* handling the interrupt in irq_code. This method is the top-half.
654	*
655	* @param status contents of USBSTS register at the time of the interrupt.
656	*/
657	void hc_interrupt(bus_t *bus, uint32_t status)
658	{
659	xhci_hc_t *hc = bus_to_hc(bus);
660	status = xhci2host(32, status);
661
662	if (status & XHCI_REG_MASK(XHCI_OP_HSE)) {
663	usb_log_error("Host controller error occured. Bad things gonna happen...");
664	status &= ~XHCI_REG_MASK(XHCI_OP_HSE);
665	}
666
667	if (status & XHCI_REG_MASK(XHCI_OP_EINT)) {
668	usb_log_debug2("Event interrupt, running the event ring.");
669	hc_run_event_ring(hc, &hc->event_ring, &hc->rt_regs->ir[0]);
670	status &= ~XHCI_REG_MASK(XHCI_OP_EINT);
671	}
672
673	if (status & XHCI_REG_MASK(XHCI_OP_SRE)) {
674	usb_log_error("Save/Restore error occured. WTF, "
675	"S/R mechanism not implemented!");
676	status &= ~XHCI_REG_MASK(XHCI_OP_SRE);
677	}
678
679	/* According to Note on p. 302, we may safely ignore the PCD bit. */
680	status &= ~XHCI_REG_MASK(XHCI_OP_PCD);
681
682	if (status) {
683	usb_log_error("Non-zero status after interrupt handling (%08x) "
684	" - missing something?", status);
685	}
686	}
687
688	/**
689	* Tear down all in-memory structures.
690	*/
691	void hc_fini(xhci_hc_t *hc)
692	{
693	xhci_sw_ring_stop(&hc->sw_ring);
694
695	// TODO: completion_wait
696	fibril_mutex_lock(&hc->event_fibril_completion.guard);
697	while (hc->event_fibril_completion.active)
698	fibril_condvar_wait(&hc->event_fibril_completion.cv,
699	&hc->event_fibril_completion.guard);
700	fibril_mutex_unlock(&hc->event_fibril_completion.guard);
701	xhci_sw_ring_fini(&hc->sw_ring);
702
703	xhci_bus_fini(&hc->bus);
704	xhci_event_ring_fini(&hc->event_ring);
705	xhci_scratchpad_free(hc);
706	dma_buffer_free(&hc->dcbaa_dma);
707	xhci_fini_commands(hc);
708	xhci_rh_fini(&hc->rh);
709	pio_disable(hc->reg_base, RNGSZ(hc->mmio_range));
710	usb_log_info("Finalized.");
711	}
712
713	unsigned hc_speed_to_psiv(usb_speed_t speed)
714	{
715	assert(speed < ARRAY_SIZE(usb_speed_to_psiv));
716	return usb_speed_to_psiv[speed];
717	}
718
719	/**
720	* Ring a xHC Doorbell. Implements section 4.7.
721	*/
722	void hc_ring_doorbell(xhci_hc_t *hc, unsigned doorbell, unsigned target)
723	{
724	assert(hc);
725	uint32_t v = host2xhci(32, target & BIT_RRANGE(uint32_t, 7));
726	pio_write_32(&hc->db_arry[doorbell], v);
727	usb_log_debug2("Ringing doorbell %d (target: %d)", doorbell, target);
728	}
729
730	/**
731	* Return an index to device context.
732	*/
733	static uint8_t endpoint_dci(xhci_endpoint_t *ep)
734	{
735	return (2 * ep->base.endpoint) +
736	(ep->base.transfer_type == USB_TRANSFER_CONTROL
737	\|\| ep->base.direction == USB_DIRECTION_IN);
738	}
739
740	void hc_ring_ep_doorbell(xhci_endpoint_t *ep, uint32_t stream_id)
741	{
742	xhci_device_t * const dev = xhci_ep_to_dev(ep);
743	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
744	const uint8_t dci = endpoint_dci(ep);
745	const uint32_t target = (stream_id << 16) \| (dci & 0x1ff);
746	hc_ring_doorbell(hc, dev->slot_id, target);
747	}
748
749	/**
750	* Issue an Enable Slot command. Allocate memory for the slot and fill the
751	* DCBAA with the newly created slot.
752	*/
753	int hc_enable_slot(xhci_device_t *dev)
754	{
755	int err;
756	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
757
758	/* Prepare memory for the context */
759	if ((err = dma_buffer_alloc(&dev->dev_ctx, XHCI_DEVICE_CTX_SIZE(hc))))
760	return err;
761	memset(dev->dev_ctx.virt, 0, XHCI_DEVICE_CTX_SIZE(hc));
762
763	/* Get the slot number */
764	xhci_cmd_t cmd;
765	xhci_cmd_init(&cmd, XHCI_CMD_ENABLE_SLOT);
766
767	err = xhci_cmd_sync(hc, &cmd);
768
769	/* Link them together */
770	if (err == EOK) {
771	dev->slot_id = cmd.slot_id;
772	hc->dcbaa[dev->slot_id] = host2xhci(64, dev->dev_ctx.phys);
773	}
774
775	xhci_cmd_fini(&cmd);
776
777	if (err)
778	dma_buffer_free(&dev->dev_ctx);
779
780	return err;
781	}
782
783	/**
784	* Issue a Disable Slot command for a slot occupied by device.
785	* Frees the device context.
786	*/
787	int hc_disable_slot(xhci_device_t *dev)
788	{
789	int err;
790	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
791
792	if ((err = xhci_cmd_sync_inline(hc, DISABLE_SLOT, .slot_id = dev->slot_id))) {
793	return err;
794	}
795
796	/* Free the device context. */
797	hc->dcbaa[dev->slot_id] = 0;
798	dma_buffer_free(&dev->dev_ctx);
799
800	/* Mark the slot as invalid. */
801	dev->slot_id = 0;
802
803	return EOK;
804	}
805
806	/**
807	* Prepare an empty Endpoint Input Context inside a dma buffer.
808	*/
809	static int create_configure_ep_input_ctx(xhci_device_t dev, dma_buffer_t dma_buf)
810	{
811	const xhci_hc_t * hc = bus_to_hc(dev->base.bus);
812	const int err = dma_buffer_alloc(dma_buf, XHCI_INPUT_CTX_SIZE(hc));
813	if (err)
814	return err;
815
816	xhci_input_ctx_t *ictx = dma_buf->virt;
817	memset(ictx, 0, XHCI_INPUT_CTX_SIZE(hc));
818
819	// Quoting sec. 4.6.5 and 4.6.6: A1, D0, D1 are down (already zeroed), A0 is up.
820	XHCI_INPUT_CTRL_CTX_ADD_SET(*XHCI_GET_CTRL_CTX(ictx, hc), 0);
821	xhci_slot_ctx_t *slot_ctx = XHCI_GET_SLOT_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc);
822	xhci_setup_slot_context(dev, slot_ctx);
823
824	return EOK;
825	}
826
827	/**
828	* Initialize a device, assigning it an address. Implements section 4.3.4.
829	*
830	* @param dev Device to assing an address (unconfigured yet)
831	*/
832	int hc_address_device(xhci_device_t *dev)
833	{
834	int err = ENOMEM;
835	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
836	xhci_endpoint_t *ep0 = xhci_endpoint_get(dev->base.endpoints[0]);
837
838	/* Although we have the precise PSIV value on devices of tier 1,
839	* we have to rely on reverse mapping on others. */
840	if (!usb_speed_to_psiv[dev->base.speed]) {
841	usb_log_error("Device reported an USB speed (%s) that cannot be mapped "
842	"to HC port speed.", usb_str_speed(dev->base.speed));
843	return EINVAL;
844	}
845
846	/* Issue configure endpoint command (sec 4.3.5). */
847	dma_buffer_t ictx_dma_buf;
848	if ((err = create_configure_ep_input_ctx(dev, &ictx_dma_buf)))
849	return err;
850	xhci_input_ctx_t *ictx = ictx_dma_buf.virt;
851
852	/* Copy endpoint 0 context and set A1 flag. */
853	XHCI_INPUT_CTRL_CTX_ADD_SET(*XHCI_GET_CTRL_CTX(ictx, hc), 1);
854	xhci_ep_ctx_t *ep_ctx = XHCI_GET_EP_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc, 1);
855	xhci_setup_endpoint_context(ep0, ep_ctx);
856
857	/* Address device needs Ctx entries set to 1 only */
858	xhci_slot_ctx_t *slot_ctx = XHCI_GET_SLOT_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc);
859	XHCI_SLOT_CTX_ENTRIES_SET(*slot_ctx, 1);
860
861	/* Issue Address Device command. */
862	if ((err = xhci_cmd_sync_inline(hc, ADDRESS_DEVICE,
863	.slot_id = dev->slot_id,
864	.input_ctx = ictx_dma_buf
865	)))
866	return err;
867
868	xhci_device_ctx_t *device_ctx = dev->dev_ctx.virt;
869	dev->base.address = XHCI_SLOT_DEVICE_ADDRESS(*XHCI_GET_SLOT_CTX(device_ctx, hc));
870	usb_log_debug("Obtained USB address: %d.", dev->base.address);
871
872	return EOK;
873	}
874
875	/**
876	* Issue a Configure Device command for a device in slot.
877	*
878	* @param slot_id Slot ID assigned to the device.
879	*/
880	int hc_configure_device(xhci_device_t *dev)
881	{
882	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
883
884	/* Issue configure endpoint command (sec 4.3.5). */
885	dma_buffer_t ictx_dma_buf;
886	const int err = create_configure_ep_input_ctx(dev, &ictx_dma_buf);
887	if (err)
888	return err;
889
890	return xhci_cmd_sync_inline(hc, CONFIGURE_ENDPOINT,
891	.slot_id = dev->slot_id,
892	.input_ctx = ictx_dma_buf
893	);
894	}
895
896	/**
897	* Issue a Deconfigure Device command for a device in slot.
898	*
899	* @param dev The owner of the device
900	*/
901	int hc_deconfigure_device(xhci_device_t *dev)
902	{
903	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
904
905	/* Issue configure endpoint command (sec 4.3.5) with the DC flag. */
906	return xhci_cmd_sync_inline(hc, CONFIGURE_ENDPOINT,
907	.slot_id = dev->slot_id,
908	.deconfigure = true
909	);
910	}
911
912	/**
913	* Instruct xHC to add an endpoint with supplied endpoint context.
914	*
915	* @param dev The owner of the device
916	* @param ep_idx Endpoint DCI in question
917	* @param ep_ctx Endpoint context of the endpoint
918	*/
919	int hc_add_endpoint(xhci_endpoint_t *ep)
920	{
921	xhci_device_t * const dev = xhci_ep_to_dev(ep);
922	const unsigned dci = endpoint_dci(ep);
923
924	/* Issue configure endpoint command (sec 4.3.5). */
925	dma_buffer_t ictx_dma_buf;
926	const int err = create_configure_ep_input_ctx(dev, &ictx_dma_buf);
927	if (err)
928	return err;
929
930	xhci_input_ctx_t *ictx = ictx_dma_buf.virt;
931
932	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
933	XHCI_INPUT_CTRL_CTX_ADD_SET(*XHCI_GET_CTRL_CTX(ictx, hc), dci);
934
935	xhci_ep_ctx_t *ep_ctx = XHCI_GET_EP_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc, dci);
936	xhci_setup_endpoint_context(ep, ep_ctx);
937
938	return xhci_cmd_sync_inline(hc, CONFIGURE_ENDPOINT,
939	.slot_id = dev->slot_id,
940	.input_ctx = ictx_dma_buf
941	);
942	}
943
944	/**
945	* Instruct xHC to drop an endpoint.
946	*
947	* @param dev The owner of the endpoint
948	* @param ep_idx Endpoint DCI in question
949	*/
950	int hc_drop_endpoint(xhci_endpoint_t *ep)
951	{
952	xhci_device_t * const dev = xhci_ep_to_dev(ep);
953	const unsigned dci = endpoint_dci(ep);
954
955	/* Issue configure endpoint command (sec 4.3.5). */
956	dma_buffer_t ictx_dma_buf;
957	const int err = create_configure_ep_input_ctx(dev, &ictx_dma_buf);
958	if (err)
959	return err;
960
961	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
962	xhci_input_ctx_t *ictx = ictx_dma_buf.virt;
963	XHCI_INPUT_CTRL_CTX_DROP_SET(*XHCI_GET_CTRL_CTX(ictx, hc), dci);
964
965	return xhci_cmd_sync_inline(hc, CONFIGURE_ENDPOINT,
966	.slot_id = dev->slot_id,
967	.input_ctx = ictx_dma_buf
968	);
969	}
970
971	/**
972	* Instruct xHC to update information about an endpoint, using supplied
973	* endpoint context.
974	*
975	* @param dev The owner of the endpoint
976	* @param ep_idx Endpoint DCI in question
977	* @param ep_ctx Endpoint context of the endpoint
978	*/
979	int hc_update_endpoint(xhci_endpoint_t *ep)
980	{
981	xhci_device_t * const dev = xhci_ep_to_dev(ep);
982	const unsigned dci = endpoint_dci(ep);
983
984	dma_buffer_t ictx_dma_buf;
985	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
986
987	const int err = dma_buffer_alloc(&ictx_dma_buf, XHCI_INPUT_CTX_SIZE(hc));
988	if (err)
989	return err;
990
991	xhci_input_ctx_t *ictx = ictx_dma_buf.virt;
992	memset(ictx, 0, XHCI_INPUT_CTX_SIZE(hc));
993
994	XHCI_INPUT_CTRL_CTX_ADD_SET(*XHCI_GET_CTRL_CTX(ictx, hc), dci);
995	xhci_ep_ctx_t *ep_ctx = XHCI_GET_EP_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc, dci);
996	xhci_setup_endpoint_context(ep, ep_ctx);
997
998	return xhci_cmd_sync_inline(hc, EVALUATE_CONTEXT,
999	.slot_id = dev->slot_id,
1000	.input_ctx = ictx_dma_buf
1001	);
1002	}
1003
1004	/**
1005	* Instruct xHC to stop running a transfer ring on an endpoint.
1006	*
1007	* @param dev The owner of the endpoint
1008	* @param ep_idx Endpoint DCI in question
1009	*/
1010	int hc_stop_endpoint(xhci_endpoint_t *ep)
1011	{
1012	xhci_device_t * const dev = xhci_ep_to_dev(ep);
1013	const unsigned dci = endpoint_dci(ep);
1014	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
1015	return xhci_cmd_sync_inline(hc, STOP_ENDPOINT,
1016	.slot_id = dev->slot_id,
1017	.endpoint_id = dci
1018	);
1019	}
1020
1021	/**
1022	* Instruct xHC to reset halted endpoint.
1023	*
1024	* @param dev The owner of the endpoint
1025	* @param ep_idx Endpoint DCI in question
1026	*/
1027	int hc_reset_endpoint(xhci_endpoint_t *ep)
1028	{
1029	xhci_device_t * const dev = xhci_ep_to_dev(ep);
1030	const unsigned dci = endpoint_dci(ep);
1031	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
1032	return xhci_cmd_sync_inline(hc, RESET_ENDPOINT,
1033	.slot_id = dev->slot_id,
1034	.endpoint_id = dci
1035	);
1036	}
1037
1038	/**
1039	* Reset a ring position in both software and hardware.
1040	*
1041	* @param dev The owner of the endpoint
1042	*/
1043	int hc_reset_ring(xhci_endpoint_t *ep, uint32_t stream_id)
1044	{
1045	xhci_device_t * const dev = xhci_ep_to_dev(ep);
1046	const unsigned dci = endpoint_dci(ep);
1047	uintptr_t addr;
1048
1049	xhci_trb_ring_t *ring = xhci_endpoint_get_ring(ep, stream_id);
1050	xhci_trb_ring_reset_dequeue_state(ring, &addr);
1051
1052	xhci_hc_t * const hc = bus_to_hc(endpoint_get_bus(&ep->base));
1053	return xhci_cmd_sync_inline(hc, SET_TR_DEQUEUE_POINTER,
1054	.slot_id = dev->slot_id,
1055	.endpoint_id = dci,
1056	.stream_id = stream_id,
1057	.dequeue_ptr = addr,
1058	);
1059	}
1060
1061	/**
1062	* @}
1063	*/

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source: mainline/uspace/drv/bus/usb/xhci/hc.c@ da9d6ca

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