source: mainline/uspace/drv/bus/usb/xhci/endpoint.c@ abb5d08

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since abb5d08 was 682c9354, checked in by Ondřej Hlavatý <aearsis@…>, 8 years ago

xhci: move all real functionality from bus to device/endpoint/transfers
  • Property mode set to 100644
File size: 13.2 KB
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1/*
2 * Copyright (c) 2017 Petr Manek
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbxhci
30 * @{
31 */
32/** @file
33 * @brief The host controller endpoint management.
34 */
35
36#include <usb/host/endpoint.h>
37#include <usb/descriptor.h>
38
39#include <errno.h>
40#include <macros.h>
41#include <str_error.h>
42
43#include "hc.h"
44#include "bus.h"
45#include "commands.h"
46#include "device.h"
47#include "endpoint.h"
48#include "streams.h"
49
50static int alloc_transfer_ds(xhci_endpoint_t *);
51
52/**
53 * Initialize new XHCI endpoint.
54 * @param[in] xhci_ep Allocated XHCI endpoint to initialize.
55 * @param[in] dev Device, to which the endpoint belongs.
56 * @param[in] desc USB endpoint descriptor carrying configuration data.
57 *
58 * @return Error code.
59 */
60static int xhci_endpoint_init(xhci_endpoint_t *xhci_ep, device_t *dev, const usb_endpoint_descriptors_t *desc)
61{
62 int rc;
63 assert(xhci_ep);
64
65 endpoint_t *ep = &xhci_ep->base;
66
67 endpoint_init(ep, dev, desc);
68
69 xhci_ep->max_burst = desc->companion.max_burst + 1;
70
71 if (ep->transfer_type == USB_TRANSFER_BULK)
72 xhci_ep->max_streams = 1 << (USB_SSC_MAX_STREAMS(desc->companion));
73 else
74 xhci_ep->max_streams = 1;
75
76 if (ep->transfer_type == USB_TRANSFER_ISOCHRONOUS)
77 xhci_ep->mult = USB_SSC_MULT(desc->companion) + 1;
78 else
79 xhci_ep->mult = 1;
80
81 /* In USB 3, the semantics of wMaxPacketSize changed. Now the number of
82 * packets per service interval is determined from max_burst and mult.
83 */
84 if (dev->speed >= USB_SPEED_SUPER) {
85 ep->packets_per_uframe = xhci_ep->max_burst * xhci_ep->mult;
86 ep->max_transfer_size = ep->max_packet_size * ep->packets_per_uframe;
87 }
88
89 xhci_ep->interval = desc->endpoint.poll_interval;
90
91 /*
92 * Only Low/Full speed interrupt endpoints have interval as a linear field,
93 * others have 2-based log of it.
94 */
95 if (dev->speed >= USB_SPEED_HIGH || ep->transfer_type != USB_TRANSFER_INTERRUPT) {
96 xhci_ep->interval = 1 << (xhci_ep->interval - 1);
97 }
98
99 /* Full speed devices have interval in frames */
100 if (dev->speed <= USB_SPEED_FULL) {
101 xhci_ep->interval *= 8;
102 }
103
104 if (xhci_ep->base.transfer_type == USB_TRANSFER_ISOCHRONOUS)
105 isoch_init(xhci_ep, desc);
106
107 if ((rc = alloc_transfer_ds(xhci_ep)))
108 goto err;
109
110 return EOK;
111
112err:
113 return rc;
114}
115
116/**
117 * Create a new xHCI endpoint structure.
118 *
119 * Bus callback.
120 */
121endpoint_t *xhci_endpoint_create(device_t *dev, const usb_endpoint_descriptors_t *desc)
122{
123 const usb_transfer_type_t type = USB_ED_GET_TRANSFER_TYPE(desc->endpoint);
124
125 xhci_endpoint_t *ep = calloc(1, sizeof(xhci_endpoint_t)
126 + (type == USB_TRANSFER_ISOCHRONOUS) * sizeof(*ep->isoch));
127 if (!ep)
128 return NULL;
129
130 if (xhci_endpoint_init(ep, dev, desc)) {
131 free(ep);
132 return NULL;
133 }
134
135 return &ep->base;
136}
137
138/**
139 * Finalize XHCI endpoint.
140 * @param[in] xhci_ep XHCI endpoint to finalize.
141 */
142static void xhci_endpoint_fini(xhci_endpoint_t *xhci_ep)
143{
144 assert(xhci_ep);
145
146 xhci_endpoint_free_transfer_ds(xhci_ep);
147
148 // TODO: Something missed?
149}
150
151/**
152 * Destroy given xHCI endpoint structure.
153 *
154 * Bus callback.
155 */
156void xhci_endpoint_destroy(endpoint_t *ep)
157{
158 xhci_endpoint_t *xhci_ep = xhci_endpoint_get(ep);
159
160 xhci_endpoint_fini(xhci_ep);
161 free(xhci_ep);
162}
163
164
165/**
166 * Register an andpoint to the xHC.
167 *
168 * Bus callback.
169 */
170int xhci_endpoint_register(endpoint_t *ep_base)
171{
172 int err;
173 xhci_endpoint_t *ep = xhci_endpoint_get(ep_base);
174 xhci_device_t *dev = xhci_device_get(ep_base->device);
175
176 xhci_ep_ctx_t ep_ctx;
177 xhci_setup_endpoint_context(ep, &ep_ctx);
178
179 if ((err = hc_add_endpoint(dev, xhci_endpoint_index(ep), &ep_ctx)))
180 return err;
181
182 return EOK;
183}
184
185/**
186 * Abort a transfer on an endpoint.
187 */
188static int endpoint_abort(endpoint_t *ep)
189{
190 xhci_device_t *dev = xhci_device_get(ep->device);
191
192 usb_transfer_batch_t *batch = NULL;
193 fibril_mutex_lock(&ep->guard);
194 if (ep->active_batch) {
195 if (dev->slot_id) {
196 const int err = hc_stop_endpoint(dev, xhci_endpoint_dci(xhci_endpoint_get(ep)));
197 if (err) {
198 usb_log_warning("Failed to stop endpoint %u of device " XHCI_DEV_FMT ": %s",
199 ep->endpoint, XHCI_DEV_ARGS(*dev), str_error(err));
200 }
201
202 endpoint_wait_timeout_locked(ep, 2000);
203 }
204
205 batch = ep->active_batch;
206 if (batch) {
207 endpoint_deactivate_locked(ep);
208 }
209 }
210 fibril_mutex_unlock(&ep->guard);
211
212 if (batch) {
213 batch->error = EINTR;
214 batch->transfered_size = 0;
215 usb_transfer_batch_finish(batch);
216 }
217 return EOK;
218}
219
220/**
221 * Unregister an endpoint. If the device is still available, inform the xHC
222 * about it.
223 *
224 * Bus callback.
225 */
226void xhci_endpoint_unregister(endpoint_t *ep_base)
227{
228 int err;
229 xhci_endpoint_t *ep = xhci_endpoint_get(ep_base);
230 xhci_device_t *dev = xhci_device_get(ep_base->device);
231
232 endpoint_abort(ep_base);
233
234 /* If device slot is still available, drop the endpoint. */
235 if (dev->slot_id) {
236
237 if ((err = hc_drop_endpoint(dev, xhci_endpoint_index(ep)))) {
238 usb_log_error("Failed to drop endpoint " XHCI_EP_FMT ": %s", XHCI_EP_ARGS(*ep), str_error(err));
239 }
240 } else {
241 usb_log_debug("Not going to drop endpoint " XHCI_EP_FMT " because"
242 " the slot has already been disabled.", XHCI_EP_ARGS(*ep));
243 }
244}
245
246/**
247 * Determine the type of a XHCI endpoint.
248 * @param[in] ep XHCI endpoint to query.
249 *
250 * @return EP_TYPE_[CONTROL|ISOCH|BULK|INTERRUPT]_[IN|OUT]
251 */
252int xhci_endpoint_type(xhci_endpoint_t *ep)
253{
254 const bool in = ep->base.direction == USB_DIRECTION_IN;
255
256 switch (ep->base.transfer_type) {
257 case USB_TRANSFER_CONTROL:
258 return EP_TYPE_CONTROL;
259
260 case USB_TRANSFER_ISOCHRONOUS:
261 return in ? EP_TYPE_ISOCH_IN
262 : EP_TYPE_ISOCH_OUT;
263
264 case USB_TRANSFER_BULK:
265 return in ? EP_TYPE_BULK_IN
266 : EP_TYPE_BULK_OUT;
267
268 case USB_TRANSFER_INTERRUPT:
269 return in ? EP_TYPE_INTERRUPT_IN
270 : EP_TYPE_INTERRUPT_OUT;
271 }
272
273 return EP_TYPE_INVALID;
274}
275
276/** Allocate transfer data structures for XHCI endpoint not using streams.
277 * @param[in] xhci_ep XHCI endpoint to allocate data structures for.
278 *
279 * @return Error code.
280 */
281static int alloc_transfer_ds(xhci_endpoint_t *xhci_ep)
282{
283 /* Can't use XHCI_EP_FMT because the endpoint may not have device. */
284 usb_log_debug2("Allocating main transfer ring for endpoint " XHCI_EP_FMT, XHCI_EP_ARGS(*xhci_ep));
285
286 xhci_ep->primary_stream_data_array = NULL;
287 xhci_ep->primary_stream_data_size = 0;
288
289 int err;
290 if ((err = xhci_trb_ring_init(&xhci_ep->ring))) {
291 return err;
292 }
293
294 if (xhci_ep->base.transfer_type == USB_TRANSFER_ISOCHRONOUS) {
295 if ((err = isoch_alloc_transfers(xhci_ep))) {
296 xhci_trb_ring_fini(&xhci_ep->ring);
297 return err;
298 }
299 }
300
301 return EOK;
302}
303
304/** Free transfer data structures for XHCI endpoint.
305 * @param[in] xhci_ep XHCI endpoint to free data structures for.
306 */
307void xhci_endpoint_free_transfer_ds(xhci_endpoint_t *xhci_ep)
308{
309 if (xhci_ep->primary_stream_data_size) {
310 xhci_stream_free_ds(xhci_ep);
311 } else {
312 usb_log_debug2("Freeing main transfer ring of endpoint " XHCI_EP_FMT, XHCI_EP_ARGS(*xhci_ep));
313 xhci_trb_ring_fini(&xhci_ep->ring);
314 }
315
316 if (xhci_ep->base.transfer_type == USB_TRANSFER_ISOCHRONOUS)
317 isoch_fini(xhci_ep);
318}
319
320/** See section 4.5.1 of the xHCI spec.
321 */
322uint8_t xhci_endpoint_dci(xhci_endpoint_t *ep)
323{
324 return (2 * ep->base.endpoint) +
325 (ep->base.transfer_type == USB_TRANSFER_CONTROL
326 || ep->base.direction == USB_DIRECTION_IN);
327}
328
329/** Return an index to the endpoint array. The indices are assigned as follows:
330 * 0 EP0 BOTH
331 * 1 EP1 OUT
332 * 2 EP1 IN
333 *
334 * For control endpoints >0, the IN endpoint index is used.
335 *
336 * The index returned must be usually offset by a number of contexts preceding
337 * the endpoint contexts themselves.
338 */
339uint8_t xhci_endpoint_index(xhci_endpoint_t *ep)
340{
341 return xhci_endpoint_dci(ep) - 1;
342}
343
344/** Configure endpoint context of a control endpoint.
345 * @param[in] ep XHCI control endpoint.
346 * @param[in] ctx Endpoint context to configure.
347 */
348static void setup_control_ep_ctx(xhci_endpoint_t *ep, xhci_ep_ctx_t *ctx)
349{
350 XHCI_EP_TYPE_SET(*ctx, xhci_endpoint_type(ep));
351 XHCI_EP_MAX_PACKET_SIZE_SET(*ctx, ep->base.max_packet_size);
352 XHCI_EP_MAX_BURST_SIZE_SET(*ctx, ep->max_burst - 1);
353 XHCI_EP_MULT_SET(*ctx, ep->mult - 1);
354 XHCI_EP_ERROR_COUNT_SET(*ctx, 3);
355 XHCI_EP_TR_DPTR_SET(*ctx, ep->ring.dequeue);
356 XHCI_EP_DCS_SET(*ctx, 1);
357}
358
359/** Configure endpoint context of a bulk endpoint.
360 * @param[in] ep XHCI bulk endpoint.
361 * @param[in] ctx Endpoint context to configure.
362 */
363static void setup_bulk_ep_ctx(xhci_endpoint_t *ep, xhci_ep_ctx_t *ctx)
364{
365 XHCI_EP_TYPE_SET(*ctx, xhci_endpoint_type(ep));
366 XHCI_EP_MAX_PACKET_SIZE_SET(*ctx, ep->base.max_packet_size);
367 XHCI_EP_MAX_BURST_SIZE_SET(*ctx, ep->max_burst - 1);
368 XHCI_EP_ERROR_COUNT_SET(*ctx, 3);
369
370 XHCI_EP_MAX_P_STREAMS_SET(*ctx, 0);
371 XHCI_EP_TR_DPTR_SET(*ctx, ep->ring.dequeue);
372 XHCI_EP_DCS_SET(*ctx, 1);
373}
374
375/** Configure endpoint context of a isochronous endpoint.
376 * @param[in] ep XHCI isochronous endpoint.
377 * @param[in] ctx Endpoint context to configure.
378 */
379static void setup_isoch_ep_ctx(xhci_endpoint_t *ep, xhci_ep_ctx_t *ctx)
380{
381 XHCI_EP_TYPE_SET(*ctx, xhci_endpoint_type(ep));
382 XHCI_EP_MAX_PACKET_SIZE_SET(*ctx, ep->base.max_packet_size & 0x07FF);
383 XHCI_EP_MAX_BURST_SIZE_SET(*ctx, ep->max_burst - 1);
384 XHCI_EP_MULT_SET(*ctx, ep->mult - 1);
385 XHCI_EP_ERROR_COUNT_SET(*ctx, 0);
386 XHCI_EP_TR_DPTR_SET(*ctx, ep->ring.dequeue);
387 XHCI_EP_DCS_SET(*ctx, 1);
388 XHCI_EP_INTERVAL_SET(*ctx, fnzb32(ep->interval) % 32);
389
390 XHCI_EP_MAX_ESIT_PAYLOAD_LO_SET(*ctx, ep->isoch->max_size & 0xFFFF);
391 XHCI_EP_MAX_ESIT_PAYLOAD_HI_SET(*ctx, (ep->isoch->max_size >> 16) & 0xFF);
392}
393
394/** Configure endpoint context of a interrupt endpoint.
395 * @param[in] ep XHCI interrupt endpoint.
396 * @param[in] ctx Endpoint context to configure.
397 */
398static void setup_interrupt_ep_ctx(xhci_endpoint_t *ep, xhci_ep_ctx_t *ctx)
399{
400 XHCI_EP_TYPE_SET(*ctx, xhci_endpoint_type(ep));
401 XHCI_EP_MAX_PACKET_SIZE_SET(*ctx, ep->base.max_packet_size & 0x07FF);
402 XHCI_EP_MAX_BURST_SIZE_SET(*ctx, ep->max_burst - 1);
403 XHCI_EP_MULT_SET(*ctx, 0);
404 XHCI_EP_ERROR_COUNT_SET(*ctx, 3);
405 XHCI_EP_TR_DPTR_SET(*ctx, ep->ring.dequeue);
406 XHCI_EP_DCS_SET(*ctx, 1);
407 XHCI_EP_INTERVAL_SET(*ctx, fnzb32(ep->interval) % 32);
408 // TODO: max ESIT payload
409}
410
411/** Type of endpoint context configuration function. */
412typedef void (*setup_ep_ctx_helper)(xhci_endpoint_t *, xhci_ep_ctx_t *);
413
414/** Static array, which maps USB endpoint types to their respective endpoint context configuration functions. */
415static const setup_ep_ctx_helper setup_ep_ctx_helpers[] = {
416 [USB_TRANSFER_CONTROL] = setup_control_ep_ctx,
417 [USB_TRANSFER_ISOCHRONOUS] = setup_isoch_ep_ctx,
418 [USB_TRANSFER_BULK] = setup_bulk_ep_ctx,
419 [USB_TRANSFER_INTERRUPT] = setup_interrupt_ep_ctx,
420};
421
422/** Configure endpoint context of XHCI endpoint.
423 * @param[in] ep Associated XHCI endpoint.
424 * @param[in] ep_ctx Endpoint context to configure.
425 */
426void xhci_setup_endpoint_context(xhci_endpoint_t *ep, xhci_ep_ctx_t *ep_ctx)
427{
428 assert(ep);
429 assert(ep_ctx);
430
431 usb_transfer_type_t tt = ep->base.transfer_type;
432
433 memset(ep_ctx, 0, sizeof(*ep_ctx));
434 setup_ep_ctx_helpers[tt](ep, ep_ctx);
435}
436
437uint8_t xhci_endpoint_get_state(xhci_endpoint_t *ep)
438{
439 assert(ep);
440
441 xhci_device_t *dev = xhci_device_get(ep->base.device);
442 if (!dev->slot_id)
443 return EP_STATE_DISABLED;
444
445 unsigned idx = xhci_endpoint_index(ep);
446 xhci_device_ctx_t *ctx = dev->dev_ctx.virt;
447 const xhci_hc_t * hc = bus_to_hc(dev->base.bus);
448 xhci_ep_ctx_t *ep_ctx = XHCI_GET_EP_CTX(ctx, hc, idx);
449
450 return XHCI_EP_STATE(*ep_ctx);
451}
452
453/**
454 * Clear endpoint halt condition by resetting the endpoint and skipping the
455 * offending transfer.
456 */
457int xhci_endpoint_clear_halt(xhci_endpoint_t *ep, unsigned stream_id)
458{
459 int err;
460
461 xhci_device_t * const dev = xhci_device_get(ep->base.device);
462 xhci_bus_t * const bus = bus_to_xhci_bus(dev->base.bus);
463 xhci_hc_t * const hc = bus->hc;
464
465 const unsigned slot_id = dev->slot_id;
466 const unsigned dci = xhci_endpoint_dci(ep);
467
468 if ((err = hc_reset_endpoint(dev, dci)))
469 return err;
470
471 uintptr_t addr;
472
473 xhci_trb_ring_reset_dequeue_state(&ep->ring, &addr);
474
475 if ((err = xhci_cmd_sync_inline(hc, SET_TR_DEQUEUE_POINTER,
476 .slot_id = slot_id,
477 .endpoint_id = dci,
478 .stream_id = stream_id,
479 .dequeue_ptr = addr,
480 )))
481 return err;
482
483 return EOK;
484}
485
486/**
487 * @}
488 */
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