[c9c0e41] | 1 | /*
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| 2 | * Copyright (c) 2017 Jaroslav Jindrak
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | /** @addtogroup drvusbxhci
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| 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | * @brief Command sending functions.
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| 34 | */
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| 35 |
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| 36 | #include <errno.h>
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| 37 | #include <str_error.h>
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| 38 | #include <usb/debug.h>
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| 39 | #include "commands.h"
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| 40 | #include "debug.h"
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| 41 | #include "hc.h"
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[8db42f7] | 42 | #include "hw_struct/context.h"
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[c9c0e41] | 43 | #include "hw_struct/trb.h"
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| 44 |
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[e7f21884] | 45 | #define TRB_SET_TSP(trb, tsp) (trb).control |= host2xhci(32, (((tsp) & 0x1) << 9))
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[1b78a7c1] | 46 | #define TRB_SET_TYPE(trb, type) (trb).control |= host2xhci(32, (type) << 10)
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[b724494] | 47 | #define TRB_SET_DC(trb, dc) (trb).control |= host2xhci(32, (dc) << 9)
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[1b78a7c1] | 48 | #define TRB_SET_EP(trb, ep) (trb).control |= host2xhci(32, ((ep) & 0x5) << 16)
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[0cabd10] | 49 | #define TRB_SET_STREAM(trb, st) (trb).control |= host2xhci(32, ((st) & 0xFFFF) << 16)
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[1b78a7c1] | 50 | #define TRB_SET_SUSP(trb, susp) (trb).control |= host2xhci(32, ((susp) & 0x1) << 23)
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| 51 | #define TRB_SET_SLOT(trb, slot) (trb).control |= host2xhci(32, (slot) << 24)
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[60af4cdb] | 52 | #define TRB_SET_DEV_SPEED(trb, speed) (trb).control |= host2xhci(32, (speed & 0xF) << 16)
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[0cabd10] | 53 | #define TRB_SET_DEQUEUE_PTR(trb, dptr) (trb).parameter |= host2xhci(64, (dptr))
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[b80c1ab] | 54 | #define TRB_SET_ICTX(trb, phys) (trb).parameter |= host2xhci(64, (phys) & (~0xF))
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[1b78a7c1] | 55 |
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| 56 | #define TRB_GET_CODE(trb) XHCI_DWORD_EXTRACT((trb).status, 31, 24)
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| 57 | #define TRB_GET_SLOT(trb) XHCI_DWORD_EXTRACT((trb).control, 31, 24)
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| 58 | #define TRB_GET_PHYS(trb) (XHCI_QWORD_EXTRACT((trb).parameter, 63, 4) << 4)
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| 59 |
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[c3d926f3] | 60 | /* Control functions */
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| 61 |
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[889146e] | 62 | static xhci_cmd_ring_t *get_cmd_ring(xhci_hc_t *hc)
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[110d795] | 63 | {
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| 64 | assert(hc);
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[889146e] | 65 | return &hc->cr;
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| 66 | }
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| 67 |
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[eb928c4] | 68 | /**
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| 69 | * Initialize the command subsystem. Allocates the comand ring.
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| 70 | *
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| 71 | * Does not configure the CR pointer to the hardware, because the xHC will be
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| 72 | * reset before starting.
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| 73 | */
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[889146e] | 74 | int xhci_init_commands(xhci_hc_t *hc)
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| 75 | {
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| 76 | xhci_cmd_ring_t *cr = get_cmd_ring(hc);
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| 77 | int err;
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| 78 |
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[998773d] | 79 | if ((err = xhci_trb_ring_init(&cr->trb_ring, 0)))
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[889146e] | 80 | return err;
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[110d795] | 81 |
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[889146e] | 82 | fibril_mutex_initialize(&cr->guard);
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| 83 | fibril_condvar_initialize(&cr->state_cv);
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| 84 | fibril_condvar_initialize(&cr->stopped_cv);
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[74b852b] | 85 |
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[889146e] | 86 | list_initialize(&cr->cmd_list);
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| 87 |
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| 88 | cr->state = XHCI_CR_STATE_OPEN;
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[74b852b] | 89 |
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[110d795] | 90 | return EOK;
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| 91 | }
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| 92 |
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[eb928c4] | 93 | /**
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| 94 | * Finish the command subsystem. Stops the hardware from running commands, then
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| 95 | * deallocates the ring.
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| 96 | */
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[c46c356] | 97 | void xhci_fini_commands(xhci_hc_t *hc)
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| 98 | {
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| 99 | assert(hc);
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[eb928c4] | 100 | xhci_stop_command_ring(hc);
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| 101 |
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| 102 | xhci_cmd_ring_t *cr = get_cmd_ring(hc);
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| 103 |
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| 104 | fibril_mutex_lock(&cr->guard);
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| 105 | xhci_trb_ring_fini(&cr->trb_ring);
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| 106 | fibril_mutex_unlock(&cr->guard);
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[c46c356] | 107 | }
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| 108 |
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[eb928c4] | 109 | /**
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| 110 | * Initialize a command structure for the given command.
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| 111 | */
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[c3d926f3] | 112 | void xhci_cmd_init(xhci_cmd_t *cmd, xhci_cmd_type_t type)
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[110d795] | 113 | {
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[c3d926f3] | 114 | memset(cmd, 0, sizeof(*cmd));
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[110d795] | 115 |
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[c3d926f3] | 116 | link_initialize(&cmd->_header.link);
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[110d795] | 117 |
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[c3d926f3] | 118 | fibril_mutex_initialize(&cmd->_header.completed_mtx);
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| 119 | fibril_condvar_initialize(&cmd->_header.completed_cv);
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[04df063] | 120 |
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[c3d926f3] | 121 | cmd->_header.cmd = type;
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[4688350b] | 122 | }
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| 123 |
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[eb928c4] | 124 | /**
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| 125 | * Finish the command structure. Some command invocation includes allocating
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| 126 | * a context structure. To have the convenience in calling commands, this
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| 127 | * method deallocates all resources.
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| 128 | */
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[c3d926f3] | 129 | void xhci_cmd_fini(xhci_cmd_t *cmd)
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[4688350b] | 130 | {
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[c3d926f3] | 131 | list_remove(&cmd->_header.link);
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[110d795] | 132 |
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[b80c1ab] | 133 | dma_buffer_free(&cmd->input_ctx);
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| 134 | dma_buffer_free(&cmd->bandwidth_ctx);
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[9304b66] | 135 |
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[c3d926f3] | 136 | if (cmd->_header.async) {
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| 137 | free(cmd);
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| 138 | }
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[110d795] | 139 | }
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| 140 |
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[eb928c4] | 141 | /**
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| 142 | * Find a command issued by TRB at @c phys inside the command list.
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| 143 | *
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| 144 | * Call with guard locked only.
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| 145 | */
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[889146e] | 146 | static inline xhci_cmd_t *find_command(xhci_hc_t *hc, uint64_t phys)
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[110d795] | 147 | {
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[889146e] | 148 | xhci_cmd_ring_t *cr = get_cmd_ring(hc);
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| 149 | assert(fibril_mutex_is_locked(&cr->guard));
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[74b852b] | 150 |
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[889146e] | 151 | link_t *cmd_link = list_first(&cr->cmd_list);
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[110d795] | 152 |
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[2fa43d1] | 153 | while (cmd_link != NULL) {
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[c3d926f3] | 154 | xhci_cmd_t *cmd = list_get_instance(cmd_link, xhci_cmd_t, _header.link);
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[2fa43d1] | 155 |
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[c3d926f3] | 156 | if (cmd->_header.trb_phys == phys)
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[2fa43d1] | 157 | break;
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| 158 |
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[889146e] | 159 | cmd_link = list_next(cmd_link, &cr->cmd_list);
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[2fa43d1] | 160 | }
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| 161 |
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[889146e] | 162 | return cmd_link ? list_get_instance(cmd_link, xhci_cmd_t, _header.link)
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| 163 | : NULL;
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[110d795] | 164 | }
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| 165 |
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[d2c3dcd] | 166 | static void cr_set_state(xhci_cmd_ring_t *cr, xhci_cr_state_t state)
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| 167 | {
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| 168 | assert(fibril_mutex_is_locked(&cr->guard));
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| 169 |
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| 170 | cr->state = state;
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| 171 | if (state == XHCI_CR_STATE_OPEN
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| 172 | || state == XHCI_CR_STATE_CLOSED)
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| 173 | fibril_condvar_broadcast(&cr->state_cv);
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| 174 | }
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| 175 |
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| 176 | static int wait_for_ring_open(xhci_cmd_ring_t *cr)
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| 177 | {
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| 178 | assert(fibril_mutex_is_locked(&cr->guard));
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| 179 |
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| 180 | while (true) {
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| 181 | switch (cr->state) {
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| 182 | case XHCI_CR_STATE_CHANGING:
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| 183 | case XHCI_CR_STATE_FULL:
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| 184 | fibril_condvar_wait(&cr->state_cv, &cr->guard);
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| 185 | break;
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| 186 | case XHCI_CR_STATE_OPEN:
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| 187 | return EOK;
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| 188 | case XHCI_CR_STATE_CLOSED:
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| 189 | return ENAK;
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| 190 | }
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| 191 | }
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| 192 | }
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| 193 |
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[eb928c4] | 194 | /**
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| 195 | * Enqueue a command on the TRB ring. Ring the doorbell to initiate processing.
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| 196 | * Register the command as waiting for completion inside the command list.
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| 197 | */
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| 198 | static inline int enqueue_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
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[481af21e] | 199 | {
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[889146e] | 200 | xhci_cmd_ring_t *cr = get_cmd_ring(hc);
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[548c123] | 201 | assert(cmd);
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| 202 |
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[889146e] | 203 | fibril_mutex_lock(&cr->guard);
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[c058a388] | 204 |
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[d2c3dcd] | 205 | if (wait_for_ring_open(cr)) {
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[889146e] | 206 | fibril_mutex_unlock(&cr->guard);
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| 207 | return ENAK;
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| 208 | }
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| 209 |
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[837581fd] | 210 | usb_log_debug("Sending command %s", xhci_trb_str_type(TRB_TYPE(cmd->_header.trb)));
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[481af21e] | 211 |
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[889146e] | 212 | list_append(&cmd->_header.link, &cr->cmd_list);
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| 213 |
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[d2c3dcd] | 214 | int err = EOK;
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| 215 | while (err == EOK) {
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| 216 | err = xhci_trb_ring_enqueue(&cr->trb_ring,
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| 217 | &cmd->_header.trb, &cmd->_header.trb_phys);
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| 218 | if (err != EAGAIN)
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| 219 | break;
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| 220 |
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| 221 | cr_set_state(cr, XHCI_CR_STATE_FULL);
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| 222 | err = wait_for_ring_open(cr);
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| 223 | }
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| 224 |
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| 225 | if (err == EOK)
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| 226 | hc_ring_doorbell(hc, 0, 0);
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[889146e] | 227 |
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| 228 | fibril_mutex_unlock(&cr->guard);
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| 229 |
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[d2c3dcd] | 230 | return err;
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[481af21e] | 231 | }
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| 232 |
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[eb928c4] | 233 | /**
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| 234 | * Stop the command ring. Stop processing commands, block issuing new ones.
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| 235 | * Wait until hardware acknowledges it is stopped.
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| 236 | */
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[3dc519f] | 237 | void xhci_stop_command_ring(xhci_hc_t *hc)
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| 238 | {
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[889146e] | 239 | xhci_cmd_ring_t *cr = get_cmd_ring(hc);
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[3dc519f] | 240 |
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[889146e] | 241 | fibril_mutex_lock(&cr->guard);
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[3dc519f] | 242 |
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[889146e] | 243 | // Prevent others from starting CR again.
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[d2c3dcd] | 244 | cr_set_state(cr, XHCI_CR_STATE_CLOSED);
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[3dc519f] | 245 |
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[8033f89] | 246 | /* Some systems, inc. QEMU, need whole 64-bit qword to be written */
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[889146e] | 247 | XHCI_REG_SET(hc->op_regs, XHCI_OP_CS, 1);
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[8033f89] | 248 | XHCI_REG_SET(hc->op_regs, XHCI_OP_CRCR_HI, 0);
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[3dc519f] | 249 |
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[889146e] | 250 | while (XHCI_REG_RD(hc->op_regs, XHCI_OP_CRR))
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| 251 | fibril_condvar_wait(&cr->stopped_cv, &cr->guard);
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| 252 |
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| 253 | fibril_mutex_unlock(&cr->guard);
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[3dc519f] | 254 | }
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| 255 |
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[eb928c4] | 256 | /**
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| 257 | * Abort currently processed command. Note that it is only aborted when the
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| 258 | * command is "blocking" - see section 4.6.1.2 of xHCI spec.
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| 259 | */
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[889146e] | 260 | static void abort_command_ring(xhci_hc_t *hc)
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[3dc519f] | 261 | {
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[8033f89] | 262 | /* Some systems, inc. QEMU, need whole 64-bit qword to be written */
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| 263 | XHCI_REG_SET(hc->op_regs, XHCI_OP_CA, 1);
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| 264 | XHCI_REG_SET(hc->op_regs, XHCI_OP_CRCR_HI, 0);
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[3dc519f] | 265 | }
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| 266 |
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[4fa5342] | 267 | static const char *trb_codes [] = {
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| 268 | #define TRBC(t) [XHCI_TRBC_##t] = #t
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| 269 | TRBC(INVALID),
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| 270 | TRBC(SUCCESS),
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| 271 | TRBC(DATA_BUFFER_ERROR),
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| 272 | TRBC(BABBLE_DETECTED_ERROR),
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| 273 | TRBC(USB_TRANSACTION_ERROR),
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| 274 | TRBC(TRB_ERROR),
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| 275 | TRBC(STALL_ERROR),
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| 276 | TRBC(RESOURCE_ERROR),
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| 277 | TRBC(BANDWIDTH_ERROR),
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| 278 | TRBC(NO_SLOTS_ERROR),
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| 279 | TRBC(INVALID_STREAM_ERROR),
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| 280 | TRBC(SLOT_NOT_ENABLED_ERROR),
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| 281 | TRBC(EP_NOT_ENABLED_ERROR),
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| 282 | TRBC(SHORT_PACKET),
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| 283 | TRBC(RING_UNDERRUN),
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| 284 | TRBC(RING_OVERRUN),
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| 285 | TRBC(VF_EVENT_RING_FULL),
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| 286 | TRBC(PARAMETER_ERROR),
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| 287 | TRBC(BANDWIDTH_OVERRUN_ERROR),
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| 288 | TRBC(CONTEXT_STATE_ERROR),
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| 289 | TRBC(NO_PING_RESPONSE_ERROR),
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| 290 | TRBC(EVENT_RING_FULL_ERROR),
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| 291 | TRBC(INCOMPATIBLE_DEVICE_ERROR),
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| 292 | TRBC(MISSED_SERVICE_ERROR),
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| 293 | TRBC(COMMAND_RING_STOPPED),
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| 294 | TRBC(COMMAND_ABORTED),
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| 295 | TRBC(STOPPED),
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| 296 | TRBC(STOPPED_LENGTH_INVALID),
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| 297 | TRBC(STOPPED_SHORT_PACKET),
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| 298 | TRBC(MAX_EXIT_LATENCY_TOO_LARGE_ERROR),
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| 299 | [30] = "<reserved>",
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| 300 | TRBC(ISOCH_BUFFER_OVERRUN),
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| 301 | TRBC(EVENT_LOST_ERROR),
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| 302 | TRBC(UNDEFINED_ERROR),
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| 303 | TRBC(INVALID_STREAM_ID_ERROR),
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| 304 | TRBC(SECONDARY_BANDWIDTH_ERROR),
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| 305 | TRBC(SPLIT_TRANSACTION_ERROR),
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| 306 | [XHCI_TRBC_MAX] = NULL
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| 307 | #undef TRBC
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| 308 | };
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| 309 |
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[eb928c4] | 310 | /**
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| 311 | * Report an error according to command completion code.
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| 312 | */
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[4fa5342] | 313 | static void report_error(int code)
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| 314 | {
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| 315 | if (code < XHCI_TRBC_MAX && trb_codes[code] != NULL)
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| 316 | usb_log_error("Command resulted in error: %s.", trb_codes[code]);
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| 317 | else
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| 318 | usb_log_error("Command resulted in reserved or vendor specific error.");
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| 319 | }
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| 320 |
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[eb928c4] | 321 | /**
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| 322 | * Handle a command completion. Feed the fibril waiting for result.
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| 323 | *
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| 324 | * @param trb The COMMAND_COMPLETION TRB found in event ring.
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| 325 | */
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[c3d926f3] | 326 | int xhci_handle_command_completion(xhci_hc_t *hc, xhci_trb_t *trb)
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[c9c0e41] | 327 | {
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[889146e] | 328 | xhci_cmd_ring_t *cr = get_cmd_ring(hc);
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[c3d926f3] | 329 | assert(trb);
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| 330 |
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[889146e] | 331 | fibril_mutex_lock(&cr->guard);
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| 332 |
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| 333 | int code = TRB_GET_CODE(*trb);
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| 334 |
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| 335 | if (code == XHCI_TRBC_COMMAND_RING_STOPPED) {
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| 336 | /* This can either mean that the ring is being stopped, or
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| 337 | * a command was aborted. In either way, wake threads waiting
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| 338 | * on stopped_cv.
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| 339 | *
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| 340 | * Note that we need to hold mutex, because we must be sure the
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| 341 | * requesting thread is waiting inside the CV.
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| 342 | */
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[defaab2] | 343 | usb_log_debug("Command ring stopped.");
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[889146e] | 344 | fibril_condvar_broadcast(&cr->stopped_cv);
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| 345 | fibril_mutex_unlock(&cr->guard);
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| 346 | return EOK;
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| 347 | }
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| 348 |
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[d2c3dcd] | 349 | const uint64_t phys = TRB_GET_PHYS(*trb);
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| 350 | xhci_trb_ring_update_dequeue(&cr->trb_ring, phys);
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| 351 |
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| 352 | if (cr->state == XHCI_CR_STATE_FULL)
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| 353 | cr_set_state(cr, XHCI_CR_STATE_OPEN);
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| 354 |
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[889146e] | 355 | xhci_cmd_t *command = find_command(hc, phys);
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[c3d926f3] | 356 | if (command == NULL) {
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[837581fd] | 357 | usb_log_error("No command struct for completion event found.");
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[c3d926f3] | 358 |
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| 359 | if (code != XHCI_TRBC_SUCCESS)
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| 360 | report_error(code);
|
---|
| 361 |
|
---|
| 362 | return EOK;
|
---|
| 363 | }
|
---|
[c058a388] | 364 |
|
---|
[889146e] | 365 | list_remove(&command->_header.link);
|
---|
| 366 |
|
---|
[3cbc138] | 367 | /* Semantics of NO_OP_CMD is that success is marked as a TRB error. */
|
---|
| 368 | if (command->_header.cmd == XHCI_CMD_NO_OP && code == XHCI_TRBC_TRB_ERROR)
|
---|
| 369 | code = XHCI_TRBC_SUCCESS;
|
---|
| 370 |
|
---|
[c3d926f3] | 371 | command->status = code;
|
---|
| 372 | command->slot_id = TRB_GET_SLOT(*trb);
|
---|
[c9c0e41] | 373 |
|
---|
[8033f89] | 374 | usb_log_debug("Completed command %s",
|
---|
| 375 | xhci_trb_str_type(TRB_TYPE(command->_header.trb)));
|
---|
[3cbc138] | 376 |
|
---|
| 377 | if (code != XHCI_TRBC_SUCCESS) {
|
---|
| 378 | report_error(code);
|
---|
| 379 | xhci_dump_trb(&command->_header.trb);
|
---|
[c3d926f3] | 380 | }
|
---|
| 381 |
|
---|
[889146e] | 382 | fibril_mutex_unlock(&cr->guard);
|
---|
| 383 |
|
---|
[c3d926f3] | 384 | fibril_mutex_lock(&command->_header.completed_mtx);
|
---|
| 385 | command->_header.completed = true;
|
---|
| 386 | fibril_condvar_broadcast(&command->_header.completed_cv);
|
---|
| 387 | fibril_mutex_unlock(&command->_header.completed_mtx);
|
---|
| 388 |
|
---|
| 389 | if (command->_header.async) {
|
---|
| 390 | /* Free the command and other DS upon completion. */
|
---|
| 391 | xhci_cmd_fini(command);
|
---|
| 392 | }
|
---|
| 393 |
|
---|
| 394 | return EOK;
|
---|
| 395 | }
|
---|
| 396 |
|
---|
| 397 | /* Command-issuing functions */
|
---|
| 398 |
|
---|
| 399 | static int no_op_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
| 400 | {
|
---|
| 401 | assert(hc);
|
---|
| 402 |
|
---|
| 403 | xhci_trb_clean(&cmd->_header.trb);
|
---|
| 404 |
|
---|
| 405 | TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_NO_OP_CMD);
|
---|
[110d795] | 406 |
|
---|
[eb928c4] | 407 | return enqueue_command(hc, cmd);
|
---|
[c9c0e41] | 408 | }
|
---|
| 409 |
|
---|
[c3d926f3] | 410 | static int enable_slot_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
[c9c0e41] | 411 | {
|
---|
[c058a388] | 412 | assert(hc);
|
---|
| 413 |
|
---|
[c3d926f3] | 414 | xhci_trb_clean(&cmd->_header.trb);
|
---|
[c9c0e41] | 415 |
|
---|
[c3d926f3] | 416 | TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_ENABLE_SLOT_CMD);
|
---|
[8033f89] | 417 | cmd->_header.trb.control |=
|
---|
| 418 | host2xhci(32, XHCI_REG_RD(hc->xecp, XHCI_EC_SP_SLOT_TYPE) << 16);
|
---|
[110d795] | 419 |
|
---|
[eb928c4] | 420 | return enqueue_command(hc, cmd);
|
---|
[5ac5eb1] | 421 | }
|
---|
| 422 |
|
---|
[c3d926f3] | 423 | static int disable_slot_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
[5ac5eb1] | 424 | {
|
---|
[c058a388] | 425 | assert(hc);
|
---|
[110d795] | 426 | assert(cmd);
|
---|
[c058a388] | 427 |
|
---|
[c3d926f3] | 428 | xhci_trb_clean(&cmd->_header.trb);
|
---|
[5ac5eb1] | 429 |
|
---|
[c3d926f3] | 430 | TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_DISABLE_SLOT_CMD);
|
---|
| 431 | TRB_SET_SLOT(cmd->_header.trb, cmd->slot_id);
|
---|
[110d795] | 432 |
|
---|
[eb928c4] | 433 | return enqueue_command(hc, cmd);
|
---|
[c9c0e41] | 434 | }
|
---|
| 435 |
|
---|
[c3d926f3] | 436 | static int address_device_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
[8db42f7] | 437 | {
|
---|
[c058a388] | 438 | assert(hc);
|
---|
[110d795] | 439 | assert(cmd);
|
---|
[b80c1ab] | 440 | assert(dma_buffer_is_set(&cmd->input_ctx));
|
---|
[c058a388] | 441 |
|
---|
[8db42f7] | 442 | /**
|
---|
| 443 | * TODO: Requirements for this command:
|
---|
| 444 | * dcbaa[slot_id] is properly sized and initialized
|
---|
| 445 | * ictx has valids slot context and endpoint 0, all
|
---|
| 446 | * other should be ignored at this point (see section 4.6.5).
|
---|
| 447 | */
|
---|
[04df063] | 448 |
|
---|
[c3d926f3] | 449 | xhci_trb_clean(&cmd->_header.trb);
|
---|
[8db42f7] | 450 |
|
---|
[b80c1ab] | 451 | TRB_SET_ICTX(cmd->_header.trb, cmd->input_ctx.phys);
|
---|
[8db42f7] | 452 |
|
---|
| 453 | /**
|
---|
| 454 | * Note: According to section 6.4.3.4, we can set the 9th bit
|
---|
| 455 | * of the control field of the trb (BSR) to 1 and then the xHC
|
---|
| 456 | * will not issue the SET_ADDRESS request to the USB device.
|
---|
| 457 | * This can be used to provide compatibility with legacy USB devices
|
---|
| 458 | * that require their device descriptor to be read before such request.
|
---|
| 459 | */
|
---|
[c3d926f3] | 460 | TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_ADDRESS_DEVICE_CMD);
|
---|
| 461 | TRB_SET_SLOT(cmd->_header.trb, cmd->slot_id);
|
---|
[8db42f7] | 462 |
|
---|
[eb928c4] | 463 | return enqueue_command(hc, cmd);
|
---|
[8db42f7] | 464 | }
|
---|
| 465 |
|
---|
[c3d926f3] | 466 | static int configure_endpoint_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
[665bf3c] | 467 | {
|
---|
[c058a388] | 468 | assert(hc);
|
---|
[110d795] | 469 | assert(cmd);
|
---|
[c058a388] | 470 |
|
---|
[c3d926f3] | 471 | xhci_trb_clean(&cmd->_header.trb);
|
---|
[665bf3c] | 472 |
|
---|
[b724494] | 473 | if (!cmd->deconfigure) {
|
---|
| 474 | /* If the DC flag is on, input context is not evaluated. */
|
---|
[b80c1ab] | 475 | assert(dma_buffer_is_set(&cmd->input_ctx));
|
---|
[b724494] | 476 |
|
---|
[b80c1ab] | 477 | TRB_SET_ICTX(cmd->_header.trb, cmd->input_ctx.phys);
|
---|
[b724494] | 478 | }
|
---|
[110d795] | 479 |
|
---|
[c3d926f3] | 480 | TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_CONFIGURE_ENDPOINT_CMD);
|
---|
| 481 | TRB_SET_SLOT(cmd->_header.trb, cmd->slot_id);
|
---|
| 482 | TRB_SET_DC(cmd->_header.trb, cmd->deconfigure);
|
---|
[665bf3c] | 483 |
|
---|
[eb928c4] | 484 | return enqueue_command(hc, cmd);
|
---|
[665bf3c] | 485 | }
|
---|
| 486 |
|
---|
[c3d926f3] | 487 | static int evaluate_context_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
[c9ce62ae] | 488 | {
|
---|
[c058a388] | 489 | assert(hc);
|
---|
[110d795] | 490 | assert(cmd);
|
---|
[b80c1ab] | 491 | assert(dma_buffer_is_set(&cmd->input_ctx));
|
---|
[c058a388] | 492 |
|
---|
[c9ce62ae] | 493 | /**
|
---|
| 494 | * Note: All Drop Context flags of the input context shall be 0,
|
---|
| 495 | * all Add Context flags shall be initialize to indicate IDs
|
---|
| 496 | * of the contexts affected by the command.
|
---|
| 497 | * Refer to sections 6.2.2.3 and 6.3.3.3 for further info.
|
---|
| 498 | */
|
---|
[c3d926f3] | 499 | xhci_trb_clean(&cmd->_header.trb);
|
---|
[c9ce62ae] | 500 |
|
---|
[b80c1ab] | 501 | TRB_SET_ICTX(cmd->_header.trb, cmd->input_ctx.phys);
|
---|
[c9ce62ae] | 502 |
|
---|
[c3d926f3] | 503 | TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_EVALUATE_CONTEXT_CMD);
|
---|
| 504 | TRB_SET_SLOT(cmd->_header.trb, cmd->slot_id);
|
---|
[110d795] | 505 |
|
---|
[eb928c4] | 506 | return enqueue_command(hc, cmd);
|
---|
[c9ce62ae] | 507 | }
|
---|
| 508 |
|
---|
[c3d926f3] | 509 | static int reset_endpoint_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
[05aeee0e] | 510 | {
|
---|
[c058a388] | 511 | assert(hc);
|
---|
[110d795] | 512 | assert(cmd);
|
---|
[c058a388] | 513 |
|
---|
[c3d926f3] | 514 | xhci_trb_clean(&cmd->_header.trb);
|
---|
[05aeee0e] | 515 |
|
---|
[c3d926f3] | 516 | TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_RESET_ENDPOINT_CMD);
|
---|
[e7f21884] | 517 | TRB_SET_TSP(cmd->_header.trb, cmd->tsp);
|
---|
[c3d926f3] | 518 | TRB_SET_EP(cmd->_header.trb, cmd->endpoint_id);
|
---|
| 519 | TRB_SET_SLOT(cmd->_header.trb, cmd->slot_id);
|
---|
[c9bec1c] | 520 |
|
---|
[eb928c4] | 521 | return enqueue_command(hc, cmd);
|
---|
[05aeee0e] | 522 | }
|
---|
| 523 |
|
---|
[c3d926f3] | 524 | static int stop_endpoint_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
[05aeee0e] | 525 | {
|
---|
[c058a388] | 526 | assert(hc);
|
---|
[110d795] | 527 | assert(cmd);
|
---|
[c058a388] | 528 |
|
---|
[c3d926f3] | 529 | xhci_trb_clean(&cmd->_header.trb);
|
---|
[110d795] | 530 |
|
---|
[c3d926f3] | 531 | TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_STOP_ENDPOINT_CMD);
|
---|
| 532 | TRB_SET_EP(cmd->_header.trb, cmd->endpoint_id);
|
---|
| 533 | TRB_SET_SUSP(cmd->_header.trb, cmd->susp);
|
---|
| 534 | TRB_SET_SLOT(cmd->_header.trb, cmd->slot_id);
|
---|
[05aeee0e] | 535 |
|
---|
[eb928c4] | 536 | return enqueue_command(hc, cmd);
|
---|
[c058a388] | 537 | }
|
---|
[05aeee0e] | 538 |
|
---|
[c3d926f3] | 539 | static int set_tr_dequeue_pointer_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
[0cabd10] | 540 | {
|
---|
| 541 | assert(hc);
|
---|
| 542 | assert(cmd);
|
---|
| 543 |
|
---|
[c3d926f3] | 544 | xhci_trb_clean(&cmd->_header.trb);
|
---|
[0cabd10] | 545 |
|
---|
[c3d926f3] | 546 | TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_SET_TR_DEQUEUE_POINTER_CMD);
|
---|
| 547 | TRB_SET_EP(cmd->_header.trb, cmd->endpoint_id);
|
---|
| 548 | TRB_SET_STREAM(cmd->_header.trb, cmd->stream_id);
|
---|
| 549 | TRB_SET_SLOT(cmd->_header.trb, cmd->slot_id);
|
---|
| 550 | TRB_SET_DEQUEUE_PTR(cmd->_header.trb, cmd->dequeue_ptr);
|
---|
[0cabd10] | 551 |
|
---|
[eb928c4] | 552 | return enqueue_command(hc, cmd);
|
---|
[0cabd10] | 553 | }
|
---|
| 554 |
|
---|
[c3d926f3] | 555 | static int reset_device_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
[c058a388] | 556 | {
|
---|
| 557 | assert(hc);
|
---|
[110d795] | 558 | assert(cmd);
|
---|
[c058a388] | 559 |
|
---|
[c3d926f3] | 560 | xhci_trb_clean(&cmd->_header.trb);
|
---|
[c058a388] | 561 |
|
---|
[c3d926f3] | 562 | TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_RESET_DEVICE_CMD);
|
---|
| 563 | TRB_SET_SLOT(cmd->_header.trb, cmd->slot_id);
|
---|
[c9bec1c] | 564 |
|
---|
[eb928c4] | 565 | return enqueue_command(hc, cmd);
|
---|
[05aeee0e] | 566 | }
|
---|
| 567 |
|
---|
[c3d926f3] | 568 | static int get_port_bandwidth_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
[60af4cdb] | 569 | {
|
---|
| 570 | assert(hc);
|
---|
| 571 | assert(cmd);
|
---|
| 572 |
|
---|
[c3d926f3] | 573 | xhci_trb_clean(&cmd->_header.trb);
|
---|
[60af4cdb] | 574 |
|
---|
[b80c1ab] | 575 | TRB_SET_ICTX(cmd->_header.trb, cmd->bandwidth_ctx.phys);
|
---|
[60af4cdb] | 576 |
|
---|
[c3d926f3] | 577 | TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_GET_PORT_BANDWIDTH_CMD);
|
---|
| 578 | TRB_SET_SLOT(cmd->_header.trb, cmd->slot_id);
|
---|
| 579 | TRB_SET_DEV_SPEED(cmd->_header.trb, cmd->device_speed);
|
---|
[60af4cdb] | 580 |
|
---|
[eb928c4] | 581 | return enqueue_command(hc, cmd);
|
---|
[60af4cdb] | 582 | }
|
---|
| 583 |
|
---|
[c3d926f3] | 584 | /* The table of command-issuing functions. */
|
---|
| 585 |
|
---|
| 586 | typedef int (*cmd_handler) (xhci_hc_t *hc, xhci_cmd_t *cmd);
|
---|
| 587 |
|
---|
| 588 | static cmd_handler cmd_handlers [] = {
|
---|
| 589 | [XHCI_CMD_ENABLE_SLOT] = enable_slot_cmd,
|
---|
| 590 | [XHCI_CMD_DISABLE_SLOT] = disable_slot_cmd,
|
---|
| 591 | [XHCI_CMD_ADDRESS_DEVICE] = address_device_cmd,
|
---|
| 592 | [XHCI_CMD_CONFIGURE_ENDPOINT] = configure_endpoint_cmd,
|
---|
| 593 | [XHCI_CMD_EVALUATE_CONTEXT] = evaluate_context_cmd,
|
---|
| 594 | [XHCI_CMD_RESET_ENDPOINT] = reset_endpoint_cmd,
|
---|
| 595 | [XHCI_CMD_STOP_ENDPOINT] = stop_endpoint_cmd,
|
---|
| 596 | [XHCI_CMD_SET_TR_DEQUEUE_POINTER] = set_tr_dequeue_pointer_cmd,
|
---|
| 597 | [XHCI_CMD_RESET_DEVICE] = reset_device_cmd,
|
---|
| 598 | [XHCI_CMD_FORCE_EVENT] = NULL,
|
---|
| 599 | [XHCI_CMD_NEGOTIATE_BANDWIDTH] = NULL,
|
---|
| 600 | [XHCI_CMD_SET_LATENCY_TOLERANCE_VALUE] = NULL,
|
---|
| 601 | [XHCI_CMD_GET_PORT_BANDWIDTH] = get_port_bandwidth_cmd,
|
---|
| 602 | [XHCI_CMD_FORCE_HEADER] = NULL,
|
---|
| 603 | [XHCI_CMD_NO_OP] = no_op_cmd
|
---|
| 604 | };
|
---|
| 605 |
|
---|
[eb928c4] | 606 | /**
|
---|
| 607 | * Try to abort currently processed command. This is tricky, because
|
---|
| 608 | * calling fibril is not necessarily the one which issued the blocked command.
|
---|
| 609 | * Also, the trickiness intensifies by the fact that stopping a CR is denoted by
|
---|
| 610 | * event, which is again handled in different fibril. but, once we go to sleep
|
---|
| 611 | * on waiting for that event, another fibril may wake up and try to abort the
|
---|
| 612 | * blocked command.
|
---|
| 613 | *
|
---|
| 614 | * So, we mark the command ring as being restarted, wait for it to stop, and
|
---|
| 615 | * then start it again. If there was a blocked command, it will be satisfied by
|
---|
| 616 | * COMMAND_ABORTED event.
|
---|
| 617 | */
|
---|
[889146e] | 618 | static int try_abort_current_command(xhci_hc_t *hc)
|
---|
| 619 | {
|
---|
| 620 | xhci_cmd_ring_t *cr = get_cmd_ring(hc);
|
---|
| 621 |
|
---|
| 622 | fibril_mutex_lock(&cr->guard);
|
---|
| 623 |
|
---|
[d2c3dcd] | 624 | if (cr->state == XHCI_CR_STATE_CLOSED) {
|
---|
| 625 | fibril_mutex_unlock(&cr->guard);
|
---|
| 626 | return ENAK;
|
---|
| 627 | }
|
---|
| 628 |
|
---|
| 629 | if (cr->state == XHCI_CR_STATE_CHANGING) {
|
---|
[889146e] | 630 | fibril_mutex_unlock(&cr->guard);
|
---|
| 631 | return EOK;
|
---|
| 632 | }
|
---|
| 633 |
|
---|
[837581fd] | 634 | usb_log_error("Timeout while waiting for command: aborting current command.");
|
---|
[889146e] | 635 |
|
---|
[d2c3dcd] | 636 | cr_set_state(cr, XHCI_CR_STATE_CHANGING);
|
---|
[889146e] | 637 |
|
---|
| 638 | abort_command_ring(hc);
|
---|
| 639 |
|
---|
| 640 | fibril_condvar_wait_timeout(&cr->stopped_cv, &cr->guard, XHCI_CR_ABORT_TIMEOUT);
|
---|
| 641 |
|
---|
| 642 | if (XHCI_REG_RD(hc->op_regs, XHCI_OP_CRR)) {
|
---|
| 643 | /* 4.6.1.2, implementation note
|
---|
| 644 | * Assume there are larger problems with HC and
|
---|
| 645 | * reset it.
|
---|
| 646 | */
|
---|
[837581fd] | 647 | usb_log_error("Command didn't abort.");
|
---|
[889146e] | 648 |
|
---|
[d2c3dcd] | 649 | cr_set_state(cr, XHCI_CR_STATE_CLOSED);
|
---|
[889146e] | 650 |
|
---|
| 651 | // TODO: Reset HC completely.
|
---|
| 652 | // Don't forget to somehow complete all commands with error.
|
---|
| 653 |
|
---|
| 654 | fibril_mutex_unlock(&cr->guard);
|
---|
| 655 | return ENAK;
|
---|
| 656 | }
|
---|
| 657 |
|
---|
[d2c3dcd] | 658 | cr_set_state(cr, XHCI_CR_STATE_OPEN);
|
---|
| 659 |
|
---|
| 660 | fibril_mutex_unlock(&cr->guard);
|
---|
| 661 |
|
---|
[837581fd] | 662 | usb_log_error("Command ring stopped. Starting again.");
|
---|
[889146e] | 663 | hc_ring_doorbell(hc, 0, 0);
|
---|
| 664 |
|
---|
| 665 | return EOK;
|
---|
| 666 | }
|
---|
| 667 |
|
---|
[eb928c4] | 668 | /**
|
---|
| 669 | * Wait, until the command is completed. The completion is triggered by
|
---|
| 670 | * COMMAND_COMPLETION event. As we do not want to rely on HW completing the
|
---|
| 671 | * command in timely manner, we timeout. Note that we can't just return an
|
---|
| 672 | * error after the timeout pass - it may be other command blocking the ring,
|
---|
| 673 | * and ours can be completed afterwards. Therefore, it is not guaranteed that
|
---|
| 674 | * this function will return in XHCI_COMMAND_TIMEOUT. It will continue waiting
|
---|
| 675 | * until COMMAND_COMPLETION event arrives.
|
---|
| 676 | */
|
---|
[889146e] | 677 | static int wait_for_cmd_completion(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
[f9e7fe8] | 678 | {
|
---|
[c3d926f3] | 679 | int rv = EOK;
|
---|
[c058a388] | 680 |
|
---|
[f3baab1] | 681 | if (fibril_get_id() == hc->event_handler) {
|
---|
| 682 | usb_log_error("Deadlock detected in waiting for command.");
|
---|
| 683 | abort();
|
---|
| 684 | }
|
---|
| 685 |
|
---|
[c3d926f3] | 686 | fibril_mutex_lock(&cmd->_header.completed_mtx);
|
---|
| 687 | while (!cmd->_header.completed) {
|
---|
[f9e7fe8] | 688 |
|
---|
[8033f89] | 689 | rv = fibril_condvar_wait_timeout(&cmd->_header.completed_cv,
|
---|
| 690 | &cmd->_header.completed_mtx, XHCI_COMMAND_TIMEOUT);
|
---|
[889146e] | 691 |
|
---|
| 692 | /* The waiting timed out. Current command (not necessarily
|
---|
| 693 | * ours) is probably blocked.
|
---|
| 694 | */
|
---|
| 695 | if (!cmd->_header.completed && rv == ETIMEOUT) {
|
---|
| 696 | fibril_mutex_unlock(&cmd->_header.completed_mtx);
|
---|
| 697 |
|
---|
| 698 | rv = try_abort_current_command(hc);
|
---|
| 699 | if (rv)
|
---|
| 700 | return rv;
|
---|
| 701 |
|
---|
| 702 | fibril_mutex_lock(&cmd->_header.completed_mtx);
|
---|
[c3d926f3] | 703 | }
|
---|
| 704 | }
|
---|
| 705 | fibril_mutex_unlock(&cmd->_header.completed_mtx);
|
---|
[f711f06] | 706 |
|
---|
[c3d926f3] | 707 | return rv;
|
---|
| 708 | }
|
---|
[2fa43d1] | 709 |
|
---|
[eb928c4] | 710 | /**
|
---|
| 711 | * Issue command and block the current fibril until it is completed or timeout
|
---|
| 712 | * expires. Nothing is deallocated. Caller should always execute `xhci_cmd_fini`.
|
---|
[c3d926f3] | 713 | */
|
---|
| 714 | int xhci_cmd_sync(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
| 715 | {
|
---|
| 716 | assert(hc);
|
---|
| 717 | assert(cmd);
|
---|
[2fa43d1] | 718 |
|
---|
[c3d926f3] | 719 | int err;
|
---|
| 720 |
|
---|
| 721 | if (!cmd_handlers[cmd->_header.cmd]) {
|
---|
| 722 | /* Handler not implemented. */
|
---|
| 723 | return ENOTSUP;
|
---|
[2fa43d1] | 724 | }
|
---|
[110d795] | 725 |
|
---|
[c3d926f3] | 726 | if ((err = cmd_handlers[cmd->_header.cmd](hc, cmd))) {
|
---|
| 727 | /* Command could not be issued. */
|
---|
| 728 | return err;
|
---|
| 729 | }
|
---|
[110d795] | 730 |
|
---|
[889146e] | 731 | if ((err = wait_for_cmd_completion(hc, cmd))) {
|
---|
| 732 | /* Command failed. */
|
---|
[c3d926f3] | 733 | return err;
|
---|
[665bf3c] | 734 | }
|
---|
[c362127] | 735 |
|
---|
[e7e99bf] | 736 | switch (cmd->status) {
|
---|
| 737 | case XHCI_TRBC_SUCCESS:
|
---|
| 738 | return EOK;
|
---|
| 739 | case XHCI_TRBC_USB_TRANSACTION_ERROR:
|
---|
| 740 | return ESTALL;
|
---|
[feabe163] | 741 | case XHCI_TRBC_RESOURCE_ERROR:
|
---|
| 742 | case XHCI_TRBC_BANDWIDTH_ERROR:
|
---|
| 743 | case XHCI_TRBC_NO_SLOTS_ERROR:
|
---|
| 744 | return ELIMIT;
|
---|
| 745 | case XHCI_TRBC_SLOT_NOT_ENABLED_ERROR:
|
---|
| 746 | return ENOENT;
|
---|
[e7e99bf] | 747 | default:
|
---|
| 748 | return EINVAL;
|
---|
| 749 | }
|
---|
[c3d926f3] | 750 | }
|
---|
[110d795] | 751 |
|
---|
[eb928c4] | 752 | /**
|
---|
| 753 | * Does the same thing as `xhci_cmd_sync` and executes `xhci_cmd_fini`. This
|
---|
| 754 | * is a useful shorthand for issuing commands without out parameters.
|
---|
[c3d926f3] | 755 | */
|
---|
| 756 | int xhci_cmd_sync_fini(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
| 757 | {
|
---|
| 758 | const int err = xhci_cmd_sync(hc, cmd);
|
---|
| 759 | xhci_cmd_fini(cmd);
|
---|
| 760 |
|
---|
| 761 | return err;
|
---|
| 762 | }
|
---|
| 763 |
|
---|
[eb928c4] | 764 | /**
|
---|
| 765 | * Does the same thing as `xhci_cmd_sync_fini` without blocking the current
|
---|
| 766 | * fibril. The command is copied to stack memory and `fini` is called upon its completion.
|
---|
[c3d926f3] | 767 | */
|
---|
| 768 | int xhci_cmd_async_fini(xhci_hc_t *hc, xhci_cmd_t *stack_cmd)
|
---|
| 769 | {
|
---|
| 770 | assert(hc);
|
---|
| 771 | assert(stack_cmd);
|
---|
| 772 |
|
---|
| 773 | /* Save the command for later. */
|
---|
| 774 | xhci_cmd_t *heap_cmd = (xhci_cmd_t *) malloc(sizeof(xhci_cmd_t));
|
---|
| 775 | if (!heap_cmd) {
|
---|
| 776 | return ENOMEM;
|
---|
| 777 | }
|
---|
| 778 |
|
---|
| 779 | /* TODO: Is this good for the mutex and the condvar? */
|
---|
| 780 | memcpy(heap_cmd, stack_cmd, sizeof(xhci_cmd_t));
|
---|
| 781 | heap_cmd->_header.async = true;
|
---|
| 782 |
|
---|
| 783 | /* Issue the command. */
|
---|
| 784 | int err;
|
---|
| 785 |
|
---|
| 786 | if (!cmd_handlers[heap_cmd->_header.cmd]) {
|
---|
| 787 | /* Handler not implemented. */
|
---|
| 788 | err = ENOTSUP;
|
---|
| 789 | goto err_heap_cmd;
|
---|
[f711f06] | 790 | }
|
---|
[110d795] | 791 |
|
---|
[c3d926f3] | 792 | if ((err = cmd_handlers[heap_cmd->_header.cmd](hc, heap_cmd))) {
|
---|
| 793 | /* Command could not be issued. */
|
---|
| 794 | goto err_heap_cmd;
|
---|
| 795 | }
|
---|
[4688350b] | 796 |
|
---|
[110d795] | 797 | return EOK;
|
---|
[c9c0e41] | 798 |
|
---|
[c3d926f3] | 799 | err_heap_cmd:
|
---|
| 800 | free(heap_cmd);
|
---|
| 801 | return err;
|
---|
| 802 | }
|
---|
[c9c0e41] | 803 |
|
---|
| 804 | /**
|
---|
| 805 | * @}
|
---|
| 806 | */
|
---|