source: mainline/uspace/drv/bus/usb/uhci/uhci_batch.c@ 5fe3f954

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 5fe3f954 was 1d758fc, checked in by Ondřej Hlavatý <aearsis@…>, 8 years ago

usb: rethinking DMA buffers

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File size: 10.2 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbuhcihc
30 * @{
31 */
32/** @file
33 * @brief UHCI driver USB transfer structure
34 */
35
36#include <assert.h>
37#include <errno.h>
38#include <macros.h>
39#include <mem.h>
40#include <stdlib.h>
41
42#include <usb/usb.h>
43#include <usb/debug.h>
44#include <usb/host/endpoint.h>
45#include <usb/host/utils/malloc32.h>
46
47#include "uhci_batch.h"
48#include "hc.h"
49#include "hw_struct/transfer_descriptor.h"
50
51#define DEFAULT_ERROR_COUNT 3
52
53/** Transfer batch setup table. */
54static void (*const batch_setup[])(uhci_transfer_batch_t*);
55
56/** Destroys uhci_transfer_batch_t structure.
57 *
58 * @param[in] uhci_batch Instance to destroy.
59 */
60void uhci_transfer_batch_destroy(uhci_transfer_batch_t *uhci_batch)
61{
62 assert(uhci_batch);
63 dma_buffer_free(&uhci_batch->uhci_dma_buffer);
64 free(uhci_batch);
65}
66
67/** Allocate memory and initialize internal data structure.
68 *
69 * @param[in] usb_batch Pointer to generic USB batch structure.
70 * @return Valid pointer if all structures were successfully created,
71 * NULL otherwise.
72 */
73uhci_transfer_batch_t * uhci_transfer_batch_create(endpoint_t *ep)
74{
75 uhci_transfer_batch_t *uhci_batch =
76 calloc(1, sizeof(uhci_transfer_batch_t));
77 if (!uhci_batch) {
78 usb_log_error("Failed to allocate UHCI batch.");
79 return NULL;
80 }
81
82 usb_transfer_batch_init(&uhci_batch->base, ep);
83
84 link_initialize(&uhci_batch->link);
85 return uhci_batch;
86}
87
88/* Prepares batch for commiting.
89 *
90 * Determines the number of needed transfer descriptors (TDs).
91 * Prepares a transport buffer (that is accessible by the hardware).
92 * Initializes parameters needed for the transfer and callback.
93 */
94int uhci_transfer_batch_prepare(uhci_transfer_batch_t *uhci_batch)
95{
96 static_assert((sizeof(td_t) % 16) == 0);
97
98 usb_transfer_batch_t *usb_batch = &uhci_batch->base;
99
100 uhci_batch->td_count = (usb_batch->size + usb_batch->ep->max_packet_size - 1)
101 / usb_batch->ep->max_packet_size;
102
103 if (usb_batch->ep->transfer_type == USB_TRANSFER_CONTROL) {
104 uhci_batch->td_count += 2;
105 }
106
107 const size_t setup_size = (usb_batch->ep->transfer_type == USB_TRANSFER_CONTROL)
108 ? USB_SETUP_PACKET_SIZE
109 : 0;
110
111 const size_t total_size = (sizeof(td_t) * uhci_batch->td_count)
112 + sizeof(qh_t) + setup_size;
113
114 if (dma_buffer_alloc(&uhci_batch->uhci_dma_buffer, total_size)) {
115 usb_log_error("Failed to allocate UHCI buffer.");
116 return ENOMEM;
117 }
118 memset(uhci_batch->uhci_dma_buffer.virt, 0, total_size);
119
120 uhci_batch->tds = uhci_batch->uhci_dma_buffer.virt;
121 uhci_batch->qh = (qh_t *) &uhci_batch->tds[uhci_batch->td_count];
122
123 qh_init(uhci_batch->qh);
124 qh_set_element_td(uhci_batch->qh, &uhci_batch->tds[0]);
125
126 void *setup_buffer = uhci_transfer_batch_setup_buffer(uhci_batch);
127 assert(setup_buffer == (void *) (uhci_batch->qh + 1));
128 /* Copy SETUP packet data to the device buffer */
129 memcpy(setup_buffer, usb_batch->setup.buffer, setup_size);
130
131 usb_log_debug2("Batch %p " USB_TRANSFER_BATCH_FMT
132 " memory structures ready.", usb_batch,
133 USB_TRANSFER_BATCH_ARGS(*usb_batch));
134
135 assert(batch_setup[usb_batch->ep->transfer_type]);
136 batch_setup[usb_batch->ep->transfer_type](uhci_batch);
137
138 return EOK;
139}
140
141/** Check batch TDs for activity.
142 *
143 * @param[in] uhci_batch Batch structure to use.
144 * @return False, if there is an active TD, true otherwise.
145 *
146 * Walk all TDs. Stop with false if there is an active one (it is to be
147 * processed). Stop with true if an error is found. Return true if the last TD
148 * is reached.
149 */
150bool uhci_transfer_batch_check_completed(uhci_transfer_batch_t *uhci_batch)
151{
152 assert(uhci_batch);
153 usb_transfer_batch_t *batch = &uhci_batch->base;
154
155 usb_log_debug2("Batch %p " USB_TRANSFER_BATCH_FMT
156 " checking %zu transfer(s) for completion.",
157 uhci_batch, USB_TRANSFER_BATCH_ARGS(*batch),
158 uhci_batch->td_count);
159 batch->transferred_size = 0;
160
161 uhci_endpoint_t *uhci_ep = (uhci_endpoint_t *) batch->ep;
162
163 for (size_t i = 0;i < uhci_batch->td_count; ++i) {
164 if (td_is_active(&uhci_batch->tds[i])) {
165 return false;
166 }
167
168 batch->error = td_status(&uhci_batch->tds[i]);
169 if (batch->error != EOK) {
170 assert(batch->ep != NULL);
171
172 usb_log_debug("Batch %p found error TD(%zu->%p):%"
173 PRIx32 ".", uhci_batch, i,
174 &uhci_batch->tds[i], uhci_batch->tds[i].status);
175 td_print_status(&uhci_batch->tds[i]);
176
177 uhci_ep->toggle = td_toggle(&uhci_batch->tds[i]);
178 goto substract_ret;
179 }
180
181 batch->transferred_size
182 += td_act_size(&uhci_batch->tds[i]);
183 if (td_is_short(&uhci_batch->tds[i]))
184 goto substract_ret;
185 }
186substract_ret:
187 if (batch->transferred_size > 0 && batch->ep->transfer_type == USB_TRANSFER_CONTROL) {
188 assert(batch->transferred_size >= USB_SETUP_PACKET_SIZE);
189 batch->transferred_size -= USB_SETUP_PACKET_SIZE;
190 }
191
192 assert(batch->transferred_size <= batch->size);
193
194 return true;
195}
196
197/** Direction to pid conversion table */
198static const usb_packet_id direction_pids[] = {
199 [USB_DIRECTION_IN] = USB_PID_IN,
200 [USB_DIRECTION_OUT] = USB_PID_OUT,
201};
202
203/** Prepare generic data transfer
204 *
205 * @param[in] uhci_batch Batch structure to use.
206 * @param[in] dir Communication direction.
207 *
208 * Transactions with alternating toggle bit and supplied pid value.
209 * The last transfer is marked with IOC flag.
210 */
211static void batch_data(uhci_transfer_batch_t *uhci_batch)
212{
213 assert(uhci_batch);
214
215 usb_direction_t dir = uhci_batch->base.dir;
216 assert(dir == USB_DIRECTION_OUT || dir == USB_DIRECTION_IN);
217
218
219 const usb_packet_id pid = direction_pids[dir];
220 const bool low_speed =
221 uhci_batch->base.ep->device->speed == USB_SPEED_LOW;
222 const size_t mps = uhci_batch->base.ep->max_packet_size;
223
224 uhci_endpoint_t *uhci_ep = (uhci_endpoint_t *) uhci_batch->base.ep;
225
226 int toggle = uhci_ep->toggle;
227 assert(toggle == 0 || toggle == 1);
228
229 size_t td = 0;
230 size_t remain_size = uhci_batch->base.size;
231 char *buffer = uhci_transfer_batch_data_buffer(uhci_batch);
232
233 while (remain_size > 0) {
234 const size_t packet_size = min(remain_size, mps);
235
236 const td_t *next_td = (td + 1 < uhci_batch->td_count)
237 ? &uhci_batch->tds[td + 1] : NULL;
238
239 assert(td < uhci_batch->td_count);
240 td_init(
241 &uhci_batch->tds[td], DEFAULT_ERROR_COUNT, packet_size,
242 toggle, false, low_speed, uhci_batch->base.target, pid, buffer, next_td);
243
244 ++td;
245 toggle = 1 - toggle;
246 buffer += packet_size;
247 remain_size -= packet_size;
248 }
249 td_set_ioc(&uhci_batch->tds[td - 1]);
250 uhci_ep->toggle = toggle;
251 usb_log_debug2(
252 "Batch %p %s %s " USB_TRANSFER_BATCH_FMT " initialized.", \
253 uhci_batch,
254 usb_str_transfer_type(uhci_batch->base.ep->transfer_type),
255 usb_str_direction(uhci_batch->base.ep->direction),
256 USB_TRANSFER_BATCH_ARGS(uhci_batch->base));
257}
258
259/** Prepare generic control transfer
260 *
261 * @param[in] uhci_batch Batch structure to use.
262 * @param[in] dir Communication direction.
263 *
264 * Setup stage with toggle 0 and USB_PID_SETUP.
265 * Data stage with alternating toggle and pid determined by the communication
266 * direction.
267 * Status stage with toggle 1 and pid determined by the communication direction.
268 * The last transfer is marked with IOC.
269 */
270static void batch_control(uhci_transfer_batch_t *uhci_batch)
271{
272 assert(uhci_batch);
273
274 usb_direction_t dir = uhci_batch->base.dir;
275 assert(dir == USB_DIRECTION_OUT || dir == USB_DIRECTION_IN);
276 assert(uhci_batch->td_count >= 2);
277 static const usb_packet_id status_stage_pids[] = {
278 [USB_DIRECTION_IN] = USB_PID_OUT,
279 [USB_DIRECTION_OUT] = USB_PID_IN,
280 };
281
282 const usb_packet_id data_stage_pid = direction_pids[dir];
283 const usb_packet_id status_stage_pid = status_stage_pids[dir];
284 const bool low_speed =
285 uhci_batch->base.ep->device->speed == USB_SPEED_LOW;
286 const size_t mps = uhci_batch->base.ep->max_packet_size;
287 const usb_target_t target = uhci_batch->base.target;
288
289 /* setup stage */
290 td_init(
291 &uhci_batch->tds[0], DEFAULT_ERROR_COUNT,
292 USB_SETUP_PACKET_SIZE, 0, false,
293 low_speed, target, USB_PID_SETUP,
294 uhci_transfer_batch_setup_buffer(uhci_batch), &uhci_batch->tds[1]);
295
296 /* data stage */
297 size_t td = 1;
298 unsigned toggle = 1;
299 size_t remain_size = uhci_batch->base.size;
300 char *buffer = uhci_transfer_batch_data_buffer(uhci_batch);
301
302 while (remain_size > 0) {
303 const size_t packet_size = min(remain_size, mps);
304
305 td_init(
306 &uhci_batch->tds[td], DEFAULT_ERROR_COUNT, packet_size,
307 toggle, false, low_speed, target, data_stage_pid,
308 buffer, &uhci_batch->tds[td + 1]);
309
310 ++td;
311 toggle = 1 - toggle;
312 buffer += packet_size;
313 remain_size -= packet_size;
314 assert(td < uhci_batch->td_count);
315 }
316
317 /* status stage */
318 assert(td == uhci_batch->td_count - 1);
319
320 td_init(
321 &uhci_batch->tds[td], DEFAULT_ERROR_COUNT, 0, 1, false, low_speed,
322 target, status_stage_pid, NULL, NULL);
323 td_set_ioc(&uhci_batch->tds[td]);
324
325 usb_log_debug2("Control last TD status: %x.",
326 uhci_batch->tds[td].status);
327}
328
329static void (*const batch_setup[])(uhci_transfer_batch_t*) =
330{
331 [USB_TRANSFER_CONTROL] = batch_control,
332 [USB_TRANSFER_BULK] = batch_data,
333 [USB_TRANSFER_INTERRUPT] = batch_data,
334 [USB_TRANSFER_ISOCHRONOUS] = NULL,
335};
336/**
337 * @}
338 */
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