[9351353] | 1 | /*
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| 2 | * Copyright (c) 2011 Jan Vesely
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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[17ceb72] | 28 | /** @addtogroup drvusbuhcihc
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[9351353] | 29 | * @{
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| 30 | */
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| 31 | /** @file
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[17ceb72] | 32 | * @brief UHCI Host controller driver routines
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[9351353] | 33 | */
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| 34 | #include <errno.h>
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| 35 | #include <str_error.h>
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| 36 | #include <adt/list.h>
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| 37 | #include <libarch/ddi.h>
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| 38 |
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| 39 | #include <usb/debug.h>
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| 40 | #include <usb/usb.h>
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| 41 |
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[c01cd32] | 42 | #include "hc.h"
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[9351353] | 43 |
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[8986412] | 44 | #define UHCI_INTR_ALLOW_INTERRUPTS \
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[af81980] | 45 | (UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET)
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[8986412] | 46 | #define UHCI_STATUS_USED_INTERRUPTS \
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| 47 | (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)
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[af81980] | 48 |
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[dfe4955] | 49 | static const irq_cmd_t uhci_irq_commands[] =
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| 50 | {
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| 51 | { .cmd = CMD_PIO_READ_16, .dstarg = 1, .addr = NULL/*filled later*/},
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| 52 | { .cmd = CMD_BTEST, .srcarg = 1, .dstarg = 2,
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| 53 | .value = UHCI_STATUS_USED_INTERRUPTS | UHCI_STATUS_NM_INTERRUPTS },
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| 54 | { .cmd = CMD_PREDICATE, .srcarg = 2, .value = 2 },
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| 55 | { .cmd = CMD_PIO_WRITE_A_16, .srcarg = 1, .addr = NULL/*filled later*/},
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| 56 | { .cmd = CMD_ACCEPT },
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| 57 | };
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[302a4b6] | 58 |
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[c01cd32] | 59 | static int hc_init_transfer_lists(hc_t *instance);
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| 60 | static int hc_init_mem_structures(hc_t *instance);
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| 61 | static void hc_init_hw(hc_t *instance);
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[9351353] | 62 |
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[c01cd32] | 63 | static int hc_interrupt_emulator(void *arg);
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| 64 | static int hc_debug_checker(void *arg);
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[dfe4955] | 65 |
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| 66 | /*----------------------------------------------------------------------------*/
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| 67 | /** Get number of commands used in IRQ code.
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| 68 | * @return Number of commands.
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| 69 | */
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| 70 | size_t hc_irq_cmd_count(void)
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| 71 | {
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| 72 | return sizeof(uhci_irq_commands) / sizeof(irq_cmd_t);
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| 73 | }
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| 74 | /*----------------------------------------------------------------------------*/
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| 75 | /** Generate IRQ code commands.
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| 76 | * @param[out] cmds Place to store the commands.
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| 77 | * @param[in] cmd_size Size of the place (bytes).
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| 78 | * @param[in] regs Physical address of device's registers.
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| 79 | * @param[in] reg_size Size of the register area (bytes).
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| 80 | *
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| 81 | * @return Error code.
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| 82 | */
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| 83 | int hc_get_irq_commands(
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| 84 | irq_cmd_t cmds[], size_t cmd_size, uintptr_t regs, size_t reg_size)
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| 85 | {
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| 86 | if (cmd_size < sizeof(uhci_irq_commands)
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| 87 | || reg_size < sizeof(uhci_regs_t))
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| 88 | return EOVERFLOW;
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| 89 |
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| 90 | uhci_regs_t *registers = (uhci_regs_t*)regs;
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| 91 |
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| 92 | memcpy(cmds, uhci_irq_commands, sizeof(uhci_irq_commands));
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| 93 |
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| 94 | cmds[0].addr = (void*)®isters->usbsts;
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| 95 | cmds[3].addr = (void*)®isters->usbsts;
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| 96 | return EOK;
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| 97 | }
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[9351353] | 98 | /*----------------------------------------------------------------------------*/
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[02cacce] | 99 | /** Initialize UHCI hc driver structure
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[9351353] | 100 | *
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| 101 | * @param[in] instance Memory place to initialize.
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| 102 | * @param[in] regs Address of I/O control registers.
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[23f40280] | 103 | * @param[in] reg_size Size of I/O control registers.
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| 104 | * @param[in] interrupts True if hw interrupts should be used.
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[9351353] | 105 | * @return Error code.
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| 106 | * @note Should be called only once on any structure.
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[17ceb72] | 107 | *
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| 108 | * Initializes memory structures, starts up hw, and launches debugger and
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| 109 | * interrupt fibrils.
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[9351353] | 110 | */
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[d2bff2f] | 111 | int hc_init(hc_t *instance, void *regs, size_t reg_size, bool interrupts)
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[9351353] | 112 | {
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[dfe4955] | 113 | assert(reg_size >= sizeof(uhci_regs_t));
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[9351353] | 114 | int ret;
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| 115 |
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[ea993d18] | 116 | #define CHECK_RET_RETURN(ret, message...) \
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[9351353] | 117 | if (ret != EOK) { \
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| 118 | usb_log_error(message); \
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| 119 | return ret; \
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| 120 | } else (void) 0
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| 121 |
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[ff34e5a] | 122 | instance->hw_interrupts = interrupts;
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[fcc525d] | 123 | instance->hw_failures = 0;
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| 124 |
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[9351353] | 125 | /* allow access to hc control registers */
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[dfe4955] | 126 | uhci_regs_t *io;
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[e247d83] | 127 | ret = pio_enable(regs, reg_size, (void **)&io);
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[26858040] | 128 | CHECK_RET_RETURN(ret, "Failed to gain access to registers at %p: %s.\n",
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| 129 | io, str_error(ret));
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[9351353] | 130 | instance->registers = io;
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[26858040] | 131 | usb_log_debug(
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| 132 | "Device registers at %p (%zuB) accessible.\n", io, reg_size);
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[9351353] | 133 |
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[c01cd32] | 134 | ret = hc_init_mem_structures(instance);
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[ea993d18] | 135 | CHECK_RET_RETURN(ret,
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[26858040] | 136 | "Failed to initialize UHCI memory structures: %s.\n",
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| 137 | str_error(ret));
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[9351353] | 138 |
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[c01cd32] | 139 | hc_init_hw(instance);
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[ff34e5a] | 140 | if (!interrupts) {
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[ea993d18] | 141 | instance->interrupt_emulator =
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[c01cd32] | 142 | fibril_create(hc_interrupt_emulator, instance);
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[ea993d18] | 143 | fibril_add_ready(instance->interrupt_emulator);
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[ff34e5a] | 144 | }
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[ea993d18] | 145 | (void)hc_debug_checker;
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[9351353] | 146 |
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| 147 | return EOK;
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| 148 | #undef CHECK_RET_DEST_FUN_RETURN
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| 149 | }
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| 150 | /*----------------------------------------------------------------------------*/
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[17ceb72] | 151 | /** Initialize UHCI hc hw resources.
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[9351353] | 152 | *
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| 153 | * @param[in] instance UHCI structure to use.
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[17ceb72] | 154 | * For magic values see UHCI Design Guide
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[9351353] | 155 | */
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[c01cd32] | 156 | void hc_init_hw(hc_t *instance)
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[9351353] | 157 | {
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| 158 | assert(instance);
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[dfe4955] | 159 | uhci_regs_t *registers = instance->registers;
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[9351353] | 160 |
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| 161 | /* Reset everything, who knows what touched it before us */
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| 162 | pio_write_16(®isters->usbcmd, UHCI_CMD_GLOBAL_RESET);
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[26858040] | 163 | async_usleep(50000); /* 50ms according to USB spec(root hub reset) */
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[9351353] | 164 | pio_write_16(®isters->usbcmd, 0);
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| 165 |
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[26858040] | 166 | /* Reset hc, all states and counters. Hope that hw is not broken */
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[9351353] | 167 | pio_write_16(®isters->usbcmd, UHCI_CMD_HCRESET);
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| 168 | do { async_usleep(10); }
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| 169 | while ((pio_read_16(®isters->usbcmd) & UHCI_CMD_HCRESET) != 0);
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| 170 |
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[eb2a48a] | 171 | /* Set frame to exactly 1ms */
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| 172 | pio_write_8(®isters->sofmod, 64);
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| 173 |
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| 174 | /* Set frame list pointer */
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[9351353] | 175 | const uint32_t pa = addr_to_phys(instance->frame_list);
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| 176 | pio_write_32(®isters->flbaseadd, pa);
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| 177 |
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[ff34e5a] | 178 | if (instance->hw_interrupts) {
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| 179 | /* Enable all interrupts, but resume interrupt */
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| 180 | pio_write_16(&instance->registers->usbintr,
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[8986412] | 181 | UHCI_INTR_ALLOW_INTERRUPTS);
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[ff34e5a] | 182 | }
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[9351353] | 183 |
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[26858040] | 184 | const uint16_t cmd = pio_read_16(®isters->usbcmd);
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| 185 | if (cmd != 0)
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| 186 | usb_log_warning("Previous command value: %x.\n", cmd);
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[9351353] | 187 |
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| 188 | /* Start the hc with large(64B) packet FSBR */
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| 189 | pio_write_16(®isters->usbcmd,
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| 190 | UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
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| 191 | }
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| 192 | /*----------------------------------------------------------------------------*/
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[17ceb72] | 193 | /** Initialize UHCI hc memory structures.
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[9351353] | 194 | *
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| 195 | * @param[in] instance UHCI structure to use.
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| 196 | * @return Error code
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| 197 | * @note Should be called only once on any structure.
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[17ceb72] | 198 | *
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| 199 | * Structures:
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| 200 | * - interrupt code (I/O addressses are customized per instance)
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| 201 | * - transfer lists (queue heads need to be accessible by the hw)
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| 202 | * - frame list page (needs to be one UHCI hw accessible 4K page)
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[9351353] | 203 | */
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[c01cd32] | 204 | int hc_init_mem_structures(hc_t *instance)
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[9351353] | 205 | {
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| 206 | assert(instance);
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[77d10f0] | 207 | #define CHECK_RET_RETURN(ret, message...) \
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[9351353] | 208 | if (ret != EOK) { \
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| 209 | usb_log_error(message); \
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| 210 | return ret; \
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| 211 | } else (void) 0
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| 212 |
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| 213 | /* Init transfer lists */
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[77d10f0] | 214 | int ret = hc_init_transfer_lists(instance);
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[26858040] | 215 | CHECK_RET_RETURN(ret, "Failed to initialize transfer lists.\n");
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[9351353] | 216 | usb_log_debug("Initialized transfer lists.\n");
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| 217 |
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[26858040] | 218 | /* Init device keeper */
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| 219 | usb_device_keeper_init(&instance->manager);
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| 220 | usb_log_debug("Initialized device keeper.\n");
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| 221 |
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| 222 | ret = usb_endpoint_manager_init(&instance->ep_manager,
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| 223 | BANDWIDTH_AVAILABLE_USB11);
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| 224 | CHECK_RET_RETURN(ret, "Failed to initialize endpoint manager: %s.\n",
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| 225 | str_error(ret));
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| 226 |
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[9351353] | 227 | /* Init USB frame list page*/
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| 228 | instance->frame_list = get_page();
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[26858040] | 229 | if (!instance->frame_list) {
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| 230 | usb_log_error("Failed to get frame list page.\n");
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| 231 | usb_endpoint_manager_destroy(&instance->ep_manager);
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| 232 | return ENOMEM;
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| 233 | }
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[001b152] | 234 | usb_log_debug("Initialized frame list at %p.\n", instance->frame_list);
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[9351353] | 235 |
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| 236 | /* Set all frames to point to the first queue head */
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[302a4b6] | 237 | const uint32_t queue = LINK_POINTER_QH(
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| 238 | addr_to_phys(instance->transfers_interrupt.queue_head));
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[9351353] | 239 | unsigned i = 0;
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| 240 | for(; i < UHCI_FRAME_LIST_COUNT; ++i) {
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| 241 | instance->frame_list[i] = queue;
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| 242 | }
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| 243 |
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| 244 | return EOK;
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[77d10f0] | 245 | #undef CHECK_RET_RETURN
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[9351353] | 246 | }
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| 247 | /*----------------------------------------------------------------------------*/
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[17ceb72] | 248 | /** Initialize UHCI hc transfer lists.
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[9351353] | 249 | *
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| 250 | * @param[in] instance UHCI structure to use.
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| 251 | * @return Error code
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| 252 | * @note Should be called only once on any structure.
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[17ceb72] | 253 | *
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| 254 | * Initializes transfer lists and sets them in one chain to support proper
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| 255 | * USB scheduling. Sets pointer table for quick access.
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[9351353] | 256 | */
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[c01cd32] | 257 | int hc_init_transfer_lists(hc_t *instance)
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[9351353] | 258 | {
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| 259 | assert(instance);
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[27205841] | 260 | #define SETUP_TRANSFER_LIST(type, name) \
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| 261 | do { \
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| 262 | int ret = transfer_list_init(&instance->transfers_##type, name); \
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[9351353] | 263 | if (ret != EOK) { \
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[26858040] | 264 | usb_log_error("Failed to setup %s transfer list: %s.\n", \
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| 265 | name, str_error(ret)); \
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[9351353] | 266 | transfer_list_fini(&instance->transfers_bulk_full); \
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| 267 | transfer_list_fini(&instance->transfers_control_full); \
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| 268 | transfer_list_fini(&instance->transfers_control_slow); \
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| 269 | transfer_list_fini(&instance->transfers_interrupt); \
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| 270 | return ret; \
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[27205841] | 271 | } \
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| 272 | } while (0)
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| 273 |
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| 274 | SETUP_TRANSFER_LIST(bulk_full, "BULK FULL");
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| 275 | SETUP_TRANSFER_LIST(control_full, "CONTROL FULL");
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| 276 | SETUP_TRANSFER_LIST(control_slow, "CONTROL LOW");
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| 277 | SETUP_TRANSFER_LIST(interrupt, "INTERRUPT");
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| 278 | #undef SETUP_TRANSFER_LIST
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| 279 | /* Connect lists into one schedule */
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[9351353] | 280 | transfer_list_set_next(&instance->transfers_control_full,
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| 281 | &instance->transfers_bulk_full);
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| 282 | transfer_list_set_next(&instance->transfers_control_slow,
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| 283 | &instance->transfers_control_full);
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| 284 | transfer_list_set_next(&instance->transfers_interrupt,
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| 285 | &instance->transfers_control_slow);
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| 286 |
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[e247d83] | 287 | /*FSBR, This feature is not needed (adds no benefit) and is supposedly
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| 288 | * buggy on certain hw, enable at your own risk. */
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[9351353] | 289 | #ifdef FSBR
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| 290 | transfer_list_set_next(&instance->transfers_bulk_full,
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[302a4b6] | 291 | &instance->transfers_control_full);
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[9351353] | 292 | #endif
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| 293 |
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| 294 | /* Assign pointers to be used during scheduling */
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| 295 | instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
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| 296 | &instance->transfers_interrupt;
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| 297 | instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
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| 298 | &instance->transfers_interrupt;
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| 299 | instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
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| 300 | &instance->transfers_control_full;
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| 301 | instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
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| 302 | &instance->transfers_control_slow;
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| 303 | instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
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| 304 | &instance->transfers_bulk_full;
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| 305 |
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| 306 | return EOK;
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| 307 | #undef CHECK_RET_CLEAR_RETURN
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| 308 | }
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| 309 | /*----------------------------------------------------------------------------*/
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[17ceb72] | 310 | /** Schedule batch for execution.
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[9351353] | 311 | *
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| 312 | * @param[in] instance UHCI structure to use.
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| 313 | * @param[in] batch Transfer batch to schedule.
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| 314 | * @return Error code
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[17ceb72] | 315 | *
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| 316 | * Checks for bandwidth availability and appends the batch to the proper queue.
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[9351353] | 317 | */
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[c01cd32] | 318 | int hc_schedule(hc_t *instance, usb_transfer_batch_t *batch)
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[9351353] | 319 | {
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| 320 | assert(instance);
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| 321 | assert(batch);
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| 322 |
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| 323 | transfer_list_t *list =
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[d017cea] | 324 | instance->transfers[batch->ep->speed][batch->ep->transfer_type];
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[9351353] | 325 | assert(list);
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| 326 | transfer_list_add_batch(list, batch);
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| 327 |
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| 328 | return EOK;
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| 329 | }
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| 330 | /*----------------------------------------------------------------------------*/
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[17ceb72] | 331 | /** Take action based on the interrupt cause.
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[9351353] | 332 | *
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| 333 | * @param[in] instance UHCI structure to use.
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[17ceb72] | 334 | * @param[in] status Value of the status register at the time of interrupt.
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| 335 | *
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| 336 | * Interrupt might indicate:
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| 337 | * - transaction completed, either by triggering IOC, SPD, or an error
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| 338 | * - some kind of device error
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| 339 | * - resume from suspend state (not implemented)
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[9351353] | 340 | */
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[c01cd32] | 341 | void hc_interrupt(hc_t *instance, uint16_t status)
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[9351353] | 342 | {
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| 343 | assert(instance);
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| 344 | /* Lower 2 bits are transaction error and transaction complete */
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[27205841] | 345 | if (status & (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)) {
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[1585c7e] | 346 | LIST_INITIALIZE(done);
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| 347 | transfer_list_remove_finished(
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| 348 | &instance->transfers_interrupt, &done);
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| 349 | transfer_list_remove_finished(
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| 350 | &instance->transfers_control_slow, &done);
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| 351 | transfer_list_remove_finished(
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| 352 | &instance->transfers_control_full, &done);
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| 353 | transfer_list_remove_finished(
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| 354 | &instance->transfers_bulk_full, &done);
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| 355 |
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| 356 | while (!list_empty(&done)) {
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[b72efe8] | 357 | link_t *item = list_first(&done);
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[1585c7e] | 358 | list_remove(item);
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| 359 | usb_transfer_batch_t *batch =
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| 360 | list_get_instance(item, usb_transfer_batch_t, link);
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[cd1cec3b] | 361 | usb_transfer_batch_finish(batch);
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[1585c7e] | 362 | }
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[9351353] | 363 | }
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[27205841] | 364 | /* Resume interrupts are not supported */
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[302a4b6] | 365 | if (status & UHCI_STATUS_RESUME) {
|
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| 366 | usb_log_error("Resume interrupt!\n");
|
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| 367 | }
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[27205841] | 368 |
|
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| 369 | /* Bits 4 and 5 indicate hc error */
|
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| 370 | if (status & (UHCI_STATUS_PROCESS_ERROR | UHCI_STATUS_SYSTEM_ERROR)) {
|
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[fcc525d] | 371 | usb_log_error("UHCI hardware failure!.\n");
|
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| 372 | ++instance->hw_failures;
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[a963a68] | 373 | transfer_list_abort_all(&instance->transfers_interrupt);
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| 374 | transfer_list_abort_all(&instance->transfers_control_slow);
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| 375 | transfer_list_abort_all(&instance->transfers_control_full);
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| 376 | transfer_list_abort_all(&instance->transfers_bulk_full);
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[fcc525d] | 377 |
|
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| 378 | if (instance->hw_failures < UHCI_ALLOWED_HW_FAIL) {
|
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| 379 | /* reinitialize hw, this triggers virtual disconnect*/
|
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[c01cd32] | 380 | hc_init_hw(instance);
|
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[fcc525d] | 381 | } else {
|
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| 382 | usb_log_fatal("Too many UHCI hardware failures!.\n");
|
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[c01cd32] | 383 | hc_fini(instance);
|
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[fcc525d] | 384 | }
|
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[a963a68] | 385 | }
|
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[9351353] | 386 | }
|
---|
| 387 | /*----------------------------------------------------------------------------*/
|
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| 388 | /** Polling function, emulates interrupts.
|
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| 389 | *
|
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[17ceb72] | 390 | * @param[in] arg UHCI hc structure to use.
|
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| 391 | * @return EOK (should never return)
|
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[9351353] | 392 | */
|
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[c01cd32] | 393 | int hc_interrupt_emulator(void* arg)
|
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[9351353] | 394 | {
|
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| 395 | usb_log_debug("Started interrupt emulator.\n");
|
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[6f122df] | 396 | hc_t *instance = arg;
|
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[9351353] | 397 | assert(instance);
|
---|
| 398 |
|
---|
| 399 | while (1) {
|
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[6f122df] | 400 | /* Read and clear status register */
|
---|
[9351353] | 401 | uint16_t status = pio_read_16(&instance->registers->usbsts);
|
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[27205841] | 402 | pio_write_16(&instance->registers->usbsts, status);
|
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[9351353] | 403 | if (status != 0)
|
---|
| 404 | usb_log_debug2("UHCI status: %x.\n", status);
|
---|
[6f122df] | 405 | // Qemu fails to report stalled communication
|
---|
| 406 | // see https://bugs.launchpad.net/qemu/+bug/757654
|
---|
| 407 | // This is a simple workaround to force queue processing every time
|
---|
| 408 | // status |= 1;
|
---|
[c01cd32] | 409 | hc_interrupt(instance, status);
|
---|
[27205841] | 410 | async_usleep(UHCI_INT_EMULATOR_TIMEOUT);
|
---|
[9351353] | 411 | }
|
---|
| 412 | return EOK;
|
---|
| 413 | }
|
---|
| 414 | /*---------------------------------------------------------------------------*/
|
---|
| 415 | /** Debug function, checks consistency of memory structures.
|
---|
| 416 | *
|
---|
| 417 | * @param[in] arg UHCI structure to use.
|
---|
[17ceb72] | 418 | * @return EOK (should never return)
|
---|
[9351353] | 419 | */
|
---|
[c01cd32] | 420 | int hc_debug_checker(void *arg)
|
---|
[9351353] | 421 | {
|
---|
[6f122df] | 422 | hc_t *instance = arg;
|
---|
[9351353] | 423 | assert(instance);
|
---|
| 424 |
|
---|
| 425 | #define QH(queue) \
|
---|
| 426 | instance->transfers_##queue.queue_head
|
---|
| 427 |
|
---|
| 428 | while (1) {
|
---|
| 429 | const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
|
---|
| 430 | const uint16_t sts = pio_read_16(&instance->registers->usbsts);
|
---|
| 431 | const uint16_t intr =
|
---|
| 432 | pio_read_16(&instance->registers->usbintr);
|
---|
| 433 |
|
---|
| 434 | if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
|
---|
| 435 | usb_log_debug2("Command: %X Status: %X Intr: %x\n",
|
---|
| 436 | cmd, sts, intr);
|
---|
| 437 | }
|
---|
| 438 |
|
---|
[e247d83] | 439 | const uintptr_t frame_list =
|
---|
[9351353] | 440 | pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
|
---|
| 441 | if (frame_list != addr_to_phys(instance->frame_list)) {
|
---|
| 442 | usb_log_debug("Framelist address: %p vs. %p.\n",
|
---|
[4125b7d] | 443 | (void *) frame_list,
|
---|
| 444 | (void *) addr_to_phys(instance->frame_list));
|
---|
[9351353] | 445 | }
|
---|
| 446 |
|
---|
| 447 | int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
|
---|
| 448 |
|
---|
| 449 | uintptr_t expected_pa = instance->frame_list[frnum]
|
---|
| 450 | & LINK_POINTER_ADDRESS_MASK;
|
---|
| 451 | uintptr_t real_pa = addr_to_phys(QH(interrupt));
|
---|
| 452 | if (expected_pa != real_pa) {
|
---|
[4125b7d] | 453 | usb_log_debug("Interrupt QH: %p (frame %d) vs. %p.\n",
|
---|
| 454 | (void *) expected_pa, frnum, (void *) real_pa);
|
---|
[9351353] | 455 | }
|
---|
| 456 |
|
---|
| 457 | expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
|
---|
| 458 | real_pa = addr_to_phys(QH(control_slow));
|
---|
| 459 | if (expected_pa != real_pa) {
|
---|
| 460 | usb_log_debug("Control Slow QH: %p vs. %p.\n",
|
---|
[4125b7d] | 461 | (void *) expected_pa, (void *) real_pa);
|
---|
[9351353] | 462 | }
|
---|
| 463 |
|
---|
| 464 | expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
|
---|
| 465 | real_pa = addr_to_phys(QH(control_full));
|
---|
| 466 | if (expected_pa != real_pa) {
|
---|
| 467 | usb_log_debug("Control Full QH: %p vs. %p.\n",
|
---|
[4125b7d] | 468 | (void *) expected_pa, (void *) real_pa);
|
---|
[9351353] | 469 | }
|
---|
| 470 |
|
---|
| 471 | expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
|
---|
| 472 | real_pa = addr_to_phys(QH(bulk_full));
|
---|
| 473 | if (expected_pa != real_pa ) {
|
---|
| 474 | usb_log_debug("Bulk QH: %p vs. %p.\n",
|
---|
[4125b7d] | 475 | (void *) expected_pa, (void *) real_pa);
|
---|
[9351353] | 476 | }
|
---|
| 477 | async_usleep(UHCI_DEBUGER_TIMEOUT);
|
---|
| 478 | }
|
---|
| 479 | return EOK;
|
---|
| 480 | #undef QH
|
---|
| 481 | }
|
---|
| 482 | /**
|
---|
| 483 | * @}
|
---|
| 484 | */
|
---|