source: mainline/uspace/drv/bus/usb/ohci/hc.c@ 53fdf8c

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 53fdf8c was 5a6cc679, checked in by Jenda <jenda.jzqk73@…>, 8 years ago

Merge commit '50f19b7ee8e94570b5c63896736c4eb49cfa18db' into forwardport

Not all ints are converted to errno_t in xhci tree yet, however it compiles and works :)

  • Property mode set to 100644
File size: 17.6 KB
RevLine 
[41b96b4]1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
[8486c07]28
[41b96b4]29/** @addtogroup drvusbohcihc
30 * @{
31 */
32/** @file
33 * @brief OHCI Host controller driver routines
34 */
[8486c07]35
[0d4b110]36#include <assert.h>
37#include <async.h>
[41b96b4]38#include <errno.h>
[0d4b110]39#include <macros.h>
40#include <mem.h>
41#include <stdlib.h>
[41b96b4]42#include <str_error.h>
[8d2dd7f2]43#include <stddef.h>
44#include <stdint.h>
[41b96b4]45
46#include <usb/debug.h>
[c6f82e5]47#include <usb/host/utility.h>
[41b96b4]48#include <usb/usb.h>
49
[e6b9182]50#include "ohci_bus.h"
[0d4b110]51#include "ohci_batch.h"
52
53#include "hc.h"
[41b96b4]54
[561112f]55#define OHCI_USED_INTERRUPTS \
56 (I_SO | I_WDH | I_UE | I_RHSC)
[1ecc5de]57
[d57122c]58static const irq_pio_range_t ohci_pio_ranges[] = {
59 {
[8486c07]60 .base = 0,
[d57122c]61 .size = sizeof(ohci_regs_t)
62 }
63};
64
65static const irq_cmd_t ohci_irq_commands[] = {
[8486c07]66 {
67 .cmd = CMD_PIO_READ_32,
68 .dstarg = 1,
69 .addr = NULL
70 },
71 {
72 .cmd = CMD_AND,
73 .srcarg = 1,
74 .dstarg = 2,
[ea8b91d]75 .value = 0
[8486c07]76 },
77 {
78 .cmd = CMD_PREDICATE,
79 .srcarg = 2,
80 .value = 2
81 },
82 {
83 .cmd = CMD_PIO_WRITE_A_32,
84 .srcarg = 1,
85 .addr = NULL
86 },
87 {
88 .cmd = CMD_ACCEPT
89 }
[1ecc5de]90};
91
[5a6cc679]92static errno_t hc_init_transfer_lists(hc_t *instance);
93static errno_t hc_init_memory(hc_t *instance);
[76fbd9a]94
[d57122c]95/** Generate IRQ code.
96 * @param[out] ranges PIO ranges buffer.
97 * @param[in] ranges_size Size of the ranges buffer (bytes).
98 * @param[out] cmds Commands buffer.
99 * @param[in] cmds_size Size of the commands buffer (bytes).
[ba4a03a5]100 * @param[in] hw_res Device's resources.
[1cb4f05]101 *
102 * @return Error code.
103 */
[5a6cc679]104errno_t hc_gen_irq_code(irq_code_t *code, hc_device_t *hcd, const hw_res_list_parsed_t *hw_res, int *irq)
[1cb4f05]105{
[6210a333]106 assert(code);
[ba4a03a5]107 assert(hw_res);
108
109 if (hw_res->irqs.count != 1 || hw_res->mem_ranges.count != 1)
110 return EINVAL;
111
112 const addr_range_t regs = hw_res->mem_ranges.ranges[0];
113
114 if (RNGSZ(regs) < sizeof(ohci_regs_t))
[1cb4f05]115 return EOVERFLOW;
116
[6210a333]117 code->ranges = malloc(sizeof(ohci_pio_ranges));
118 if (code->ranges == NULL)
119 return ENOMEM;
[1cb4f05]120
[6210a333]121 code->cmds = malloc(sizeof(ohci_irq_commands));
122 if (code->cmds == NULL) {
123 free(code->ranges);
124 return ENOMEM;
125 }
126
127 code->rangecount = ARRAY_SIZE(ohci_pio_ranges);
128 code->cmdcount = ARRAY_SIZE(ohci_irq_commands);
129
130 memcpy(code->ranges, ohci_pio_ranges, sizeof(ohci_pio_ranges));
[ba4a03a5]131 code->ranges[0].base = RNGABS(regs);
[6210a333]132
133 memcpy(code->cmds, ohci_irq_commands, sizeof(ohci_irq_commands));
[ba4a03a5]134 ohci_regs_t *registers = (ohci_regs_t *) RNGABSPTR(regs);
[6210a333]135 code->cmds[0].addr = (void *) &registers->interrupt_status;
136 code->cmds[3].addr = (void *) &registers->interrupt_status;
137 OHCI_WR(code->cmds[1].value, OHCI_USED_INTERRUPTS);
[1cb4f05]138
[a1732929]139 usb_log_debug("Memory mapped regs at %p (size %zu), IRQ %d.",
[ba4a03a5]140 RNGABSPTR(regs), RNGSZ(regs), hw_res->irqs.irqs[0]);
141
[68e5406]142 *irq = hw_res->irqs.irqs[0];
143 return EOK;
[1cb4f05]144}
[76fbd9a]145
[02cacce]146/** Initialize OHCI hc driver structure
147 *
148 * @param[in] instance Memory place for the structure.
[7813516]149 * @param[in] regs Device's resources
[02cacce]150 * @param[in] interrupts True if w interrupts should be used
151 * @return Error code
152 */
[5a6cc679]153errno_t hc_add(hc_device_t *hcd, const hw_res_list_parsed_t *hw_res)
[41b96b4]154{
[32fb6bce]155 hc_t *instance = hcd_to_hc(hcd);
[7813516]156 assert(hw_res);
157 if (hw_res->mem_ranges.count != 1 ||
158 hw_res->mem_ranges.ranges[0].size < sizeof(ohci_regs_t))
159 return EINVAL;
[1cb4f05]160
[5a6cc679]161 errno_t ret = pio_enable_range(&hw_res->mem_ranges.ranges[0],
[7813516]162 (void **) &instance->registers);
[6340a6ff]163 if (ret != EOK) {
[a1732929]164 usb_log_error("Failed to gain access to registers: %s.",
[6340a6ff]165 str_error(ret));
166 return ret;
167 }
[a1732929]168 usb_log_debug("Device registers at %" PRIx64 " (%zuB) accessible.",
[7813516]169 hw_res->mem_ranges.ranges[0].address.absolute,
170 hw_res->mem_ranges.ranges[0].size);
[c2be0e5]171
[d60115a]172 list_initialize(&instance->pending_endpoints);
[6340a6ff]173 fibril_mutex_initialize(&instance->guard);
[e7bc999]174
[8790650]175 ret = hc_init_memory(instance);
[6340a6ff]176 if (ret != EOK) {
[a1732929]177 usb_log_error("Failed to create OHCI memory structures: %s.",
[6340a6ff]178 str_error(ret));
[58563585]179 // TODO: We should disable pio access here
[6340a6ff]180 return ret;
181 }
[2c617b0]182
[8627377]183 return EOK;
[a6d1bc1]184}
[76fbd9a]185
[7813516]186/** Safely dispose host controller internal structures
187 *
188 * @param[in] instance Host controller structure to use.
189 */
[32fb6bce]190int hc_gone(hc_device_t *instance)
[7813516]191{
192 assert(instance);
193 /* TODO: implement*/
[32fb6bce]194 return ENOTSUP;
195}
[7813516]196
[57e06ef]197void hc_enqueue_endpoint(hc_t *instance, const endpoint_t *ep)
[620c710]198{
[57e06ef]199 assert(instance);
200 assert(ep);
201
[620c710]202 endpoint_list_t *list = &instance->lists[ep->transfer_type];
203 ohci_endpoint_t *ohci_ep = ohci_endpoint_get(ep);
[57e06ef]204 assert(list);
205 assert(ohci_ep);
206
[620c710]207 /* Enqueue ep */
208 switch (ep->transfer_type) {
209 case USB_TRANSFER_CONTROL:
[bfc5c9dd]210 OHCI_CLR(instance->registers->control, C_CLE);
[620c710]211 endpoint_list_add_ep(list, ohci_ep);
[bfc5c9dd]212 OHCI_WR(instance->registers->control_current, 0);
213 OHCI_SET(instance->registers->control, C_CLE);
[620c710]214 break;
215 case USB_TRANSFER_BULK:
[bfc5c9dd]216 OHCI_CLR(instance->registers->control, C_BLE);
[f974519]217 endpoint_list_add_ep(list, ohci_ep);
[bfc5c9dd]218 OHCI_WR(instance->registers->bulk_current, 0);
219 OHCI_SET(instance->registers->control, C_BLE);
[620c710]220 break;
221 case USB_TRANSFER_ISOCHRONOUS:
222 case USB_TRANSFER_INTERRUPT:
[bfc5c9dd]223 OHCI_CLR(instance->registers->control, C_PLE | C_IE);
[f974519]224 endpoint_list_add_ep(list, ohci_ep);
[bfc5c9dd]225 OHCI_SET(instance->registers->control, C_PLE | C_IE);
[620c710]226 break;
227 }
228}
[76fbd9a]229
[57e06ef]230void hc_dequeue_endpoint(hc_t *instance, const endpoint_t *ep)
[620c710]231{
[57e06ef]232 assert(instance);
233 assert(ep);
234
[620c710]235 /* Dequeue ep */
236 endpoint_list_t *list = &instance->lists[ep->transfer_type];
237 ohci_endpoint_t *ohci_ep = ohci_endpoint_get(ep);
[57e06ef]238
239 assert(list);
240 assert(ohci_ep);
[620c710]241 switch (ep->transfer_type) {
242 case USB_TRANSFER_CONTROL:
[bfc5c9dd]243 OHCI_CLR(instance->registers->control, C_CLE);
[620c710]244 endpoint_list_remove_ep(list, ohci_ep);
[bfc5c9dd]245 OHCI_WR(instance->registers->control_current, 0);
246 OHCI_SET(instance->registers->control, C_CLE);
[620c710]247 break;
248 case USB_TRANSFER_BULK:
[bfc5c9dd]249 OHCI_CLR(instance->registers->control, C_BLE);
[620c710]250 endpoint_list_remove_ep(list, ohci_ep);
[bfc5c9dd]251 OHCI_WR(instance->registers->bulk_current, 0);
252 OHCI_SET(instance->registers->control, C_BLE);
[620c710]253 break;
254 case USB_TRANSFER_ISOCHRONOUS:
255 case USB_TRANSFER_INTERRUPT:
[bfc5c9dd]256 OHCI_CLR(instance->registers->control, C_PLE | C_IE);
[620c710]257 endpoint_list_remove_ep(list, ohci_ep);
[bfc5c9dd]258 OHCI_SET(instance->registers->control, C_PLE | C_IE);
[620c710]259 break;
260 default:
261 break;
262 }
263}
[76fbd9a]264
[5a6cc679]265errno_t ohci_hc_status(bus_t *bus_base, uint32_t *status)
[e26a9d95]266{
[32fb6bce]267 assert(bus_base);
[e26a9d95]268 assert(status);
269
[32fb6bce]270 ohci_bus_t *bus = (ohci_bus_t *) bus_base;
271 hc_t *hc = bus->hc;
272 assert(hc);
273
274 if (hc->registers){
275 *status = OHCI_RD(hc->registers->interrupt_status);
276 OHCI_WR(hc->registers->interrupt_status, *status);
[e26a9d95]277 }
278 return EOK;
279}
280
[02cacce]281/** Add USB transfer to the schedule.
282 *
[fccf289]283 * @param[in] hcd HCD driver structure.
[02cacce]284 * @param[in] batch Batch representing the transfer.
285 * @return Error code.
286 */
[5a6cc679]287errno_t ohci_hc_schedule(usb_transfer_batch_t *batch)
[41b96b4]288{
[32fb6bce]289 assert(batch);
290
291 ohci_bus_t *bus = (ohci_bus_t *) endpoint_get_bus(batch->ep);
292 hc_t *hc = bus->hc;
293 assert(hc);
[9ff5ff82]294
[02cacce]295 /* Check for root hub communication */
[32fb6bce]296 if (batch->target.address == ohci_rh_get_address(&hc->rh)) {
[a1732929]297 usb_log_debug("OHCI root hub request.");
[32fb6bce]298 return ohci_rh_schedule(&hc->rh, batch);
[41b96b4]299 }
[5fd9c30]300
[d60115a]301 endpoint_t *ep = batch->ep;
302 ohci_endpoint_t * const ohci_ep = ohci_endpoint_get(ep);
[4db49344]303 ohci_transfer_batch_t *ohci_batch = ohci_transfer_batch_get(batch);
304 int err;
305
306 fibril_mutex_lock(&hc->guard);
307 if ((err = endpoint_activate_locked(ep, batch))) {
308 fibril_mutex_unlock(&hc->guard);
309 return err;
310 }
[d60115a]311
[705f83a]312 if ((err = ohci_transfer_batch_prepare(ohci_batch)))
313 return err;
314
[9c10e51]315 ohci_transfer_batch_commit(ohci_batch);
[4db49344]316 list_append(&ohci_ep->pending_link, &hc->pending_endpoints);
317 fibril_mutex_unlock(&hc->guard);
[02cacce]318
319 /* Control and bulk schedules need a kick to start working */
320 switch (batch->ep->transfer_type)
321 {
[9ff5ff82]322 case USB_TRANSFER_CONTROL:
[32fb6bce]323 OHCI_SET(hc->registers->command_status, CS_CLF);
[9ff5ff82]324 break;
325 case USB_TRANSFER_BULK:
[32fb6bce]326 OHCI_SET(hc->registers->command_status, CS_BLF);
[9ff5ff82]327 break;
328 default:
329 break;
330 }
[d60115a]331
[4c28d17]332 return EOK;
[41b96b4]333}
[76fbd9a]334
[02cacce]335/** Interrupt handling routine
336 *
[fccf289]337 * @param[in] hcd HCD driver structure.
[02cacce]338 * @param[in] status Value of the status register at the time of interrupt.
339 */
[32fb6bce]340void ohci_hc_interrupt(bus_t *bus_base, uint32_t status)
[41b96b4]341{
[32fb6bce]342 assert(bus_base);
343
344 ohci_bus_t *bus = (ohci_bus_t *) bus_base;
345 hc_t *hc = bus->hc;
346 assert(hc);
347
[d1ca752]348 status = OHCI_RD(status);
[32fb6bce]349 assert(hc);
[561112f]350 if ((status & ~I_SF) == 0) /* ignore sof status */
[eaf1e3d]351 return;
[a1732929]352 usb_log_debug2("OHCI(%p) interrupt: %x.", hc, status);
[561112f]353 if (status & I_RHSC)
[32fb6bce]354 ohci_rh_interrupt(&hc->rh);
[7d6a676]355
[561112f]356 if (status & I_WDH) {
[32fb6bce]357 fibril_mutex_lock(&hc->guard);
[a1732929]358 usb_log_debug2("HCCA: %p-%#" PRIx32 " (%p).", hc->hcca,
[32fb6bce]359 OHCI_RD(hc->registers->hcca),
360 (void *) addr_to_phys(hc->hcca));
[a1732929]361 usb_log_debug2("Periodic current: %#" PRIx32 ".",
[32fb6bce]362 OHCI_RD(hc->registers->periodic_current));
[eaf1e3d]363
[d60115a]364 list_foreach_safe(hc->pending_endpoints, current, next) {
365 ohci_endpoint_t *ep
366 = list_get_instance(current, ohci_endpoint_t, pending_link);
367
368 ohci_transfer_batch_t *batch
369 = ohci_transfer_batch_get(ep->base.active_batch);
370 assert(batch);
[7013b14]371
[5fd9c30]372 if (ohci_transfer_batch_check_completed(batch)) {
[d60115a]373 endpoint_deactivate_locked(&ep->base);
[d6522dd]374 list_remove(current);
[c6f82e5]375 hc_reset_toggles(&batch->base, &ohci_ep_toggle_reset);
[5fd9c30]376 usb_transfer_batch_finish(&batch->base);
[7013b14]377 }
[eaf1e3d]378 }
[32fb6bce]379 fibril_mutex_unlock(&hc->guard);
[4c28d17]380 }
[68b9f148]381
382 if (status & I_UE) {
[a1732929]383 usb_log_fatal("Error like no other!");
[32fb6bce]384 hc_start(&hc->base);
[68b9f148]385 }
386
[41b96b4]387}
[76fbd9a]388
[02cacce]389/** Turn off any (BIOS)driver that might be in control of the device.
[78ab6d4]390 *
391 * This function implements routines described in chapter 5.1.1.3 of the OHCI
392 * specification (page 40, pdf page 54).
[02cacce]393 *
394 * @param[in] instance OHCI hc driver structure.
395 */
[32fb6bce]396int hc_gain_control(hc_device_t *hcd)
[2c617b0]397{
[32fb6bce]398 hc_t *instance = hcd_to_hc(hcd);
[78ab6d4]399
[a1732929]400 usb_log_debug("Requesting OHCI control.");
[bfc5c9dd]401 if (OHCI_RD(instance->registers->revision) & R_LEGACY_FLAG) {
[78ab6d4]402 /* Turn off legacy emulation, it should be enough to zero
403 * the lowest bit, but it caused problems. Thus clear all
404 * except GateA20 (causes restart on some hw).
405 * See page 145 of the specs for details.
406 */
407 volatile uint32_t *ohci_emulation_reg =
408 (uint32_t*)((char*)instance->registers + LEGACY_REGS_OFFSET);
[a1732929]409 usb_log_debug("OHCI legacy register %p: %x.",
[bfc5c9dd]410 ohci_emulation_reg, OHCI_RD(*ohci_emulation_reg));
[78ab6d4]411 /* Zero everything but A20State */
[58563585]412 // TODO: should we ack interrupts before doing this?
[bfc5c9dd]413 OHCI_CLR(*ohci_emulation_reg, ~0x100);
[78ab6d4]414 usb_log_debug(
[a1732929]415 "OHCI legacy register (should be 0 or 0x100) %p: %x.",
[bfc5c9dd]416 ohci_emulation_reg, OHCI_RD(*ohci_emulation_reg));
[78ab6d4]417 }
[112d159]418
[2c617b0]419 /* Interrupt routing enabled => smm driver is active */
[bfc5c9dd]420 if (OHCI_RD(instance->registers->control) & C_IR) {
[a1732929]421 usb_log_debug("SMM driver: request ownership change.");
[58563585]422 // TODO: should we ack interrupts before doing this?
[bfc5c9dd]423 OHCI_SET(instance->registers->command_status, CS_OCR);
[78ab6d4]424 /* Hope that SMM actually knows its stuff or we can hang here */
[f5bfd98]425 while (OHCI_RD(instance->registers->control) & C_IR) {
[2c617b0]426 async_usleep(1000);
427 }
[a1732929]428 usb_log_info("SMM driver: Ownership taken.");
[78ab6d4]429 C_HCFS_SET(instance->registers->control, C_HCFS_RESET);
[5d07f54]430 async_usleep(50000);
[32fb6bce]431 return EOK;
[2c617b0]432 }
[8486c07]433
[78ab6d4]434 const unsigned hc_status = C_HCFS_GET(instance->registers->control);
[2c617b0]435 /* Interrupt routing disabled && status != USB_RESET => BIOS active */
436 if (hc_status != C_HCFS_RESET) {
[a1732929]437 usb_log_debug("BIOS driver found.");
[2c617b0]438 if (hc_status == C_HCFS_OPERATIONAL) {
[a1732929]439 usb_log_info("BIOS driver: HC operational.");
[32fb6bce]440 return EOK;
[2c617b0]441 }
[bfc5c9dd]442 /* HC is suspended assert resume for 20ms */
[78ab6d4]443 C_HCFS_SET(instance->registers->control, C_HCFS_RESUME);
[2c617b0]444 async_usleep(20000);
[a1732929]445 usb_log_info("BIOS driver: HC resumed.");
[32fb6bce]446 return EOK;
[2c617b0]447 }
448
449 /* HC is in reset (hw startup) => no other driver
450 * maintain reset for at least the time specified in USB spec (50 ms)*/
[a1732929]451 usb_log_debug("Host controller found in reset state.");
[2c617b0]452 async_usleep(50000);
[32fb6bce]453 return EOK;
[2c617b0]454}
[76fbd9a]455
[02cacce]456/** OHCI hw initialization routine.
457 *
458 * @param[in] instance OHCI hc driver structure.
459 */
[32fb6bce]460int hc_start(hc_device_t *hcd)
[2c617b0]461{
[32fb6bce]462 hc_t *instance = hcd_to_hc(hcd);
[ee0ffa6]463 ohci_rh_init(&instance->rh, instance->registers, &instance->guard, "ohci rh");
[e4d7363]464
[112d159]465 /* OHCI guide page 42 */
[2c617b0]466 assert(instance);
[a1732929]467 usb_log_debug2("Started hc initialization routine.");
[112d159]468
469 /* Save contents of fm_interval register */
[bfc5c9dd]470 const uint32_t fm_interval = OHCI_RD(instance->registers->fm_interval);
[a1732929]471 usb_log_debug2("Old value of HcFmInterval: %x.", fm_interval);
[344925c]472
[112d159]473 /* Reset hc */
[a1732929]474 usb_log_debug2("HC reset.");
[112d159]475 size_t time = 0;
[bfc5c9dd]476 OHCI_WR(instance->registers->command_status, CS_HCR);
477 while (OHCI_RD(instance->registers->command_status) & CS_HCR) {
[112d159]478 async_usleep(10);
479 time += 10;
480 }
[a1732929]481 usb_log_debug2("HC reset complete in %zu us.", time);
[344925c]482
[112d159]483 /* Restore fm_interval */
[bfc5c9dd]484 OHCI_WR(instance->registers->fm_interval, fm_interval);
485 assert((OHCI_RD(instance->registers->command_status) & CS_HCR) == 0);
[344925c]486
[2c617b0]487 /* hc is now in suspend state */
[a1732929]488 usb_log_debug2("HC should be in suspend state(%x).",
[bfc5c9dd]489 OHCI_RD(instance->registers->control));
[344925c]490
[78d4e1f]491 /* Use HCCA */
[bfc5c9dd]492 OHCI_WR(instance->registers->hcca, addr_to_phys(instance->hcca));
[78d4e1f]493
494 /* Use queues */
[bfc5c9dd]495 OHCI_WR(instance->registers->bulk_head,
496 instance->lists[USB_TRANSFER_BULK].list_head_pa);
[a1732929]497 usb_log_debug2("Bulk HEAD set to: %p (%#" PRIx32 ").",
[5a2c42b]498 instance->lists[USB_TRANSFER_BULK].list_head,
499 instance->lists[USB_TRANSFER_BULK].list_head_pa);
[78d4e1f]500
[bfc5c9dd]501 OHCI_WR(instance->registers->control_head,
502 instance->lists[USB_TRANSFER_CONTROL].list_head_pa);
[a1732929]503 usb_log_debug2("Control HEAD set to: %p (%#" PRIx32 ").",
[5a2c42b]504 instance->lists[USB_TRANSFER_CONTROL].list_head,
505 instance->lists[USB_TRANSFER_CONTROL].list_head_pa);
[78d4e1f]506
[112d159]507 /* Enable queues */
[65eac7b]508 OHCI_SET(instance->registers->control, (C_PLE | C_IE | C_CLE | C_BLE));
[a1732929]509 usb_log_debug("Queues enabled(%x).",
[65eac7b]510 OHCI_RD(instance->registers->control));
[112d159]511
[561112f]512 /* Enable interrupts */
[32fb6bce]513 if (instance->base.irq_cap >= 0) {
[a5361fb]514 OHCI_WR(instance->registers->interrupt_enable,
515 OHCI_USED_INTERRUPTS);
[a1732929]516 usb_log_debug("Enabled interrupts: %x.",
[a5361fb]517 OHCI_RD(instance->registers->interrupt_enable));
518 OHCI_WR(instance->registers->interrupt_enable, I_MI);
519 }
[112d159]520
521 /* Set periodic start to 90% */
[bfc5c9dd]522 const uint32_t frame_length =
523 (fm_interval >> FMI_FI_SHIFT) & FMI_FI_MASK;
524 OHCI_WR(instance->registers->periodic_start,
525 ((frame_length / 10) * 9) & PS_MASK << PS_SHIFT);
[a1732929]526 usb_log_debug2("All periodic start set to: %x(%u - 90%% of %d).",
[bfc5c9dd]527 OHCI_RD(instance->registers->periodic_start),
528 OHCI_RD(instance->registers->periodic_start), frame_length);
[78ab6d4]529 C_HCFS_SET(instance->registers->control, C_HCFS_OPERATIONAL);
[a1732929]530 usb_log_debug("OHCI HC up and running (ctl_reg=0x%x).",
[bfc5c9dd]531 OHCI_RD(instance->registers->control));
[32fb6bce]532
533 return EOK;
[2c617b0]534}
[76fbd9a]535
[129b821f]536/**
537 * Setup roothub as a virtual hub.
538 */
539int hc_setup_roothub(hc_device_t *hcd)
540{
541 return hc_setup_virtual_root_hub(hcd, USB_SPEED_FULL);
542}
543
[02cacce]544/** Initialize schedule queues
545 *
546 * @param[in] instance OHCI hc driver structure
547 * @return Error code
548 */
[5a6cc679]549errno_t hc_init_transfer_lists(hc_t *instance)
[6b6e3ed3]550{
551 assert(instance);
[5a2c42b]552#define SETUP_ENDPOINT_LIST(type) \
[344925c]553do { \
[5a2c42b]554 const char *name = usb_str_transfer_type(type); \
[5a6cc679]555 const errno_t ret = endpoint_list_init(&instance->lists[type], name); \
[6b6e3ed3]556 if (ret != EOK) { \
[a1732929]557 usb_log_error("Failed to setup %s endpoint list: %s.", \
[1cb4f05]558 name, str_error(ret)); \
[68b9f148]559 endpoint_list_fini(&instance->lists[USB_TRANSFER_ISOCHRONOUS]);\
[5a2c42b]560 endpoint_list_fini(&instance->lists[USB_TRANSFER_INTERRUPT]); \
561 endpoint_list_fini(&instance->lists[USB_TRANSFER_CONTROL]); \
562 endpoint_list_fini(&instance->lists[USB_TRANSFER_BULK]); \
[70c85320]563 return ret; \
[344925c]564 } \
565} while (0)
[6b6e3ed3]566
[5a2c42b]567 SETUP_ENDPOINT_LIST(USB_TRANSFER_ISOCHRONOUS);
568 SETUP_ENDPOINT_LIST(USB_TRANSFER_INTERRUPT);
569 SETUP_ENDPOINT_LIST(USB_TRANSFER_CONTROL);
570 SETUP_ENDPOINT_LIST(USB_TRANSFER_BULK);
571#undef SETUP_ENDPOINT_LIST
572 endpoint_list_set_next(&instance->lists[USB_TRANSFER_INTERRUPT],
573 &instance->lists[USB_TRANSFER_ISOCHRONOUS]);
[6b6e3ed3]574
575 return EOK;
576}
[76fbd9a]577
[02cacce]578/** Initialize memory structures used by the OHCI hcd.
579 *
580 * @param[in] instance OHCI hc driver structure.
581 * @return Error code.
582 */
[5a6cc679]583errno_t hc_init_memory(hc_t *instance)
[344925c]584{
585 assert(instance);
[5d07f54]586
[acdb5bac]587 memset(&instance->rh, 0, sizeof(instance->rh));
[8790650]588 /* Init queues */
[5a6cc679]589 errno_t ret = hc_init_transfer_lists(instance);
[8953514]590 if (ret != EOK) {
591 return ret;
592 }
[344925c]593
[8790650]594 /*Init HCCA */
[f8dfb40]595 instance->hcca = hcca_get();
[344925c]596 if (instance->hcca == NULL)
597 return ENOMEM;
[a1732929]598 usb_log_debug2("OHCI HCCA initialized at %p.", instance->hcca);
[344925c]599
[1b90e90]600 for (unsigned i = 0; i < HCCA_INT_EP_COUNT; ++i) {
601 hcca_set_int_ep(instance->hcca, i,
[65eac7b]602 instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa);
[344925c]603 }
[a1732929]604 usb_log_debug2("Interrupt HEADs set to: %p (%#" PRIx32 ").",
[5a2c42b]605 instance->lists[USB_TRANSFER_INTERRUPT].list_head,
606 instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa);
[344925c]607
[32fb6bce]608 if ((ret = ohci_bus_init(&instance->bus, instance))) {
609 usb_log_error("HC(%p): Failed to setup bus : %s",
610 instance, str_error(ret));
611 return ret;
612 }
613
614 hc_device_setup(&instance->base, (bus_t *) &instance->bus);
615
[344925c]616 return EOK;
617}
[1ecc5de]618
[41b96b4]619/**
620 * @}
621 */
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