source: mainline/uspace/drv/bus/usb/ohci/hc.c@ 132ab5d1

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 132ab5d1 was 132ab5d1, checked in by Jenda <jenda.jzqk73@…>, 8 years ago

Merge commit '6a5d05bd2551e64111bea4f9332dd7448c26ce84' into forwardport

Separate return value from error code in gen_irq_code*().
  • Property mode set to 100644
File size: 17.5 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbohcihc
30 * @{
31 */
32/** @file
33 * @brief OHCI Host controller driver routines
34 */
35
36#include <assert.h>
37#include <async.h>
38#include <errno.h>
39#include <macros.h>
40#include <mem.h>
41#include <stdlib.h>
42#include <str_error.h>
43#include <stddef.h>
44#include <stdint.h>
45
46#include <usb/debug.h>
47#include <usb/host/utility.h>
48#include <usb/usb.h>
49
50#include "ohci_bus.h"
51#include "ohci_batch.h"
52
53#include "hc.h"
54
55#define OHCI_USED_INTERRUPTS \
56 (I_SO | I_WDH | I_UE | I_RHSC)
57
58static const irq_pio_range_t ohci_pio_ranges[] = {
59 {
60 .base = 0,
61 .size = sizeof(ohci_regs_t)
62 }
63};
64
65static const irq_cmd_t ohci_irq_commands[] = {
66 {
67 .cmd = CMD_PIO_READ_32,
68 .dstarg = 1,
69 .addr = NULL
70 },
71 {
72 .cmd = CMD_AND,
73 .srcarg = 1,
74 .dstarg = 2,
75 .value = 0
76 },
77 {
78 .cmd = CMD_PREDICATE,
79 .srcarg = 2,
80 .value = 2
81 },
82 {
83 .cmd = CMD_PIO_WRITE_A_32,
84 .srcarg = 1,
85 .addr = NULL
86 },
87 {
88 .cmd = CMD_ACCEPT
89 }
90};
91
92static int hc_init_transfer_lists(hc_t *instance);
93static int hc_init_memory(hc_t *instance);
94
95/** Generate IRQ code.
96 * @param[out] ranges PIO ranges buffer.
97 * @param[in] ranges_size Size of the ranges buffer (bytes).
98 * @param[out] cmds Commands buffer.
99 * @param[in] cmds_size Size of the commands buffer (bytes).
100 * @param[in] hw_res Device's resources.
101 *
102 * @return Error code.
103 */
104int hc_gen_irq_code(irq_code_t *code, hc_device_t *hcd, const hw_res_list_parsed_t *hw_res, int *irq)
105{
106 assert(code);
107 assert(hw_res);
108
109 if (hw_res->irqs.count != 1 || hw_res->mem_ranges.count != 1)
110 return EINVAL;
111
112 const addr_range_t regs = hw_res->mem_ranges.ranges[0];
113
114 if (RNGSZ(regs) < sizeof(ohci_regs_t))
115 return EOVERFLOW;
116
117 code->ranges = malloc(sizeof(ohci_pio_ranges));
118 if (code->ranges == NULL)
119 return ENOMEM;
120
121 code->cmds = malloc(sizeof(ohci_irq_commands));
122 if (code->cmds == NULL) {
123 free(code->ranges);
124 return ENOMEM;
125 }
126
127 code->rangecount = ARRAY_SIZE(ohci_pio_ranges);
128 code->cmdcount = ARRAY_SIZE(ohci_irq_commands);
129
130 memcpy(code->ranges, ohci_pio_ranges, sizeof(ohci_pio_ranges));
131 code->ranges[0].base = RNGABS(regs);
132
133 memcpy(code->cmds, ohci_irq_commands, sizeof(ohci_irq_commands));
134 ohci_regs_t *registers = (ohci_regs_t *) RNGABSPTR(regs);
135 code->cmds[0].addr = (void *) &registers->interrupt_status;
136 code->cmds[3].addr = (void *) &registers->interrupt_status;
137 OHCI_WR(code->cmds[1].value, OHCI_USED_INTERRUPTS);
138
139 usb_log_debug("Memory mapped regs at %p (size %zu), IRQ %d.",
140 RNGABSPTR(regs), RNGSZ(regs), hw_res->irqs.irqs[0]);
141
142 *irq = hw_res->irqs.irqs[0];
143 return EOK;
144}
145
146/** Initialize OHCI hc driver structure
147 *
148 * @param[in] instance Memory place for the structure.
149 * @param[in] regs Device's resources
150 * @param[in] interrupts True if w interrupts should be used
151 * @return Error code
152 */
153int hc_add(hc_device_t *hcd, const hw_res_list_parsed_t *hw_res)
154{
155 hc_t *instance = hcd_to_hc(hcd);
156 assert(hw_res);
157 if (hw_res->mem_ranges.count != 1 ||
158 hw_res->mem_ranges.ranges[0].size < sizeof(ohci_regs_t))
159 return EINVAL;
160
161 int ret = pio_enable_range(&hw_res->mem_ranges.ranges[0],
162 (void **) &instance->registers);
163 if (ret != EOK) {
164 usb_log_error("Failed to gain access to registers: %s.",
165 str_error(ret));
166 return ret;
167 }
168 usb_log_debug("Device registers at %" PRIx64 " (%zuB) accessible.",
169 hw_res->mem_ranges.ranges[0].address.absolute,
170 hw_res->mem_ranges.ranges[0].size);
171
172 list_initialize(&instance->pending_endpoints);
173 fibril_mutex_initialize(&instance->guard);
174
175 ret = hc_init_memory(instance);
176 if (ret != EOK) {
177 usb_log_error("Failed to create OHCI memory structures: %s.",
178 str_error(ret));
179 // TODO: We should disable pio access here
180 return ret;
181 }
182
183 return EOK;
184}
185
186/** Safely dispose host controller internal structures
187 *
188 * @param[in] instance Host controller structure to use.
189 */
190int hc_gone(hc_device_t *instance)
191{
192 assert(instance);
193 /* TODO: implement*/
194 return ENOTSUP;
195}
196
197void hc_enqueue_endpoint(hc_t *instance, const endpoint_t *ep)
198{
199 assert(instance);
200 assert(ep);
201
202 endpoint_list_t *list = &instance->lists[ep->transfer_type];
203 ohci_endpoint_t *ohci_ep = ohci_endpoint_get(ep);
204 assert(list);
205 assert(ohci_ep);
206
207 /* Enqueue ep */
208 switch (ep->transfer_type) {
209 case USB_TRANSFER_CONTROL:
210 OHCI_CLR(instance->registers->control, C_CLE);
211 endpoint_list_add_ep(list, ohci_ep);
212 OHCI_WR(instance->registers->control_current, 0);
213 OHCI_SET(instance->registers->control, C_CLE);
214 break;
215 case USB_TRANSFER_BULK:
216 OHCI_CLR(instance->registers->control, C_BLE);
217 endpoint_list_add_ep(list, ohci_ep);
218 OHCI_WR(instance->registers->bulk_current, 0);
219 OHCI_SET(instance->registers->control, C_BLE);
220 break;
221 case USB_TRANSFER_ISOCHRONOUS:
222 case USB_TRANSFER_INTERRUPT:
223 OHCI_CLR(instance->registers->control, C_PLE | C_IE);
224 endpoint_list_add_ep(list, ohci_ep);
225 OHCI_SET(instance->registers->control, C_PLE | C_IE);
226 break;
227 }
228}
229
230void hc_dequeue_endpoint(hc_t *instance, const endpoint_t *ep)
231{
232 assert(instance);
233 assert(ep);
234
235 /* Dequeue ep */
236 endpoint_list_t *list = &instance->lists[ep->transfer_type];
237 ohci_endpoint_t *ohci_ep = ohci_endpoint_get(ep);
238
239 assert(list);
240 assert(ohci_ep);
241 switch (ep->transfer_type) {
242 case USB_TRANSFER_CONTROL:
243 OHCI_CLR(instance->registers->control, C_CLE);
244 endpoint_list_remove_ep(list, ohci_ep);
245 OHCI_WR(instance->registers->control_current, 0);
246 OHCI_SET(instance->registers->control, C_CLE);
247 break;
248 case USB_TRANSFER_BULK:
249 OHCI_CLR(instance->registers->control, C_BLE);
250 endpoint_list_remove_ep(list, ohci_ep);
251 OHCI_WR(instance->registers->bulk_current, 0);
252 OHCI_SET(instance->registers->control, C_BLE);
253 break;
254 case USB_TRANSFER_ISOCHRONOUS:
255 case USB_TRANSFER_INTERRUPT:
256 OHCI_CLR(instance->registers->control, C_PLE | C_IE);
257 endpoint_list_remove_ep(list, ohci_ep);
258 OHCI_SET(instance->registers->control, C_PLE | C_IE);
259 break;
260 default:
261 break;
262 }
263}
264
265int ohci_hc_status(bus_t *bus_base, uint32_t *status)
266{
267 assert(bus_base);
268 assert(status);
269
270 ohci_bus_t *bus = (ohci_bus_t *) bus_base;
271 hc_t *hc = bus->hc;
272 assert(hc);
273
274 if (hc->registers){
275 *status = OHCI_RD(hc->registers->interrupt_status);
276 OHCI_WR(hc->registers->interrupt_status, *status);
277 }
278 return EOK;
279}
280
281/** Add USB transfer to the schedule.
282 *
283 * @param[in] hcd HCD driver structure.
284 * @param[in] batch Batch representing the transfer.
285 * @return Error code.
286 */
287int ohci_hc_schedule(usb_transfer_batch_t *batch)
288{
289 assert(batch);
290
291 ohci_bus_t *bus = (ohci_bus_t *) endpoint_get_bus(batch->ep);
292 hc_t *hc = bus->hc;
293 assert(hc);
294
295 /* Check for root hub communication */
296 if (batch->target.address == ohci_rh_get_address(&hc->rh)) {
297 usb_log_debug("OHCI root hub request.");
298 return ohci_rh_schedule(&hc->rh, batch);
299 }
300
301 endpoint_t *ep = batch->ep;
302 ohci_endpoint_t * const ohci_ep = ohci_endpoint_get(ep);
303 ohci_transfer_batch_t *ohci_batch = ohci_transfer_batch_get(batch);
304 int err;
305
306 fibril_mutex_lock(&hc->guard);
307 if ((err = endpoint_activate_locked(ep, batch))) {
308 fibril_mutex_unlock(&hc->guard);
309 return err;
310 }
311
312 if ((err = ohci_transfer_batch_prepare(ohci_batch)))
313 return err;
314
315 ohci_transfer_batch_commit(ohci_batch);
316 list_append(&ohci_ep->pending_link, &hc->pending_endpoints);
317 fibril_mutex_unlock(&hc->guard);
318
319 /* Control and bulk schedules need a kick to start working */
320 switch (batch->ep->transfer_type)
321 {
322 case USB_TRANSFER_CONTROL:
323 OHCI_SET(hc->registers->command_status, CS_CLF);
324 break;
325 case USB_TRANSFER_BULK:
326 OHCI_SET(hc->registers->command_status, CS_BLF);
327 break;
328 default:
329 break;
330 }
331
332 return EOK;
333}
334
335/** Interrupt handling routine
336 *
337 * @param[in] hcd HCD driver structure.
338 * @param[in] status Value of the status register at the time of interrupt.
339 */
340void ohci_hc_interrupt(bus_t *bus_base, uint32_t status)
341{
342 assert(bus_base);
343
344 ohci_bus_t *bus = (ohci_bus_t *) bus_base;
345 hc_t *hc = bus->hc;
346 assert(hc);
347
348 status = OHCI_RD(status);
349 assert(hc);
350 if ((status & ~I_SF) == 0) /* ignore sof status */
351 return;
352 usb_log_debug2("OHCI(%p) interrupt: %x.", hc, status);
353 if (status & I_RHSC)
354 ohci_rh_interrupt(&hc->rh);
355
356 if (status & I_WDH) {
357 fibril_mutex_lock(&hc->guard);
358 usb_log_debug2("HCCA: %p-%#" PRIx32 " (%p).", hc->hcca,
359 OHCI_RD(hc->registers->hcca),
360 (void *) addr_to_phys(hc->hcca));
361 usb_log_debug2("Periodic current: %#" PRIx32 ".",
362 OHCI_RD(hc->registers->periodic_current));
363
364 list_foreach_safe(hc->pending_endpoints, current, next) {
365 ohci_endpoint_t *ep
366 = list_get_instance(current, ohci_endpoint_t, pending_link);
367
368 ohci_transfer_batch_t *batch
369 = ohci_transfer_batch_get(ep->base.active_batch);
370 assert(batch);
371
372 if (ohci_transfer_batch_check_completed(batch)) {
373 endpoint_deactivate_locked(&ep->base);
374 list_remove(current);
375 hc_reset_toggles(&batch->base, &ohci_ep_toggle_reset);
376 usb_transfer_batch_finish(&batch->base);
377 }
378 }
379 fibril_mutex_unlock(&hc->guard);
380 }
381
382 if (status & I_UE) {
383 usb_log_fatal("Error like no other!");
384 hc_start(&hc->base);
385 }
386
387}
388
389/** Turn off any (BIOS)driver that might be in control of the device.
390 *
391 * This function implements routines described in chapter 5.1.1.3 of the OHCI
392 * specification (page 40, pdf page 54).
393 *
394 * @param[in] instance OHCI hc driver structure.
395 */
396int hc_gain_control(hc_device_t *hcd)
397{
398 hc_t *instance = hcd_to_hc(hcd);
399
400 usb_log_debug("Requesting OHCI control.");
401 if (OHCI_RD(instance->registers->revision) & R_LEGACY_FLAG) {
402 /* Turn off legacy emulation, it should be enough to zero
403 * the lowest bit, but it caused problems. Thus clear all
404 * except GateA20 (causes restart on some hw).
405 * See page 145 of the specs for details.
406 */
407 volatile uint32_t *ohci_emulation_reg =
408 (uint32_t*)((char*)instance->registers + LEGACY_REGS_OFFSET);
409 usb_log_debug("OHCI legacy register %p: %x.",
410 ohci_emulation_reg, OHCI_RD(*ohci_emulation_reg));
411 /* Zero everything but A20State */
412 // TODO: should we ack interrupts before doing this?
413 OHCI_CLR(*ohci_emulation_reg, ~0x100);
414 usb_log_debug(
415 "OHCI legacy register (should be 0 or 0x100) %p: %x.",
416 ohci_emulation_reg, OHCI_RD(*ohci_emulation_reg));
417 }
418
419 /* Interrupt routing enabled => smm driver is active */
420 if (OHCI_RD(instance->registers->control) & C_IR) {
421 usb_log_debug("SMM driver: request ownership change.");
422 // TODO: should we ack interrupts before doing this?
423 OHCI_SET(instance->registers->command_status, CS_OCR);
424 /* Hope that SMM actually knows its stuff or we can hang here */
425 while (OHCI_RD(instance->registers->control) & C_IR) {
426 async_usleep(1000);
427 }
428 usb_log_info("SMM driver: Ownership taken.");
429 C_HCFS_SET(instance->registers->control, C_HCFS_RESET);
430 async_usleep(50000);
431 return EOK;
432 }
433
434 const unsigned hc_status = C_HCFS_GET(instance->registers->control);
435 /* Interrupt routing disabled && status != USB_RESET => BIOS active */
436 if (hc_status != C_HCFS_RESET) {
437 usb_log_debug("BIOS driver found.");
438 if (hc_status == C_HCFS_OPERATIONAL) {
439 usb_log_info("BIOS driver: HC operational.");
440 return EOK;
441 }
442 /* HC is suspended assert resume for 20ms */
443 C_HCFS_SET(instance->registers->control, C_HCFS_RESUME);
444 async_usleep(20000);
445 usb_log_info("BIOS driver: HC resumed.");
446 return EOK;
447 }
448
449 /* HC is in reset (hw startup) => no other driver
450 * maintain reset for at least the time specified in USB spec (50 ms)*/
451 usb_log_debug("Host controller found in reset state.");
452 async_usleep(50000);
453 return EOK;
454}
455
456/** OHCI hw initialization routine.
457 *
458 * @param[in] instance OHCI hc driver structure.
459 */
460int hc_start(hc_device_t *hcd)
461{
462 hc_t *instance = hcd_to_hc(hcd);
463 ohci_rh_init(&instance->rh, instance->registers, &instance->guard, "ohci rh");
464
465 /* OHCI guide page 42 */
466 assert(instance);
467 usb_log_debug2("Started hc initialization routine.");
468
469 /* Save contents of fm_interval register */
470 const uint32_t fm_interval = OHCI_RD(instance->registers->fm_interval);
471 usb_log_debug2("Old value of HcFmInterval: %x.", fm_interval);
472
473 /* Reset hc */
474 usb_log_debug2("HC reset.");
475 size_t time = 0;
476 OHCI_WR(instance->registers->command_status, CS_HCR);
477 while (OHCI_RD(instance->registers->command_status) & CS_HCR) {
478 async_usleep(10);
479 time += 10;
480 }
481 usb_log_debug2("HC reset complete in %zu us.", time);
482
483 /* Restore fm_interval */
484 OHCI_WR(instance->registers->fm_interval, fm_interval);
485 assert((OHCI_RD(instance->registers->command_status) & CS_HCR) == 0);
486
487 /* hc is now in suspend state */
488 usb_log_debug2("HC should be in suspend state(%x).",
489 OHCI_RD(instance->registers->control));
490
491 /* Use HCCA */
492 OHCI_WR(instance->registers->hcca, addr_to_phys(instance->hcca));
493
494 /* Use queues */
495 OHCI_WR(instance->registers->bulk_head,
496 instance->lists[USB_TRANSFER_BULK].list_head_pa);
497 usb_log_debug2("Bulk HEAD set to: %p (%#" PRIx32 ").",
498 instance->lists[USB_TRANSFER_BULK].list_head,
499 instance->lists[USB_TRANSFER_BULK].list_head_pa);
500
501 OHCI_WR(instance->registers->control_head,
502 instance->lists[USB_TRANSFER_CONTROL].list_head_pa);
503 usb_log_debug2("Control HEAD set to: %p (%#" PRIx32 ").",
504 instance->lists[USB_TRANSFER_CONTROL].list_head,
505 instance->lists[USB_TRANSFER_CONTROL].list_head_pa);
506
507 /* Enable queues */
508 OHCI_SET(instance->registers->control, (C_PLE | C_IE | C_CLE | C_BLE));
509 usb_log_debug("Queues enabled(%x).",
510 OHCI_RD(instance->registers->control));
511
512 /* Enable interrupts */
513 if (instance->base.irq_cap >= 0) {
514 OHCI_WR(instance->registers->interrupt_enable,
515 OHCI_USED_INTERRUPTS);
516 usb_log_debug("Enabled interrupts: %x.",
517 OHCI_RD(instance->registers->interrupt_enable));
518 OHCI_WR(instance->registers->interrupt_enable, I_MI);
519 }
520
521 /* Set periodic start to 90% */
522 const uint32_t frame_length =
523 (fm_interval >> FMI_FI_SHIFT) & FMI_FI_MASK;
524 OHCI_WR(instance->registers->periodic_start,
525 ((frame_length / 10) * 9) & PS_MASK << PS_SHIFT);
526 usb_log_debug2("All periodic start set to: %x(%u - 90%% of %d).",
527 OHCI_RD(instance->registers->periodic_start),
528 OHCI_RD(instance->registers->periodic_start), frame_length);
529 C_HCFS_SET(instance->registers->control, C_HCFS_OPERATIONAL);
530 usb_log_debug("OHCI HC up and running (ctl_reg=0x%x).",
531 OHCI_RD(instance->registers->control));
532
533 return EOK;
534}
535
536/**
537 * Setup roothub as a virtual hub.
538 */
539int hc_setup_roothub(hc_device_t *hcd)
540{
541 return hc_setup_virtual_root_hub(hcd, USB_SPEED_FULL);
542}
543
544/** Initialize schedule queues
545 *
546 * @param[in] instance OHCI hc driver structure
547 * @return Error code
548 */
549int hc_init_transfer_lists(hc_t *instance)
550{
551 assert(instance);
552#define SETUP_ENDPOINT_LIST(type) \
553do { \
554 const char *name = usb_str_transfer_type(type); \
555 const int ret = endpoint_list_init(&instance->lists[type], name); \
556 if (ret != EOK) { \
557 usb_log_error("Failed to setup %s endpoint list: %s.", \
558 name, str_error(ret)); \
559 endpoint_list_fini(&instance->lists[USB_TRANSFER_ISOCHRONOUS]);\
560 endpoint_list_fini(&instance->lists[USB_TRANSFER_INTERRUPT]); \
561 endpoint_list_fini(&instance->lists[USB_TRANSFER_CONTROL]); \
562 endpoint_list_fini(&instance->lists[USB_TRANSFER_BULK]); \
563 return ret; \
564 } \
565} while (0)
566
567 SETUP_ENDPOINT_LIST(USB_TRANSFER_ISOCHRONOUS);
568 SETUP_ENDPOINT_LIST(USB_TRANSFER_INTERRUPT);
569 SETUP_ENDPOINT_LIST(USB_TRANSFER_CONTROL);
570 SETUP_ENDPOINT_LIST(USB_TRANSFER_BULK);
571#undef SETUP_ENDPOINT_LIST
572 endpoint_list_set_next(&instance->lists[USB_TRANSFER_INTERRUPT],
573 &instance->lists[USB_TRANSFER_ISOCHRONOUS]);
574
575 return EOK;
576}
577
578/** Initialize memory structures used by the OHCI hcd.
579 *
580 * @param[in] instance OHCI hc driver structure.
581 * @return Error code.
582 */
583int hc_init_memory(hc_t *instance)
584{
585 assert(instance);
586
587 memset(&instance->rh, 0, sizeof(instance->rh));
588 /* Init queues */
589 int ret = hc_init_transfer_lists(instance);
590 if (ret != EOK) {
591 return ret;
592 }
593
594 /*Init HCCA */
595 instance->hcca = hcca_get();
596 if (instance->hcca == NULL)
597 return ENOMEM;
598 usb_log_debug2("OHCI HCCA initialized at %p.", instance->hcca);
599
600 for (unsigned i = 0; i < HCCA_INT_EP_COUNT; ++i) {
601 hcca_set_int_ep(instance->hcca, i,
602 instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa);
603 }
604 usb_log_debug2("Interrupt HEADs set to: %p (%#" PRIx32 ").",
605 instance->lists[USB_TRANSFER_INTERRUPT].list_head,
606 instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa);
607
608 if ((ret = ohci_bus_init(&instance->bus, instance))) {
609 usb_log_error("HC(%p): Failed to setup bus : %s",
610 instance, str_error(ret));
611 return ret;
612 }
613
614 hc_device_setup(&instance->base, (bus_t *) &instance->bus);
615
616 return EOK;
617}
618
619/**
620 * @}
621 */
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