| 1 | /*
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| 2 | * Copyright (c) 2011 Jan Vesely
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | /** @addtogroup drvusbohcihc
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| 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | * @brief OHCI Host controller driver routines
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| 34 | */
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| 35 |
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| 36 | #include <assert.h>
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| 37 | #include <async.h>
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| 38 | #include <errno.h>
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| 39 | #include <macros.h>
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| 40 | #include <mem.h>
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| 41 | #include <stdlib.h>
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| 42 | #include <str_error.h>
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| 43 | #include <stddef.h>
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| 44 | #include <stdint.h>
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| 45 |
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| 46 | #include <usb/debug.h>
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| 47 | #include <usb/host/utility.h>
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| 48 | #include <usb/usb.h>
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| 49 |
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| 50 | #include "ohci_bus.h"
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| 51 | #include "ohci_batch.h"
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| 52 |
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| 53 | #include "hc.h"
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| 54 |
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| 55 | #define OHCI_USED_INTERRUPTS \
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| 56 | (I_SO | I_WDH | I_UE | I_RHSC)
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| 57 |
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| 58 | static const irq_pio_range_t ohci_pio_ranges[] = {
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| 59 | {
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| 60 | .base = 0,
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| 61 | .size = sizeof(ohci_regs_t)
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| 62 | }
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| 63 | };
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| 64 |
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| 65 | static const irq_cmd_t ohci_irq_commands[] = {
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| 66 | {
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| 67 | .cmd = CMD_PIO_READ_32,
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| 68 | .dstarg = 1,
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| 69 | .addr = NULL
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| 70 | },
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| 71 | {
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| 72 | .cmd = CMD_AND,
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| 73 | .srcarg = 1,
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| 74 | .dstarg = 2,
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| 75 | .value = 0
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| 76 | },
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| 77 | {
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| 78 | .cmd = CMD_PREDICATE,
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| 79 | .srcarg = 2,
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| 80 | .value = 2
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| 81 | },
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| 82 | {
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| 83 | .cmd = CMD_PIO_WRITE_A_32,
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| 84 | .srcarg = 1,
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| 85 | .addr = NULL
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| 86 | },
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| 87 | {
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| 88 | .cmd = CMD_ACCEPT
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| 89 | }
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| 90 | };
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| 91 |
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| 92 | static errno_t hc_init_transfer_lists(hc_t *instance);
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| 93 | static errno_t hc_init_memory(hc_t *instance);
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| 94 |
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| 95 | /** Generate IRQ code.
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| 96 | * @param[out] ranges PIO ranges buffer.
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| 97 | * @param[in] ranges_size Size of the ranges buffer (bytes).
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| 98 | * @param[out] cmds Commands buffer.
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| 99 | * @param[in] cmds_size Size of the commands buffer (bytes).
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| 100 | * @param[in] hw_res Device's resources.
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| 101 | *
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| 102 | * @return Error code.
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| 103 | */
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| 104 | errno_t hc_gen_irq_code(irq_code_t *code, hc_device_t *hcd, const hw_res_list_parsed_t *hw_res, int *irq)
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| 105 | {
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| 106 | assert(code);
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| 107 | assert(hw_res);
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| 108 |
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| 109 | if (hw_res->irqs.count != 1 || hw_res->mem_ranges.count != 1)
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| 110 | return EINVAL;
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| 111 |
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| 112 | const addr_range_t regs = hw_res->mem_ranges.ranges[0];
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| 113 |
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| 114 | if (RNGSZ(regs) < sizeof(ohci_regs_t))
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| 115 | return EOVERFLOW;
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| 116 |
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| 117 | code->ranges = malloc(sizeof(ohci_pio_ranges));
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| 118 | if (code->ranges == NULL)
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| 119 | return ENOMEM;
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| 120 |
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| 121 | code->cmds = malloc(sizeof(ohci_irq_commands));
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| 122 | if (code->cmds == NULL) {
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| 123 | free(code->ranges);
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| 124 | return ENOMEM;
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| 125 | }
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| 126 |
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| 127 | code->rangecount = ARRAY_SIZE(ohci_pio_ranges);
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| 128 | code->cmdcount = ARRAY_SIZE(ohci_irq_commands);
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| 129 |
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| 130 | memcpy(code->ranges, ohci_pio_ranges, sizeof(ohci_pio_ranges));
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| 131 | code->ranges[0].base = RNGABS(regs);
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| 132 |
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| 133 | memcpy(code->cmds, ohci_irq_commands, sizeof(ohci_irq_commands));
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| 134 | ohci_regs_t *registers = (ohci_regs_t *) RNGABSPTR(regs);
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| 135 | code->cmds[0].addr = (void *) ®isters->interrupt_status;
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| 136 | code->cmds[3].addr = (void *) ®isters->interrupt_status;
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| 137 | OHCI_WR(code->cmds[1].value, OHCI_USED_INTERRUPTS);
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| 138 |
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| 139 | usb_log_debug("Memory mapped regs at %p (size %zu), IRQ %d.",
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| 140 | RNGABSPTR(regs), RNGSZ(regs), hw_res->irqs.irqs[0]);
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| 141 |
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| 142 | *irq = hw_res->irqs.irqs[0];
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| 143 | return EOK;
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| 144 | }
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| 145 |
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| 146 | /** Initialize OHCI hc driver structure
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| 147 | *
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| 148 | * @param[in] instance Memory place for the structure.
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| 149 | * @param[in] regs Device's resources
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| 150 | * @param[in] interrupts True if w interrupts should be used
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| 151 | * @return Error code
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| 152 | */
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| 153 | errno_t hc_add(hc_device_t *hcd, const hw_res_list_parsed_t *hw_res)
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| 154 | {
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| 155 | hc_t *instance = hcd_to_hc(hcd);
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| 156 | assert(hw_res);
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| 157 | if (hw_res->mem_ranges.count != 1 ||
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| 158 | hw_res->mem_ranges.ranges[0].size < sizeof(ohci_regs_t))
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| 159 | return EINVAL;
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| 160 |
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| 161 | errno_t ret = pio_enable_range(&hw_res->mem_ranges.ranges[0],
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| 162 | (void **) &instance->registers);
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| 163 | if (ret != EOK) {
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| 164 | usb_log_error("Failed to gain access to registers: %s.",
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| 165 | str_error(ret));
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| 166 | return ret;
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| 167 | }
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| 168 | usb_log_debug("Device registers at %" PRIx64 " (%zuB) accessible.",
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| 169 | hw_res->mem_ranges.ranges[0].address.absolute,
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| 170 | hw_res->mem_ranges.ranges[0].size);
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| 171 |
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| 172 | list_initialize(&instance->pending_endpoints);
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| 173 | fibril_mutex_initialize(&instance->guard);
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| 174 |
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| 175 | ret = hc_init_memory(instance);
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| 176 | if (ret != EOK) {
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| 177 | usb_log_error("Failed to create OHCI memory structures: %s.",
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| 178 | str_error(ret));
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| 179 | // TODO: We should disable pio access here
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| 180 | return ret;
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| 181 | }
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| 182 |
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| 183 | return EOK;
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| 184 | }
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| 185 |
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| 186 | /** Safely dispose host controller internal structures
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| 187 | *
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| 188 | * @param[in] instance Host controller structure to use.
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| 189 | */
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| 190 | int hc_gone(hc_device_t *instance)
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| 191 | {
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| 192 | assert(instance);
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| 193 | /* TODO: implement*/
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| 194 | return ENOTSUP;
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| 195 | }
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| 196 |
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| 197 | void hc_enqueue_endpoint(hc_t *instance, const endpoint_t *ep)
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| 198 | {
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| 199 | assert(instance);
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| 200 | assert(ep);
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| 201 |
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| 202 | endpoint_list_t *list = &instance->lists[ep->transfer_type];
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| 203 | ohci_endpoint_t *ohci_ep = ohci_endpoint_get(ep);
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| 204 | assert(list);
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| 205 | assert(ohci_ep);
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| 206 |
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| 207 | /* Enqueue ep */
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| 208 | switch (ep->transfer_type) {
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| 209 | case USB_TRANSFER_CONTROL:
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| 210 | OHCI_CLR(instance->registers->control, C_CLE);
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| 211 | endpoint_list_add_ep(list, ohci_ep);
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| 212 | OHCI_WR(instance->registers->control_current, 0);
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| 213 | OHCI_SET(instance->registers->control, C_CLE);
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| 214 | break;
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| 215 | case USB_TRANSFER_BULK:
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| 216 | OHCI_CLR(instance->registers->control, C_BLE);
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| 217 | endpoint_list_add_ep(list, ohci_ep);
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| 218 | OHCI_WR(instance->registers->bulk_current, 0);
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| 219 | OHCI_SET(instance->registers->control, C_BLE);
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| 220 | break;
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| 221 | case USB_TRANSFER_ISOCHRONOUS:
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| 222 | case USB_TRANSFER_INTERRUPT:
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| 223 | OHCI_CLR(instance->registers->control, C_PLE | C_IE);
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| 224 | endpoint_list_add_ep(list, ohci_ep);
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| 225 | OHCI_SET(instance->registers->control, C_PLE | C_IE);
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| 226 | break;
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| 227 | }
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| 228 | }
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| 229 |
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| 230 | void hc_dequeue_endpoint(hc_t *instance, const endpoint_t *ep)
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| 231 | {
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| 232 | assert(instance);
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| 233 | assert(ep);
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| 234 |
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| 235 | /* Dequeue ep */
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| 236 | endpoint_list_t *list = &instance->lists[ep->transfer_type];
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| 237 | ohci_endpoint_t *ohci_ep = ohci_endpoint_get(ep);
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| 238 |
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| 239 | assert(list);
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| 240 | assert(ohci_ep);
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| 241 | switch (ep->transfer_type) {
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| 242 | case USB_TRANSFER_CONTROL:
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| 243 | OHCI_CLR(instance->registers->control, C_CLE);
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| 244 | endpoint_list_remove_ep(list, ohci_ep);
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| 245 | OHCI_WR(instance->registers->control_current, 0);
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| 246 | OHCI_SET(instance->registers->control, C_CLE);
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| 247 | break;
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| 248 | case USB_TRANSFER_BULK:
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| 249 | OHCI_CLR(instance->registers->control, C_BLE);
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| 250 | endpoint_list_remove_ep(list, ohci_ep);
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| 251 | OHCI_WR(instance->registers->bulk_current, 0);
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| 252 | OHCI_SET(instance->registers->control, C_BLE);
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| 253 | break;
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| 254 | case USB_TRANSFER_ISOCHRONOUS:
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| 255 | case USB_TRANSFER_INTERRUPT:
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| 256 | OHCI_CLR(instance->registers->control, C_PLE | C_IE);
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| 257 | endpoint_list_remove_ep(list, ohci_ep);
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| 258 | OHCI_SET(instance->registers->control, C_PLE | C_IE);
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| 259 | break;
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| 260 | default:
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| 261 | break;
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| 262 | }
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| 263 | }
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| 264 |
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| 265 | errno_t ohci_hc_status(bus_t *bus_base, uint32_t *status)
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| 266 | {
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| 267 | assert(bus_base);
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| 268 | assert(status);
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| 269 |
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| 270 | ohci_bus_t *bus = (ohci_bus_t *) bus_base;
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| 271 | hc_t *hc = bus->hc;
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| 272 | assert(hc);
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| 273 |
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| 274 | if (hc->registers){
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| 275 | *status = OHCI_RD(hc->registers->interrupt_status);
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| 276 | OHCI_WR(hc->registers->interrupt_status, *status);
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| 277 | }
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| 278 | return EOK;
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| 279 | }
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| 280 |
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| 281 | /** Add USB transfer to the schedule.
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| 282 | *
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| 283 | * @param[in] hcd HCD driver structure.
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| 284 | * @param[in] batch Batch representing the transfer.
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| 285 | * @return Error code.
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| 286 | */
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| 287 | errno_t ohci_hc_schedule(usb_transfer_batch_t *batch)
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| 288 | {
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| 289 | assert(batch);
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| 290 |
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| 291 | ohci_bus_t *bus = (ohci_bus_t *) endpoint_get_bus(batch->ep);
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| 292 | hc_t *hc = bus->hc;
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| 293 | assert(hc);
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| 294 |
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| 295 | /* Check for root hub communication */
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| 296 | if (batch->target.address == ohci_rh_get_address(&hc->rh)) {
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| 297 | usb_log_debug("OHCI root hub request.");
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| 298 | return ohci_rh_schedule(&hc->rh, batch);
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| 299 | }
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| 300 |
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| 301 | endpoint_t *ep = batch->ep;
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| 302 | ohci_endpoint_t * const ohci_ep = ohci_endpoint_get(ep);
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| 303 | ohci_transfer_batch_t *ohci_batch = ohci_transfer_batch_get(batch);
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| 304 | int err;
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| 305 |
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| 306 | fibril_mutex_lock(&hc->guard);
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| 307 | if ((err = endpoint_activate_locked(ep, batch))) {
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| 308 | fibril_mutex_unlock(&hc->guard);
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| 309 | return err;
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| 310 | }
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| 311 |
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| 312 | if ((err = ohci_transfer_batch_prepare(ohci_batch)))
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| 313 | return err;
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| 314 |
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| 315 | ohci_transfer_batch_commit(ohci_batch);
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| 316 | list_append(&ohci_ep->pending_link, &hc->pending_endpoints);
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| 317 | fibril_mutex_unlock(&hc->guard);
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| 318 |
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| 319 | /* Control and bulk schedules need a kick to start working */
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| 320 | switch (batch->ep->transfer_type)
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| 321 | {
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| 322 | case USB_TRANSFER_CONTROL:
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| 323 | OHCI_SET(hc->registers->command_status, CS_CLF);
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| 324 | break;
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| 325 | case USB_TRANSFER_BULK:
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| 326 | OHCI_SET(hc->registers->command_status, CS_BLF);
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| 327 | break;
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| 328 | default:
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| 329 | break;
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| 330 | }
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| 331 |
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| 332 | return EOK;
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| 333 | }
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| 334 |
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| 335 | /** Interrupt handling routine
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| 336 | *
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| 337 | * @param[in] hcd HCD driver structure.
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| 338 | * @param[in] status Value of the status register at the time of interrupt.
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| 339 | */
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| 340 | void ohci_hc_interrupt(bus_t *bus_base, uint32_t status)
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| 341 | {
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| 342 | assert(bus_base);
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| 343 |
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| 344 | ohci_bus_t *bus = (ohci_bus_t *) bus_base;
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| 345 | hc_t *hc = bus->hc;
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| 346 | assert(hc);
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| 347 |
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| 348 | status = OHCI_RD(status);
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| 349 | assert(hc);
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| 350 | if ((status & ~I_SF) == 0) /* ignore sof status */
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| 351 | return;
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| 352 | usb_log_debug2("OHCI(%p) interrupt: %x.", hc, status);
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| 353 | if (status & I_RHSC)
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| 354 | ohci_rh_interrupt(&hc->rh);
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| 355 |
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| 356 | if (status & I_WDH) {
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| 357 | fibril_mutex_lock(&hc->guard);
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| 358 | usb_log_debug2("HCCA: %p-%#" PRIx32 " (%p).", hc->hcca,
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| 359 | OHCI_RD(hc->registers->hcca),
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| 360 | (void *) addr_to_phys(hc->hcca));
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| 361 | usb_log_debug2("Periodic current: %#" PRIx32 ".",
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| 362 | OHCI_RD(hc->registers->periodic_current));
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| 363 |
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| 364 | list_foreach_safe(hc->pending_endpoints, current, next) {
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| 365 | ohci_endpoint_t *ep
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| 366 | = list_get_instance(current, ohci_endpoint_t, pending_link);
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| 367 |
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| 368 | ohci_transfer_batch_t *batch
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| 369 | = ohci_transfer_batch_get(ep->base.active_batch);
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| 370 | assert(batch);
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| 371 |
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| 372 | if (ohci_transfer_batch_check_completed(batch)) {
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| 373 | endpoint_deactivate_locked(&ep->base);
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| 374 | list_remove(current);
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| 375 | hc_reset_toggles(&batch->base, &ohci_ep_toggle_reset);
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| 376 | usb_transfer_batch_finish(&batch->base);
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| 377 | }
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| 378 | }
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| 379 | fibril_mutex_unlock(&hc->guard);
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| 380 | }
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| 381 |
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| 382 | if (status & I_UE) {
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| 383 | usb_log_fatal("Error like no other!");
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| 384 | hc_start(&hc->base);
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| 385 | }
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| 386 |
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| 387 | }
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| 388 |
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| 389 | /** Turn off any (BIOS)driver that might be in control of the device.
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| 390 | *
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| 391 | * This function implements routines described in chapter 5.1.1.3 of the OHCI
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| 392 | * specification (page 40, pdf page 54).
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| 393 | *
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| 394 | * @param[in] instance OHCI hc driver structure.
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| 395 | */
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| 396 | int hc_gain_control(hc_device_t *hcd)
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| 397 | {
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| 398 | hc_t *instance = hcd_to_hc(hcd);
|
|---|
| 399 |
|
|---|
| 400 | usb_log_debug("Requesting OHCI control.");
|
|---|
| 401 | if (OHCI_RD(instance->registers->revision) & R_LEGACY_FLAG) {
|
|---|
| 402 | /* Turn off legacy emulation, it should be enough to zero
|
|---|
| 403 | * the lowest bit, but it caused problems. Thus clear all
|
|---|
| 404 | * except GateA20 (causes restart on some hw).
|
|---|
| 405 | * See page 145 of the specs for details.
|
|---|
| 406 | */
|
|---|
| 407 | volatile uint32_t *ohci_emulation_reg =
|
|---|
| 408 | (uint32_t*)((char*)instance->registers + LEGACY_REGS_OFFSET);
|
|---|
| 409 | usb_log_debug("OHCI legacy register %p: %x.",
|
|---|
| 410 | ohci_emulation_reg, OHCI_RD(*ohci_emulation_reg));
|
|---|
| 411 | /* Zero everything but A20State */
|
|---|
| 412 | // TODO: should we ack interrupts before doing this?
|
|---|
| 413 | OHCI_CLR(*ohci_emulation_reg, ~0x100);
|
|---|
| 414 | usb_log_debug(
|
|---|
| 415 | "OHCI legacy register (should be 0 or 0x100) %p: %x.",
|
|---|
| 416 | ohci_emulation_reg, OHCI_RD(*ohci_emulation_reg));
|
|---|
| 417 | }
|
|---|
| 418 |
|
|---|
| 419 | /* Interrupt routing enabled => smm driver is active */
|
|---|
| 420 | if (OHCI_RD(instance->registers->control) & C_IR) {
|
|---|
| 421 | usb_log_debug("SMM driver: request ownership change.");
|
|---|
| 422 | // TODO: should we ack interrupts before doing this?
|
|---|
| 423 | OHCI_SET(instance->registers->command_status, CS_OCR);
|
|---|
| 424 | /* Hope that SMM actually knows its stuff or we can hang here */
|
|---|
| 425 | while (OHCI_RD(instance->registers->control) & C_IR) {
|
|---|
| 426 | async_usleep(1000);
|
|---|
| 427 | }
|
|---|
| 428 | usb_log_info("SMM driver: Ownership taken.");
|
|---|
| 429 | C_HCFS_SET(instance->registers->control, C_HCFS_RESET);
|
|---|
| 430 | async_usleep(50000);
|
|---|
| 431 | return EOK;
|
|---|
| 432 | }
|
|---|
| 433 |
|
|---|
| 434 | const unsigned hc_status = C_HCFS_GET(instance->registers->control);
|
|---|
| 435 | /* Interrupt routing disabled && status != USB_RESET => BIOS active */
|
|---|
| 436 | if (hc_status != C_HCFS_RESET) {
|
|---|
| 437 | usb_log_debug("BIOS driver found.");
|
|---|
| 438 | if (hc_status == C_HCFS_OPERATIONAL) {
|
|---|
| 439 | usb_log_info("BIOS driver: HC operational.");
|
|---|
| 440 | return EOK;
|
|---|
| 441 | }
|
|---|
| 442 | /* HC is suspended assert resume for 20ms */
|
|---|
| 443 | C_HCFS_SET(instance->registers->control, C_HCFS_RESUME);
|
|---|
| 444 | async_usleep(20000);
|
|---|
| 445 | usb_log_info("BIOS driver: HC resumed.");
|
|---|
| 446 | return EOK;
|
|---|
| 447 | }
|
|---|
| 448 |
|
|---|
| 449 | /* HC is in reset (hw startup) => no other driver
|
|---|
| 450 | * maintain reset for at least the time specified in USB spec (50 ms)*/
|
|---|
| 451 | usb_log_debug("Host controller found in reset state.");
|
|---|
| 452 | async_usleep(50000);
|
|---|
| 453 | return EOK;
|
|---|
| 454 | }
|
|---|
| 455 |
|
|---|
| 456 | /** OHCI hw initialization routine.
|
|---|
| 457 | *
|
|---|
| 458 | * @param[in] instance OHCI hc driver structure.
|
|---|
| 459 | */
|
|---|
| 460 | int hc_start(hc_device_t *hcd)
|
|---|
| 461 | {
|
|---|
| 462 | hc_t *instance = hcd_to_hc(hcd);
|
|---|
| 463 | ohci_rh_init(&instance->rh, instance->registers, &instance->guard, "ohci rh");
|
|---|
| 464 |
|
|---|
| 465 | /* OHCI guide page 42 */
|
|---|
| 466 | assert(instance);
|
|---|
| 467 | usb_log_debug2("Started hc initialization routine.");
|
|---|
| 468 |
|
|---|
| 469 | /* Save contents of fm_interval register */
|
|---|
| 470 | const uint32_t fm_interval = OHCI_RD(instance->registers->fm_interval);
|
|---|
| 471 | usb_log_debug2("Old value of HcFmInterval: %x.", fm_interval);
|
|---|
| 472 |
|
|---|
| 473 | /* Reset hc */
|
|---|
| 474 | usb_log_debug2("HC reset.");
|
|---|
| 475 | size_t time = 0;
|
|---|
| 476 | OHCI_WR(instance->registers->command_status, CS_HCR);
|
|---|
| 477 | while (OHCI_RD(instance->registers->command_status) & CS_HCR) {
|
|---|
| 478 | async_usleep(10);
|
|---|
| 479 | time += 10;
|
|---|
| 480 | }
|
|---|
| 481 | usb_log_debug2("HC reset complete in %zu us.", time);
|
|---|
| 482 |
|
|---|
| 483 | /* Restore fm_interval */
|
|---|
| 484 | OHCI_WR(instance->registers->fm_interval, fm_interval);
|
|---|
| 485 | assert((OHCI_RD(instance->registers->command_status) & CS_HCR) == 0);
|
|---|
| 486 |
|
|---|
| 487 | /* hc is now in suspend state */
|
|---|
| 488 | usb_log_debug2("HC should be in suspend state(%x).",
|
|---|
| 489 | OHCI_RD(instance->registers->control));
|
|---|
| 490 |
|
|---|
| 491 | /* Use HCCA */
|
|---|
| 492 | OHCI_WR(instance->registers->hcca, addr_to_phys(instance->hcca));
|
|---|
| 493 |
|
|---|
| 494 | /* Use queues */
|
|---|
| 495 | OHCI_WR(instance->registers->bulk_head,
|
|---|
| 496 | instance->lists[USB_TRANSFER_BULK].list_head_pa);
|
|---|
| 497 | usb_log_debug2("Bulk HEAD set to: %p (%#" PRIx32 ").",
|
|---|
| 498 | instance->lists[USB_TRANSFER_BULK].list_head,
|
|---|
| 499 | instance->lists[USB_TRANSFER_BULK].list_head_pa);
|
|---|
| 500 |
|
|---|
| 501 | OHCI_WR(instance->registers->control_head,
|
|---|
| 502 | instance->lists[USB_TRANSFER_CONTROL].list_head_pa);
|
|---|
| 503 | usb_log_debug2("Control HEAD set to: %p (%#" PRIx32 ").",
|
|---|
| 504 | instance->lists[USB_TRANSFER_CONTROL].list_head,
|
|---|
| 505 | instance->lists[USB_TRANSFER_CONTROL].list_head_pa);
|
|---|
| 506 |
|
|---|
| 507 | /* Enable queues */
|
|---|
| 508 | OHCI_SET(instance->registers->control, (C_PLE | C_IE | C_CLE | C_BLE));
|
|---|
| 509 | usb_log_debug("Queues enabled(%x).",
|
|---|
| 510 | OHCI_RD(instance->registers->control));
|
|---|
| 511 |
|
|---|
| 512 | /* Enable interrupts */
|
|---|
| 513 | if (instance->base.irq_cap >= 0) {
|
|---|
| 514 | OHCI_WR(instance->registers->interrupt_enable,
|
|---|
| 515 | OHCI_USED_INTERRUPTS);
|
|---|
| 516 | usb_log_debug("Enabled interrupts: %x.",
|
|---|
| 517 | OHCI_RD(instance->registers->interrupt_enable));
|
|---|
| 518 | OHCI_WR(instance->registers->interrupt_enable, I_MI);
|
|---|
| 519 | }
|
|---|
| 520 |
|
|---|
| 521 | /* Set periodic start to 90% */
|
|---|
| 522 | const uint32_t frame_length =
|
|---|
| 523 | (fm_interval >> FMI_FI_SHIFT) & FMI_FI_MASK;
|
|---|
| 524 | OHCI_WR(instance->registers->periodic_start,
|
|---|
| 525 | ((frame_length / 10) * 9) & PS_MASK << PS_SHIFT);
|
|---|
| 526 | usb_log_debug2("All periodic start set to: %x(%u - 90%% of %d).",
|
|---|
| 527 | OHCI_RD(instance->registers->periodic_start),
|
|---|
| 528 | OHCI_RD(instance->registers->periodic_start), frame_length);
|
|---|
| 529 | C_HCFS_SET(instance->registers->control, C_HCFS_OPERATIONAL);
|
|---|
| 530 | usb_log_debug("OHCI HC up and running (ctl_reg=0x%x).",
|
|---|
| 531 | OHCI_RD(instance->registers->control));
|
|---|
| 532 |
|
|---|
| 533 | return EOK;
|
|---|
| 534 | }
|
|---|
| 535 |
|
|---|
| 536 | /**
|
|---|
| 537 | * Setup roothub as a virtual hub.
|
|---|
| 538 | */
|
|---|
| 539 | int hc_setup_roothub(hc_device_t *hcd)
|
|---|
| 540 | {
|
|---|
| 541 | return hc_setup_virtual_root_hub(hcd, USB_SPEED_FULL);
|
|---|
| 542 | }
|
|---|
| 543 |
|
|---|
| 544 | /** Initialize schedule queues
|
|---|
| 545 | *
|
|---|
| 546 | * @param[in] instance OHCI hc driver structure
|
|---|
| 547 | * @return Error code
|
|---|
| 548 | */
|
|---|
| 549 | errno_t hc_init_transfer_lists(hc_t *instance)
|
|---|
| 550 | {
|
|---|
| 551 | assert(instance);
|
|---|
| 552 | #define SETUP_ENDPOINT_LIST(type) \
|
|---|
| 553 | do { \
|
|---|
| 554 | const char *name = usb_str_transfer_type(type); \
|
|---|
| 555 | const errno_t ret = endpoint_list_init(&instance->lists[type], name); \
|
|---|
| 556 | if (ret != EOK) { \
|
|---|
| 557 | usb_log_error("Failed to setup %s endpoint list: %s.", \
|
|---|
| 558 | name, str_error(ret)); \
|
|---|
| 559 | endpoint_list_fini(&instance->lists[USB_TRANSFER_ISOCHRONOUS]);\
|
|---|
| 560 | endpoint_list_fini(&instance->lists[USB_TRANSFER_INTERRUPT]); \
|
|---|
| 561 | endpoint_list_fini(&instance->lists[USB_TRANSFER_CONTROL]); \
|
|---|
| 562 | endpoint_list_fini(&instance->lists[USB_TRANSFER_BULK]); \
|
|---|
| 563 | return ret; \
|
|---|
| 564 | } \
|
|---|
| 565 | } while (0)
|
|---|
| 566 |
|
|---|
| 567 | SETUP_ENDPOINT_LIST(USB_TRANSFER_ISOCHRONOUS);
|
|---|
| 568 | SETUP_ENDPOINT_LIST(USB_TRANSFER_INTERRUPT);
|
|---|
| 569 | SETUP_ENDPOINT_LIST(USB_TRANSFER_CONTROL);
|
|---|
| 570 | SETUP_ENDPOINT_LIST(USB_TRANSFER_BULK);
|
|---|
| 571 | #undef SETUP_ENDPOINT_LIST
|
|---|
| 572 | endpoint_list_set_next(&instance->lists[USB_TRANSFER_INTERRUPT],
|
|---|
| 573 | &instance->lists[USB_TRANSFER_ISOCHRONOUS]);
|
|---|
| 574 |
|
|---|
| 575 | return EOK;
|
|---|
| 576 | }
|
|---|
| 577 |
|
|---|
| 578 | /** Initialize memory structures used by the OHCI hcd.
|
|---|
| 579 | *
|
|---|
| 580 | * @param[in] instance OHCI hc driver structure.
|
|---|
| 581 | * @return Error code.
|
|---|
| 582 | */
|
|---|
| 583 | errno_t hc_init_memory(hc_t *instance)
|
|---|
| 584 | {
|
|---|
| 585 | assert(instance);
|
|---|
| 586 |
|
|---|
| 587 | memset(&instance->rh, 0, sizeof(instance->rh));
|
|---|
| 588 | /* Init queues */
|
|---|
| 589 | errno_t ret = hc_init_transfer_lists(instance);
|
|---|
| 590 | if (ret != EOK) {
|
|---|
| 591 | return ret;
|
|---|
| 592 | }
|
|---|
| 593 |
|
|---|
| 594 | /*Init HCCA */
|
|---|
| 595 | instance->hcca = hcca_get();
|
|---|
| 596 | if (instance->hcca == NULL)
|
|---|
| 597 | return ENOMEM;
|
|---|
| 598 | usb_log_debug2("OHCI HCCA initialized at %p.", instance->hcca);
|
|---|
| 599 |
|
|---|
| 600 | for (unsigned i = 0; i < HCCA_INT_EP_COUNT; ++i) {
|
|---|
| 601 | hcca_set_int_ep(instance->hcca, i,
|
|---|
| 602 | instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa);
|
|---|
| 603 | }
|
|---|
| 604 | usb_log_debug2("Interrupt HEADs set to: %p (%#" PRIx32 ").",
|
|---|
| 605 | instance->lists[USB_TRANSFER_INTERRUPT].list_head,
|
|---|
| 606 | instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa);
|
|---|
| 607 |
|
|---|
| 608 | if ((ret = ohci_bus_init(&instance->bus, instance))) {
|
|---|
| 609 | usb_log_error("HC(%p): Failed to setup bus : %s",
|
|---|
| 610 | instance, str_error(ret));
|
|---|
| 611 | return ret;
|
|---|
| 612 | }
|
|---|
| 613 |
|
|---|
| 614 | hc_device_setup(&instance->base, (bus_t *) &instance->bus);
|
|---|
| 615 |
|
|---|
| 616 | return EOK;
|
|---|
| 617 | }
|
|---|
| 618 |
|
|---|
| 619 | /**
|
|---|
| 620 | * @}
|
|---|
| 621 | */
|
|---|