[6297465] | 1 | /*
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| 2 | * Copyright (c) 2011 Jan Vesely
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[e0a5d4c] | 3 | * Copyright (c) 2018 Ondrej Hlavaty
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[6297465] | 4 | * All rights reserved.
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| 5 | *
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| 6 | * Redistribution and use in source and binary forms, with or without
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| 7 | * modification, are permitted provided that the following conditions
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| 8 | * are met:
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| 9 | *
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| 10 | * - Redistributions of source code must retain the above copyright
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| 11 | * notice, this list of conditions and the following disclaimer.
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| 12 | * - Redistributions in binary form must reproduce the above copyright
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| 13 | * notice, this list of conditions and the following disclaimer in the
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| 14 | * documentation and/or other materials provided with the distribution.
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| 15 | * - The name of the author may not be used to endorse or promote products
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| 16 | * derived from this software without specific prior written permission.
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| 17 | *
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| 18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 28 | */
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| 29 |
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| 30 | /** @addtogroup drvusbehcihc
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| 31 | * @{
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| 32 | */
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| 33 | /** @file
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| 34 | * @brief EHCI Host controller driver routines
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| 35 | */
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| 36 |
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| 37 | #include <assert.h>
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| 38 | #include <async.h>
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| 39 | #include <errno.h>
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| 40 | #include <macros.h>
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| 41 | #include <mem.h>
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| 42 | #include <stdlib.h>
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[8d2dd7f2] | 43 | #include <stdint.h>
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[6297465] | 44 | #include <str_error.h>
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| 45 |
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| 46 | #include <usb/debug.h>
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| 47 | #include <usb/usb.h>
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[c6f82e5] | 48 | #include <usb/host/utility.h>
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[6297465] | 49 |
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[e9c5bd9] | 50 | #include "ehci_batch.h"
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[6297465] | 51 |
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| 52 | #include "hc.h"
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| 53 |
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| 54 | #define EHCI_USED_INTERRUPTS \
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[bfff7fd] | 55 | (USB_INTR_IRQ_FLAG | USB_INTR_ERR_IRQ_FLAG | USB_INTR_PORT_CHANGE_FLAG | \
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| 56 | USB_INTR_ASYNC_ADVANCE_FLAG | USB_INTR_HOST_ERR_FLAG)
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[6297465] | 57 |
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| 58 | static const irq_pio_range_t ehci_pio_ranges[] = {
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| 59 | {
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| 60 | .base = 0,
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| 61 | .size = sizeof(ehci_regs_t)
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| 62 | }
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| 63 | };
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| 64 |
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| 65 | static const irq_cmd_t ehci_irq_commands[] = {
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| 66 | {
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| 67 | .cmd = CMD_PIO_READ_32,
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| 68 | .dstarg = 1,
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| 69 | .addr = NULL
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| 70 | },
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| 71 | {
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| 72 | .cmd = CMD_AND,
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| 73 | .srcarg = 1,
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| 74 | .dstarg = 2,
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| 75 | .value = 0
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| 76 | },
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| 77 | {
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| 78 | .cmd = CMD_PREDICATE,
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| 79 | .srcarg = 2,
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| 80 | .value = 2
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| 81 | },
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| 82 | {
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| 83 | .cmd = CMD_PIO_WRITE_A_32,
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| 84 | .srcarg = 1,
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| 85 | .addr = NULL
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| 86 | },
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| 87 | {
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| 88 | .cmd = CMD_ACCEPT
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| 89 | }
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| 90 | };
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| 91 |
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[5a6cc679] | 92 | static errno_t hc_init_memory(hc_t *instance);
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[6297465] | 93 |
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| 94 | /** Generate IRQ code.
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| 95 | * @param[out] ranges PIO ranges buffer.
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[ba4a03a5] | 96 | * @param[in] hw_res Device's resources.
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[6297465] | 97 | *
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[68e5406] | 98 | * @param[out] irq
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| 99 | *
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[6297465] | 100 | * @return Error code.
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| 101 | */
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[5a6cc679] | 102 | errno_t hc_gen_irq_code(irq_code_t *code, hc_device_t *hcd, const hw_res_list_parsed_t *hw_res, int *irq)
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[6297465] | 103 | {
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| 104 | assert(code);
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[ba4a03a5] | 105 | assert(hw_res);
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[32fb6bce] | 106 | hc_t *instance = hcd_to_hc(hcd);
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[e4d7363] | 107 |
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[ba4a03a5] | 108 | if (hw_res->irqs.count != 1 || hw_res->mem_ranges.count != 1)
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| 109 | return EINVAL;
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| 110 |
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| 111 | addr_range_t regs = hw_res->mem_ranges.ranges[0];
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| 112 |
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| 113 | if (RNGSZ(regs) < sizeof(ehci_regs_t))
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[6297465] | 114 | return EOVERFLOW;
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| 115 |
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| 116 | code->ranges = malloc(sizeof(ehci_pio_ranges));
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| 117 | if (code->ranges == NULL)
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| 118 | return ENOMEM;
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| 119 |
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| 120 | code->cmds = malloc(sizeof(ehci_irq_commands));
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| 121 | if (code->cmds == NULL) {
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| 122 | free(code->ranges);
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| 123 | return ENOMEM;
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| 124 | }
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| 125 |
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| 126 | code->rangecount = ARRAY_SIZE(ehci_pio_ranges);
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| 127 | code->cmdcount = ARRAY_SIZE(ehci_irq_commands);
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| 128 |
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| 129 | memcpy(code->ranges, ehci_pio_ranges, sizeof(ehci_pio_ranges));
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[ba4a03a5] | 130 | code->ranges[0].base = RNGABS(regs);
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[6297465] | 131 |
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| 132 | memcpy(code->cmds, ehci_irq_commands, sizeof(ehci_irq_commands));
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[dca8fe5] | 133 |
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[d09d108] | 134 | ehci_regs_t *registers =
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| 135 | (ehci_regs_t *)(RNGABSPTR(regs) + EHCI_RD8(instance->caps->caplength));
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| 136 | code->cmds[0].addr = (void *) ®isters->usbsts;
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| 137 | code->cmds[3].addr = (void *) ®isters->usbsts;
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[6297465] | 138 | EHCI_WR(code->cmds[1].value, EHCI_USED_INTERRUPTS);
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| 139 |
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[a1732929] | 140 | usb_log_debug("Memory mapped regs at %p (size %zu), IRQ %d.",
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[ba4a03a5] | 141 | RNGABSPTR(regs), RNGSZ(regs), hw_res->irqs.irqs[0]);
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| 142 |
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[68e5406] | 143 | *irq = hw_res->irqs.irqs[0];
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| 144 | return EOK;
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[6297465] | 145 | }
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| 146 |
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| 147 | /** Initialize EHCI hc driver structure
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| 148 | *
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| 149 | * @param[in] instance Memory place for the structure.
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| 150 | * @param[in] regs Device's I/O registers range.
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| 151 | * @param[in] interrupts True if w interrupts should be used
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| 152 | * @return Error code
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| 153 | */
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[5a6cc679] | 154 | errno_t hc_add(hc_device_t *hcd, const hw_res_list_parsed_t *hw_res)
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[6297465] | 155 | {
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[32fb6bce] | 156 | hc_t *instance = hcd_to_hc(hcd);
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[7813516] | 157 | assert(hw_res);
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| 158 | if (hw_res->mem_ranges.count != 1 ||
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| 159 | hw_res->mem_ranges.ranges[0].size <
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| 160 | (sizeof(ehci_caps_regs_t) + sizeof(ehci_regs_t)))
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| 161 | return EINVAL;
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[6297465] | 162 |
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[5a6cc679] | 163 | errno_t ret = pio_enable_range(&hw_res->mem_ranges.ranges[0],
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[7813516] | 164 | (void **)&instance->caps);
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[6297465] | 165 | if (ret != EOK) {
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[05b51e37] | 166 | usb_log_error("HC(%p): Failed to gain access to device "
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[a1732929] | 167 | "registers: %s.", instance, str_error(ret));
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[6297465] | 168 | return ret;
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| 169 | }
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[e4d7363] | 170 |
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[05b51e37] | 171 | usb_log_info("HC(%p): Device registers at %"PRIx64" (%zuB) accessible.",
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| 172 | instance, hw_res->mem_ranges.ranges[0].address.absolute,
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[7813516] | 173 | hw_res->mem_ranges.ranges[0].size);
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[6297465] | 174 | instance->registers =
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| 175 | (void*)instance->caps + EHCI_RD8(instance->caps->caplength);
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[05b51e37] | 176 | usb_log_info("HC(%p): Device control registers at %" PRIx64, instance,
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[d97f91f] | 177 | hw_res->mem_ranges.ranges[0].address.absolute
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| 178 | + EHCI_RD8(instance->caps->caplength));
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[6297465] | 179 |
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[8ad2b0a] | 180 | list_initialize(&instance->pending_endpoints);
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[6297465] | 181 | fibril_mutex_initialize(&instance->guard);
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[763dbcb] | 182 | fibril_condvar_initialize(&instance->async_doorbell);
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[6297465] | 183 |
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| 184 | ret = hc_init_memory(instance);
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| 185 | if (ret != EOK) {
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[05b51e37] | 186 | usb_log_error("HC(%p): Failed to create EHCI memory structures:"
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| 187 | " %s.", instance, str_error(ret));
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[6297465] | 188 | return ret;
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| 189 | }
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| 190 |
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[05b51e37] | 191 | usb_log_info("HC(%p): Initializing RH(%p).", instance, &instance->rh);
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[6297465] | 192 | ehci_rh_init(
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[ddbd088] | 193 | &instance->rh, instance->caps, instance->registers, &instance->guard,
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| 194 | "ehci rh");
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[6297465] | 195 |
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[32fb6bce] | 196 | ehci_bus_init(&instance->bus, instance);
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| 197 | hc_device_setup(hcd, (bus_t *) &instance->bus);
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[6297465] | 198 | return EOK;
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| 199 | }
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| 200 |
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[7813516] | 201 | /** Safely dispose host controller internal structures
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| 202 | *
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| 203 | * @param[in] instance Host controller structure to use.
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| 204 | */
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[35c37fc] | 205 | int hc_gone(hc_device_t *hcd)
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[7813516] | 206 | {
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[35c37fc] | 207 | hc_t *hc = hcd_to_hc(hcd);
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| 208 | endpoint_list_fini(&hc->async_list);
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| 209 | endpoint_list_fini(&hc->int_list);
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| 210 | dma_buffer_free(&hc->dma_buffer);
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[32fb6bce] | 211 | return EOK;
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[84239b1] | 212 | }
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[7813516] | 213 |
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[6297465] | 214 | void hc_enqueue_endpoint(hc_t *instance, const endpoint_t *ep)
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| 215 | {
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[5f5321ee] | 216 | assert(instance);
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| 217 | assert(ep);
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| 218 | ehci_endpoint_t *ehci_ep = ehci_endpoint_get(ep);
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[a1732929] | 219 | usb_log_debug("HC(%p) enqueue EP(%d:%d:%s:%s)", instance,
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[a5b3de6] | 220 | ep->device->address, ep->endpoint,
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[92900e2] | 221 | usb_str_transfer_type_short(ep->transfer_type),
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| 222 | usb_str_direction(ep->direction));
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[5f5321ee] | 223 | switch (ep->transfer_type)
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| 224 | {
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| 225 | case USB_TRANSFER_CONTROL:
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| 226 | case USB_TRANSFER_BULK:
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| 227 | endpoint_list_append_ep(&instance->async_list, ehci_ep);
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| 228 | break;
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| 229 | case USB_TRANSFER_INTERRUPT:
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| 230 | endpoint_list_append_ep(&instance->int_list, ehci_ep);
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| 231 | break;
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| 232 | case USB_TRANSFER_ISOCHRONOUS:
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| 233 | /* NOT SUPPORTED */
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| 234 | break;
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| 235 | }
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[6297465] | 236 | }
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| 237 |
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| 238 | void hc_dequeue_endpoint(hc_t *instance, const endpoint_t *ep)
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| 239 | {
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[763dbcb] | 240 | assert(instance);
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| 241 | assert(ep);
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| 242 | ehci_endpoint_t *ehci_ep = ehci_endpoint_get(ep);
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[7278cbc9] | 243 | usb_log_debug("HC(%p) dequeue EP(%d:%d:%s:%s)", instance,
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| 244 | ep->device->address, ep->endpoint,
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[92900e2] | 245 | usb_str_transfer_type_short(ep->transfer_type),
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| 246 | usb_str_direction(ep->direction));
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[763dbcb] | 247 | switch (ep->transfer_type)
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| 248 | {
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| 249 | case USB_TRANSFER_INTERRUPT:
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[ce735cc2] | 250 | endpoint_list_remove_ep(&instance->int_list, ehci_ep);
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[763dbcb] | 251 | /* Fall through */
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| 252 | case USB_TRANSFER_ISOCHRONOUS:
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| 253 | /* NOT SUPPORTED */
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| 254 | return;
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| 255 | case USB_TRANSFER_CONTROL:
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| 256 | case USB_TRANSFER_BULK:
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| 257 | endpoint_list_remove_ep(&instance->async_list, ehci_ep);
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| 258 | break;
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| 259 | }
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| 260 | fibril_mutex_lock(&instance->guard);
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[05b51e37] | 261 | usb_log_debug("HC(%p): Waiting for doorbell", instance);
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[1803b7d] | 262 | EHCI_SET(instance->registers->usbcmd, USB_CMD_IRQ_ASYNC_DOORBELL);
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[763dbcb] | 263 | fibril_condvar_wait(&instance->async_doorbell, &instance->guard);
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[05b51e37] | 264 | usb_log_debug2("HC(%p): Got doorbell", instance);
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[763dbcb] | 265 | fibril_mutex_unlock(&instance->guard);
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[6297465] | 266 | }
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| 267 |
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[5a6cc679] | 268 | errno_t ehci_hc_status(bus_t *bus_base, uint32_t *status)
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[c9e954c] | 269 | {
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[32fb6bce] | 270 | assert(bus_base);
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[c9e954c] | 271 | assert(status);
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[32fb6bce] | 272 |
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| 273 | ehci_bus_t *bus = (ehci_bus_t *) bus_base;
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| 274 | hc_t *hc = bus->hc;
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| 275 | assert(hc);
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| 276 |
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[c9e954c] | 277 | *status = 0;
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[32fb6bce] | 278 | if (hc->registers) {
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| 279 | *status = EHCI_RD(hc->registers->usbsts);
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| 280 | EHCI_WR(hc->registers->usbsts, *status);
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[c9e954c] | 281 | }
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[32fb6bce] | 282 | usb_log_debug2("HC(%p): Read status: %x", hc, *status);
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[c9e954c] | 283 | return EOK;
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| 284 | }
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| 285 |
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[6297465] | 286 | /** Add USB transfer to the schedule.
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| 287 | *
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[c9e954c] | 288 | * @param[in] hcd HCD driver structure.
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[6297465] | 289 | * @param[in] batch Batch representing the transfer.
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| 290 | * @return Error code.
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| 291 | */
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[5a6cc679] | 292 | errno_t ehci_hc_schedule(usb_transfer_batch_t *batch)
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[6297465] | 293 | {
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[32fb6bce] | 294 | assert(batch);
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| 295 |
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| 296 | ehci_bus_t *bus = (ehci_bus_t *) endpoint_get_bus(batch->ep);
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| 297 | hc_t *hc = bus->hc;
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| 298 | assert(hc);
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[6297465] | 299 |
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| 300 | /* Check for root hub communication */
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[32fb6bce] | 301 | if (batch->target.address == ehci_rh_get_address(&hc->rh)) {
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[05b51e37] | 302 | usb_log_debug("HC(%p): Scheduling BATCH(%p) for RH(%p)",
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[32fb6bce] | 303 | hc, batch, &hc->rh);
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| 304 | return ehci_rh_schedule(&hc->rh, batch);
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[6297465] | 305 | }
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[5fd9c30] | 306 |
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[8ad2b0a] | 307 | endpoint_t * const ep = batch->ep;
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| 308 | ehci_endpoint_t * const ehci_ep = ehci_endpoint_get(ep);
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[4db49344] | 309 | ehci_transfer_batch_t *ehci_batch = ehci_transfer_batch_get(batch);
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[8ad2b0a] | 310 |
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[4db49344] | 311 | int err;
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[5fd9c30] | 312 |
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[4db49344] | 313 | if ((err = ehci_transfer_batch_prepare(ehci_batch)))
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| 314 | return err;
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[8ad2b0a] | 315 |
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[4db49344] | 316 | fibril_mutex_lock(&hc->guard);
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| 317 |
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| 318 | if ((err = endpoint_activate_locked(ep, batch))) {
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| 319 | fibril_mutex_unlock(&hc->guard);
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[5fd9c30] | 320 | return err;
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[8ad2b0a] | 321 | }
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[e9c5bd9] | 322 |
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[32fb6bce] | 323 | usb_log_debug("HC(%p): Committing BATCH(%p)", hc, batch);
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[e9c5bd9] | 324 | ehci_transfer_batch_commit(ehci_batch);
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[8ad2b0a] | 325 |
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| 326 | /* Enqueue endpoint to the checked list */
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| 327 | usb_log_debug2("HC(%p): Appending BATCH(%p)", hc, batch);
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| 328 | list_append(&ehci_ep->pending_link, &hc->pending_endpoints);
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| 329 |
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[4db49344] | 330 | fibril_mutex_unlock(&hc->guard);
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[e9c5bd9] | 331 | return EOK;
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[6297465] | 332 | }
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| 333 |
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| 334 | /** Interrupt handling routine
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| 335 | *
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[c9e954c] | 336 | * @param[in] hcd HCD driver structure.
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[6297465] | 337 | * @param[in] status Value of the status register at the time of interrupt.
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| 338 | */
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[32fb6bce] | 339 | void ehci_hc_interrupt(bus_t *bus_base, uint32_t status)
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[6297465] | 340 | {
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[32fb6bce] | 341 | assert(bus_base);
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| 342 |
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| 343 | ehci_bus_t *bus = (ehci_bus_t *) bus_base;
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| 344 | hc_t *hc = bus->hc;
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| 345 | assert(hc);
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[07645906] | 346 |
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[32fb6bce] | 347 | usb_log_debug2("HC(%p): Interrupt: %"PRIx32, hc, status);
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[6297465] | 348 | if (status & USB_STS_PORT_CHANGE_FLAG) {
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[32fb6bce] | 349 | ehci_rh_interrupt(&hc->rh);
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[6297465] | 350 | }
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[07645906] | 351 |
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[580b330] | 352 | if (status & USB_STS_IRQ_ASYNC_ADVANCE_FLAG) {
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[32fb6bce] | 353 | fibril_mutex_lock(&hc->guard);
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| 354 | usb_log_debug2("HC(%p): Signaling doorbell", hc);
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| 355 | fibril_condvar_broadcast(&hc->async_doorbell);
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| 356 | fibril_mutex_unlock(&hc->guard);
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[763dbcb] | 357 | }
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[07645906] | 358 |
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[e9c5bd9] | 359 | if (status & (USB_STS_IRQ_FLAG | USB_STS_ERR_IRQ_FLAG)) {
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[32fb6bce] | 360 | fibril_mutex_lock(&hc->guard);
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[e9c5bd9] | 361 |
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[8ad2b0a] | 362 | usb_log_debug2("HC(%p): Scanning %lu pending endpoints", hc,
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| 363 | list_count(&hc->pending_endpoints));
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| 364 | list_foreach_safe(hc->pending_endpoints, current, next) {
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| 365 | ehci_endpoint_t *ep
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| 366 | = list_get_instance(current, ehci_endpoint_t, pending_link);
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| 367 |
|
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| 368 | ehci_transfer_batch_t *batch
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| 369 | = ehci_transfer_batch_get(ep->base.active_batch);
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| 370 | assert(batch);
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[e9c5bd9] | 371 |
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[5fd9c30] | 372 | if (ehci_transfer_batch_check_completed(batch)) {
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[8ad2b0a] | 373 | endpoint_deactivate_locked(&ep->base);
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[e9c5bd9] | 374 | list_remove(current);
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[c6f82e5] | 375 | hc_reset_toggles(&batch->base, &ehci_ep_toggle_reset);
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[5fd9c30] | 376 | usb_transfer_batch_finish(&batch->base);
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[e9c5bd9] | 377 | }
|
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| 378 | }
|
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[32fb6bce] | 379 | fibril_mutex_unlock(&hc->guard);
|
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[8ad2b0a] | 380 |
|
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| 381 |
|
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[e9c5bd9] | 382 | }
|
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| 383 |
|
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[07645906] | 384 | if (status & USB_STS_HOST_ERROR_FLAG) {
|
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[32fb6bce] | 385 | usb_log_fatal("HCD(%p): HOST SYSTEM ERROR!", hc);
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[07645906] | 386 | //TODO do something here
|
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| 387 | }
|
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[6297465] | 388 | }
|
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| 389 |
|
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| 390 | /** EHCI hw initialization routine.
|
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| 391 | *
|
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| 392 | * @param[in] instance EHCI hc driver structure.
|
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| 393 | */
|
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[32fb6bce] | 394 | int hc_start(hc_device_t *hcd)
|
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[6297465] | 395 | {
|
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[32fb6bce] | 396 | hc_t *instance = hcd_to_hc(hcd);
|
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[e4d7363] | 397 | usb_log_debug("HC(%p): Starting HW.", instance);
|
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| 398 |
|
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[3eb0c85] | 399 | /* Turn off the HC if it's running, Reseting a running device is
|
---|
[478e243] | 400 | * undefined */
|
---|
| 401 | if (!(EHCI_RD(instance->registers->usbsts) & USB_STS_HC_HALTED_FLAG)) {
|
---|
| 402 | /* disable all interrupts */
|
---|
| 403 | EHCI_WR(instance->registers->usbintr, 0);
|
---|
| 404 | /* ack all interrupts */
|
---|
| 405 | EHCI_WR(instance->registers->usbsts, 0x3f);
|
---|
| 406 | /* Stop HC hw */
|
---|
| 407 | EHCI_WR(instance->registers->usbcmd, 0);
|
---|
| 408 | /* Wait until hc is halted */
|
---|
| 409 | while ((EHCI_RD(instance->registers->usbsts) & USB_STS_HC_HALTED_FLAG) == 0) {
|
---|
| 410 | async_usleep(1);
|
---|
| 411 | }
|
---|
[05b51e37] | 412 | usb_log_info("HC(%p): EHCI turned off.", instance);
|
---|
[478e243] | 413 | } else {
|
---|
[05b51e37] | 414 | usb_log_info("HC(%p): EHCI was not running.", instance);
|
---|
[478e243] | 415 | }
|
---|
| 416 |
|
---|
| 417 | /* Hw initialization sequence, see page 53 (pdf 63) */
|
---|
| 418 | EHCI_SET(instance->registers->usbcmd, USB_CMD_HC_RESET_FLAG);
|
---|
[05b51e37] | 419 | usb_log_info("HC(%p): Waiting for HW reset.", instance);
|
---|
[478e243] | 420 | while (EHCI_RD(instance->registers->usbcmd) & USB_CMD_HC_RESET_FLAG) {
|
---|
| 421 | async_usleep(1);
|
---|
| 422 | }
|
---|
[05b51e37] | 423 | usb_log_debug("HC(%p): HW reset OK.", instance);
|
---|
| 424 |
|
---|
[763dbcb] | 425 | /* Use the lowest 4G segment */
|
---|
[478e243] | 426 | EHCI_WR(instance->registers->ctrldssegment, 0);
|
---|
[3eb0c85] | 427 |
|
---|
| 428 | /* Enable periodic list */
|
---|
[35c37fc] | 429 | assert(instance->periodic_list);
|
---|
[50362c6] | 430 | uintptr_t phys_base =
|
---|
[35c37fc] | 431 | addr_to_phys((void*)instance->periodic_list);
|
---|
[478e243] | 432 | assert((phys_base & USB_PERIODIC_LIST_BASE_MASK) == phys_base);
|
---|
| 433 | EHCI_WR(instance->registers->periodiclistbase, phys_base);
|
---|
[44b9b44] | 434 | EHCI_SET(instance->registers->usbcmd, USB_CMD_PERIODIC_SCHEDULE_FLAG);
|
---|
[05b51e37] | 435 | usb_log_debug("HC(%p): Enabled periodic list.", instance);
|
---|
[478e243] | 436 |
|
---|
[763dbcb] | 437 |
|
---|
[0a751aa] | 438 | /* Enable Async schedule */
|
---|
[50362c6] | 439 | phys_base = addr_to_phys((void*)instance->async_list.list_head);
|
---|
| 440 | assert((phys_base & USB_ASYNCLIST_MASK) == phys_base);
|
---|
| 441 | EHCI_WR(instance->registers->asynclistaddr, phys_base);
|
---|
[0a751aa] | 442 | EHCI_SET(instance->registers->usbcmd, USB_CMD_ASYNC_SCHEDULE_FLAG);
|
---|
[05b51e37] | 443 | usb_log_debug("HC(%p): Enabled async list.", instance);
|
---|
[44b9b44] | 444 |
|
---|
[3eb0c85] | 445 | /* Start hc and get all ports */
|
---|
[44b9b44] | 446 | EHCI_SET(instance->registers->usbcmd, USB_CMD_RUN_FLAG);
|
---|
| 447 | EHCI_SET(instance->registers->configflag, USB_CONFIG_FLAG_FLAG);
|
---|
[05b51e37] | 448 | usb_log_debug("HC(%p): HW started.", instance);
|
---|
| 449 |
|
---|
[a1732929] | 450 | usb_log_debug2("HC(%p): Registers: "
|
---|
| 451 | "\tUSBCMD(%p): %x(0x00080000 = at least 1ms between interrupts)"
|
---|
| 452 | "\tUSBSTS(%p): %x(0x00001000 = HC halted)"
|
---|
| 453 | "\tUSBINT(%p): %x(0x0 = no interrupts)."
|
---|
| 454 | "\tCONFIG(%p): %x(0x0 = ports controlled by companion hc).",
|
---|
[05b51e37] | 455 | instance,
|
---|
[615abda] | 456 | &instance->registers->usbcmd, EHCI_RD(instance->registers->usbcmd),
|
---|
| 457 | &instance->registers->usbsts, EHCI_RD(instance->registers->usbsts),
|
---|
| 458 | &instance->registers->usbintr, EHCI_RD(instance->registers->usbintr),
|
---|
| 459 | &instance->registers->configflag, EHCI_RD(instance->registers->configflag));
|
---|
[495547d] | 460 | /* Clear and Enable interrupts */
|
---|
| 461 | EHCI_WR(instance->registers->usbsts, EHCI_RD(instance->registers->usbsts));
|
---|
| 462 | EHCI_WR(instance->registers->usbintr, EHCI_USED_INTERRUPTS);
|
---|
[e4d7363] | 463 |
|
---|
| 464 | return EOK;
|
---|
[6297465] | 465 | }
|
---|
| 466 |
|
---|
[129b821f] | 467 | /**
|
---|
| 468 | * Setup roothub as a virtual hub.
|
---|
| 469 | */
|
---|
| 470 | int hc_setup_roothub(hc_device_t *hcd)
|
---|
| 471 | {
|
---|
| 472 | return hc_setup_virtual_root_hub(hcd, USB_SPEED_HIGH);
|
---|
| 473 | }
|
---|
| 474 |
|
---|
[6297465] | 475 | /** Initialize memory structures used by the EHCI hcd.
|
---|
| 476 | *
|
---|
| 477 | * @param[in] instance EHCI hc driver structure.
|
---|
| 478 | * @return Error code.
|
---|
| 479 | */
|
---|
[5a6cc679] | 480 | errno_t hc_init_memory(hc_t *instance)
|
---|
[6297465] | 481 | {
|
---|
[478e243] | 482 | assert(instance);
|
---|
[05b51e37] | 483 | usb_log_debug2("HC(%p): Initializing Async list(%p).", instance,
|
---|
| 484 | &instance->async_list);
|
---|
[5a6cc679] | 485 | errno_t ret = endpoint_list_init(&instance->async_list, "ASYNC");
|
---|
[5f5321ee] | 486 | if (ret != EOK) {
|
---|
[05b51e37] | 487 | usb_log_error("HC(%p): Failed to setup ASYNC list: %s",
|
---|
| 488 | instance, str_error(ret));
|
---|
[5f5321ee] | 489 | return ret;
|
---|
| 490 | }
|
---|
[50362c6] | 491 | /* Specs say "Software must set queue head horizontal pointer T-bits to
|
---|
| 492 | * a zero for queue heads in the asynchronous schedule" (4.4.0).
|
---|
| 493 | * So we must maintain circular buffer (all horizontal pointers
|
---|
| 494 | * have to be valid */
|
---|
| 495 | endpoint_list_chain(&instance->async_list, &instance->async_list);
|
---|
[5f5321ee] | 496 |
|
---|
[05b51e37] | 497 | usb_log_debug2("HC(%p): Initializing Interrupt list (%p).", instance,
|
---|
| 498 | &instance->int_list);
|
---|
[5f5321ee] | 499 | ret = endpoint_list_init(&instance->int_list, "INT");
|
---|
| 500 | if (ret != EOK) {
|
---|
[05b51e37] | 501 | usb_log_error("HC(%p): Failed to setup INT list: %s",
|
---|
| 502 | instance, str_error(ret));
|
---|
[5f5321ee] | 503 | endpoint_list_fini(&instance->async_list);
|
---|
| 504 | return ret;
|
---|
| 505 | }
|
---|
[478e243] | 506 |
|
---|
| 507 | /* Take 1024 periodic list heads, we ignore low mem options */
|
---|
[35c37fc] | 508 | if (dma_buffer_alloc(&instance->dma_buffer, PAGE_SIZE)) {
|
---|
[05b51e37] | 509 | usb_log_error("HC(%p): Failed to get ISO schedule page.",
|
---|
| 510 | instance);
|
---|
[5f5321ee] | 511 | endpoint_list_fini(&instance->async_list);
|
---|
| 512 | endpoint_list_fini(&instance->int_list);
|
---|
[478e243] | 513 | return ENOMEM;
|
---|
[5f5321ee] | 514 | }
|
---|
[35c37fc] | 515 | instance->periodic_list = instance->dma_buffer.virt;
|
---|
[05b51e37] | 516 |
|
---|
| 517 | usb_log_debug2("HC(%p): Initializing Periodic list.", instance);
|
---|
[35c37fc] | 518 | for (unsigned i = 0; i < PAGE_SIZE/sizeof(link_pointer_t); ++i)
|
---|
[478e243] | 519 | {
|
---|
| 520 | /* Disable everything for now */
|
---|
[35c37fc] | 521 | instance->periodic_list[i] =
|
---|
[50362c6] | 522 | LINK_POINTER_QH(addr_to_phys(instance->int_list.list_head));
|
---|
[478e243] | 523 | }
|
---|
[6297465] | 524 | return EOK;
|
---|
| 525 | }
|
---|
| 526 |
|
---|
| 527 | /**
|
---|
| 528 | * @}
|
---|
| 529 | */
|
---|