source: mainline/uspace/drv/bus/usb/ehci/hc.c@ 84239b1

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 84239b1 was 84239b1, checked in by Jiri Svoboda <jiri@…>, 7 years ago

And there was much fixing.
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File size: 15.4 KB
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1/*
2 * Copyright (c) 2011 Jan Vesely
3 * Copyright (c) 2018 Ondrej Hlavaty
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/** @addtogroup drvusbehcihc
31 * @{
32 */
33/** @file
34 * @brief EHCI Host controller driver routines
35 */
36
37#include <assert.h>
38#include <async.h>
39#include <errno.h>
40#include <macros.h>
41#include <mem.h>
42#include <stdlib.h>
43#include <stdint.h>
44#include <str_error.h>
45
46#include <usb/debug.h>
47#include <usb/usb.h>
48#include <usb/host/utility.h>
49
50#include "ehci_batch.h"
51
52#include "hc.h"
53
54#define EHCI_USED_INTERRUPTS \
55 (USB_INTR_IRQ_FLAG | USB_INTR_ERR_IRQ_FLAG | USB_INTR_PORT_CHANGE_FLAG | \
56 USB_INTR_ASYNC_ADVANCE_FLAG | USB_INTR_HOST_ERR_FLAG)
57
58static const irq_pio_range_t ehci_pio_ranges[] = {
59 {
60 .base = 0,
61 .size = sizeof(ehci_regs_t)
62 }
63};
64
65static const irq_cmd_t ehci_irq_commands[] = {
66 {
67 .cmd = CMD_PIO_READ_32,
68 .dstarg = 1,
69 .addr = NULL
70 },
71 {
72 .cmd = CMD_AND,
73 .srcarg = 1,
74 .dstarg = 2,
75 .value = 0
76 },
77 {
78 .cmd = CMD_PREDICATE,
79 .srcarg = 2,
80 .value = 2
81 },
82 {
83 .cmd = CMD_PIO_WRITE_A_32,
84 .srcarg = 1,
85 .addr = NULL
86 },
87 {
88 .cmd = CMD_ACCEPT
89 }
90};
91
92static errno_t hc_init_memory(hc_t *instance);
93
94/** Generate IRQ code.
95 * @param[out] ranges PIO ranges buffer.
96 * @param[in] hw_res Device's resources.
97 *
98 * @param[out] irq
99 *
100 * @return Error code.
101 */
102errno_t hc_gen_irq_code(irq_code_t *code, hc_device_t *hcd, const hw_res_list_parsed_t *hw_res, int *irq)
103{
104 assert(code);
105 assert(hw_res);
106 hc_t *instance = hcd_to_hc(hcd);
107
108 if (hw_res->irqs.count != 1 || hw_res->mem_ranges.count != 1)
109 return EINVAL;
110
111 addr_range_t regs = hw_res->mem_ranges.ranges[0];
112
113 if (RNGSZ(regs) < sizeof(ehci_regs_t))
114 return EOVERFLOW;
115
116 code->ranges = malloc(sizeof(ehci_pio_ranges));
117 if (code->ranges == NULL)
118 return ENOMEM;
119
120 code->cmds = malloc(sizeof(ehci_irq_commands));
121 if (code->cmds == NULL) {
122 free(code->ranges);
123 return ENOMEM;
124 }
125
126 code->rangecount = ARRAY_SIZE(ehci_pio_ranges);
127 code->cmdcount = ARRAY_SIZE(ehci_irq_commands);
128
129 memcpy(code->ranges, ehci_pio_ranges, sizeof(ehci_pio_ranges));
130 code->ranges[0].base = RNGABS(regs);
131
132 memcpy(code->cmds, ehci_irq_commands, sizeof(ehci_irq_commands));
133
134 ehci_regs_t *registers =
135 (ehci_regs_t *)(RNGABSPTR(regs) + EHCI_RD8(instance->caps->caplength));
136 code->cmds[0].addr = (void *) &registers->usbsts;
137 code->cmds[3].addr = (void *) &registers->usbsts;
138 EHCI_WR(code->cmds[1].value, EHCI_USED_INTERRUPTS);
139
140 usb_log_debug("Memory mapped regs at %p (size %zu), IRQ %d.",
141 RNGABSPTR(regs), RNGSZ(regs), hw_res->irqs.irqs[0]);
142
143 *irq = hw_res->irqs.irqs[0];
144 return EOK;
145}
146
147/** Initialize EHCI hc driver structure
148 *
149 * @param[in] instance Memory place for the structure.
150 * @param[in] regs Device's I/O registers range.
151 * @param[in] interrupts True if w interrupts should be used
152 * @return Error code
153 */
154errno_t hc_add(hc_device_t *hcd, const hw_res_list_parsed_t *hw_res)
155{
156 hc_t *instance = hcd_to_hc(hcd);
157 assert(hw_res);
158 if (hw_res->mem_ranges.count != 1 ||
159 hw_res->mem_ranges.ranges[0].size <
160 (sizeof(ehci_caps_regs_t) + sizeof(ehci_regs_t)))
161 return EINVAL;
162
163 errno_t ret = pio_enable_range(&hw_res->mem_ranges.ranges[0],
164 (void **)&instance->caps);
165 if (ret != EOK) {
166 usb_log_error("HC(%p): Failed to gain access to device "
167 "registers: %s.", instance, str_error(ret));
168 return ret;
169 }
170
171 usb_log_info("HC(%p): Device registers at %"PRIx64" (%zuB) accessible.",
172 instance, hw_res->mem_ranges.ranges[0].address.absolute,
173 hw_res->mem_ranges.ranges[0].size);
174 instance->registers =
175 (void*)instance->caps + EHCI_RD8(instance->caps->caplength);
176 usb_log_info("HC(%p): Device control registers at %" PRIx64, instance,
177 hw_res->mem_ranges.ranges[0].address.absolute
178 + EHCI_RD8(instance->caps->caplength));
179
180 list_initialize(&instance->pending_endpoints);
181 fibril_mutex_initialize(&instance->guard);
182 fibril_condvar_initialize(&instance->async_doorbell);
183
184 ret = hc_init_memory(instance);
185 if (ret != EOK) {
186 usb_log_error("HC(%p): Failed to create EHCI memory structures:"
187 " %s.", instance, str_error(ret));
188 return ret;
189 }
190
191 usb_log_info("HC(%p): Initializing RH(%p).", instance, &instance->rh);
192 ehci_rh_init(
193 &instance->rh, instance->caps, instance->registers, &instance->guard,
194 "ehci rh");
195
196 ehci_bus_init(&instance->bus, instance);
197 hc_device_setup(hcd, (bus_t *) &instance->bus);
198 return EOK;
199}
200
201/** Safely dispose host controller internal structures
202 *
203 * @param[in] instance Host controller structure to use.
204 */
205int hc_gone(hc_device_t *hcd)
206{
207 hc_t *hc = hcd_to_hc(hcd);
208 endpoint_list_fini(&hc->async_list);
209 endpoint_list_fini(&hc->int_list);
210 dma_buffer_free(&hc->dma_buffer);
211 return EOK;
212}
213
214void hc_enqueue_endpoint(hc_t *instance, const endpoint_t *ep)
215{
216 assert(instance);
217 assert(ep);
218 ehci_endpoint_t *ehci_ep = ehci_endpoint_get(ep);
219 usb_log_debug("HC(%p) enqueue EP(%d:%d:%s:%s)", instance,
220 ep->device->address, ep->endpoint,
221 usb_str_transfer_type_short(ep->transfer_type),
222 usb_str_direction(ep->direction));
223 switch (ep->transfer_type)
224 {
225 case USB_TRANSFER_CONTROL:
226 case USB_TRANSFER_BULK:
227 endpoint_list_append_ep(&instance->async_list, ehci_ep);
228 break;
229 case USB_TRANSFER_INTERRUPT:
230 endpoint_list_append_ep(&instance->int_list, ehci_ep);
231 break;
232 case USB_TRANSFER_ISOCHRONOUS:
233 /* NOT SUPPORTED */
234 break;
235 }
236}
237
238void hc_dequeue_endpoint(hc_t *instance, const endpoint_t *ep)
239{
240 assert(instance);
241 assert(ep);
242 ehci_endpoint_t *ehci_ep = ehci_endpoint_get(ep);
243 usb_log_debug("HC(%p) dequeue EP(%d:%d:%s:%s)", instance,
244 ep->device->address, ep->endpoint,
245 usb_str_transfer_type_short(ep->transfer_type),
246 usb_str_direction(ep->direction));
247 switch (ep->transfer_type)
248 {
249 case USB_TRANSFER_INTERRUPT:
250 endpoint_list_remove_ep(&instance->int_list, ehci_ep);
251 /* Fall through */
252 case USB_TRANSFER_ISOCHRONOUS:
253 /* NOT SUPPORTED */
254 return;
255 case USB_TRANSFER_CONTROL:
256 case USB_TRANSFER_BULK:
257 endpoint_list_remove_ep(&instance->async_list, ehci_ep);
258 break;
259 }
260 fibril_mutex_lock(&instance->guard);
261 usb_log_debug("HC(%p): Waiting for doorbell", instance);
262 EHCI_SET(instance->registers->usbcmd, USB_CMD_IRQ_ASYNC_DOORBELL);
263 fibril_condvar_wait(&instance->async_doorbell, &instance->guard);
264 usb_log_debug2("HC(%p): Got doorbell", instance);
265 fibril_mutex_unlock(&instance->guard);
266}
267
268errno_t ehci_hc_status(bus_t *bus_base, uint32_t *status)
269{
270 assert(bus_base);
271 assert(status);
272
273 ehci_bus_t *bus = (ehci_bus_t *) bus_base;
274 hc_t *hc = bus->hc;
275 assert(hc);
276
277 *status = 0;
278 if (hc->registers) {
279 *status = EHCI_RD(hc->registers->usbsts);
280 EHCI_WR(hc->registers->usbsts, *status);
281 }
282 usb_log_debug2("HC(%p): Read status: %x", hc, *status);
283 return EOK;
284}
285
286/** Add USB transfer to the schedule.
287 *
288 * @param[in] hcd HCD driver structure.
289 * @param[in] batch Batch representing the transfer.
290 * @return Error code.
291 */
292errno_t ehci_hc_schedule(usb_transfer_batch_t *batch)
293{
294 assert(batch);
295
296 ehci_bus_t *bus = (ehci_bus_t *) endpoint_get_bus(batch->ep);
297 hc_t *hc = bus->hc;
298 assert(hc);
299
300 /* Check for root hub communication */
301 if (batch->target.address == ehci_rh_get_address(&hc->rh)) {
302 usb_log_debug("HC(%p): Scheduling BATCH(%p) for RH(%p)",
303 hc, batch, &hc->rh);
304 return ehci_rh_schedule(&hc->rh, batch);
305 }
306
307 endpoint_t * const ep = batch->ep;
308 ehci_endpoint_t * const ehci_ep = ehci_endpoint_get(ep);
309 ehci_transfer_batch_t *ehci_batch = ehci_transfer_batch_get(batch);
310
311 int err;
312
313 if ((err = ehci_transfer_batch_prepare(ehci_batch)))
314 return err;
315
316 fibril_mutex_lock(&hc->guard);
317
318 if ((err = endpoint_activate_locked(ep, batch))) {
319 fibril_mutex_unlock(&hc->guard);
320 return err;
321 }
322
323 usb_log_debug("HC(%p): Committing BATCH(%p)", hc, batch);
324 ehci_transfer_batch_commit(ehci_batch);
325
326 /* Enqueue endpoint to the checked list */
327 usb_log_debug2("HC(%p): Appending BATCH(%p)", hc, batch);
328 list_append(&ehci_ep->pending_link, &hc->pending_endpoints);
329
330 fibril_mutex_unlock(&hc->guard);
331 return EOK;
332}
333
334/** Interrupt handling routine
335 *
336 * @param[in] hcd HCD driver structure.
337 * @param[in] status Value of the status register at the time of interrupt.
338 */
339void ehci_hc_interrupt(bus_t *bus_base, uint32_t status)
340{
341 assert(bus_base);
342
343 ehci_bus_t *bus = (ehci_bus_t *) bus_base;
344 hc_t *hc = bus->hc;
345 assert(hc);
346
347 usb_log_debug2("HC(%p): Interrupt: %"PRIx32, hc, status);
348 if (status & USB_STS_PORT_CHANGE_FLAG) {
349 ehci_rh_interrupt(&hc->rh);
350 }
351
352 if (status & USB_STS_IRQ_ASYNC_ADVANCE_FLAG) {
353 fibril_mutex_lock(&hc->guard);
354 usb_log_debug2("HC(%p): Signaling doorbell", hc);
355 fibril_condvar_broadcast(&hc->async_doorbell);
356 fibril_mutex_unlock(&hc->guard);
357 }
358
359 if (status & (USB_STS_IRQ_FLAG | USB_STS_ERR_IRQ_FLAG)) {
360 fibril_mutex_lock(&hc->guard);
361
362 usb_log_debug2("HC(%p): Scanning %lu pending endpoints", hc,
363 list_count(&hc->pending_endpoints));
364 list_foreach_safe(hc->pending_endpoints, current, next) {
365 ehci_endpoint_t *ep
366 = list_get_instance(current, ehci_endpoint_t, pending_link);
367
368 ehci_transfer_batch_t *batch
369 = ehci_transfer_batch_get(ep->base.active_batch);
370 assert(batch);
371
372 if (ehci_transfer_batch_check_completed(batch)) {
373 endpoint_deactivate_locked(&ep->base);
374 list_remove(current);
375 hc_reset_toggles(&batch->base, &ehci_ep_toggle_reset);
376 usb_transfer_batch_finish(&batch->base);
377 }
378 }
379 fibril_mutex_unlock(&hc->guard);
380
381
382 }
383
384 if (status & USB_STS_HOST_ERROR_FLAG) {
385 usb_log_fatal("HCD(%p): HOST SYSTEM ERROR!", hc);
386 //TODO do something here
387 }
388}
389
390/** EHCI hw initialization routine.
391 *
392 * @param[in] instance EHCI hc driver structure.
393 */
394int hc_start(hc_device_t *hcd)
395{
396 hc_t *instance = hcd_to_hc(hcd);
397 usb_log_debug("HC(%p): Starting HW.", instance);
398
399 /* Turn off the HC if it's running, Reseting a running device is
400 * undefined */
401 if (!(EHCI_RD(instance->registers->usbsts) & USB_STS_HC_HALTED_FLAG)) {
402 /* disable all interrupts */
403 EHCI_WR(instance->registers->usbintr, 0);
404 /* ack all interrupts */
405 EHCI_WR(instance->registers->usbsts, 0x3f);
406 /* Stop HC hw */
407 EHCI_WR(instance->registers->usbcmd, 0);
408 /* Wait until hc is halted */
409 while ((EHCI_RD(instance->registers->usbsts) & USB_STS_HC_HALTED_FLAG) == 0) {
410 async_usleep(1);
411 }
412 usb_log_info("HC(%p): EHCI turned off.", instance);
413 } else {
414 usb_log_info("HC(%p): EHCI was not running.", instance);
415 }
416
417 /* Hw initialization sequence, see page 53 (pdf 63) */
418 EHCI_SET(instance->registers->usbcmd, USB_CMD_HC_RESET_FLAG);
419 usb_log_info("HC(%p): Waiting for HW reset.", instance);
420 while (EHCI_RD(instance->registers->usbcmd) & USB_CMD_HC_RESET_FLAG) {
421 async_usleep(1);
422 }
423 usb_log_debug("HC(%p): HW reset OK.", instance);
424
425 /* Use the lowest 4G segment */
426 EHCI_WR(instance->registers->ctrldssegment, 0);
427
428 /* Enable periodic list */
429 assert(instance->periodic_list);
430 uintptr_t phys_base =
431 addr_to_phys((void*)instance->periodic_list);
432 assert((phys_base & USB_PERIODIC_LIST_BASE_MASK) == phys_base);
433 EHCI_WR(instance->registers->periodiclistbase, phys_base);
434 EHCI_SET(instance->registers->usbcmd, USB_CMD_PERIODIC_SCHEDULE_FLAG);
435 usb_log_debug("HC(%p): Enabled periodic list.", instance);
436
437
438 /* Enable Async schedule */
439 phys_base = addr_to_phys((void*)instance->async_list.list_head);
440 assert((phys_base & USB_ASYNCLIST_MASK) == phys_base);
441 EHCI_WR(instance->registers->asynclistaddr, phys_base);
442 EHCI_SET(instance->registers->usbcmd, USB_CMD_ASYNC_SCHEDULE_FLAG);
443 usb_log_debug("HC(%p): Enabled async list.", instance);
444
445 /* Start hc and get all ports */
446 EHCI_SET(instance->registers->usbcmd, USB_CMD_RUN_FLAG);
447 EHCI_SET(instance->registers->configflag, USB_CONFIG_FLAG_FLAG);
448 usb_log_debug("HC(%p): HW started.", instance);
449
450 usb_log_debug2("HC(%p): Registers: "
451 "\tUSBCMD(%p): %x(0x00080000 = at least 1ms between interrupts)"
452 "\tUSBSTS(%p): %x(0x00001000 = HC halted)"
453 "\tUSBINT(%p): %x(0x0 = no interrupts)."
454 "\tCONFIG(%p): %x(0x0 = ports controlled by companion hc).",
455 instance,
456 &instance->registers->usbcmd, EHCI_RD(instance->registers->usbcmd),
457 &instance->registers->usbsts, EHCI_RD(instance->registers->usbsts),
458 &instance->registers->usbintr, EHCI_RD(instance->registers->usbintr),
459 &instance->registers->configflag, EHCI_RD(instance->registers->configflag));
460 /* Clear and Enable interrupts */
461 EHCI_WR(instance->registers->usbsts, EHCI_RD(instance->registers->usbsts));
462 EHCI_WR(instance->registers->usbintr, EHCI_USED_INTERRUPTS);
463
464 return EOK;
465}
466
467/**
468 * Setup roothub as a virtual hub.
469 */
470int hc_setup_roothub(hc_device_t *hcd)
471{
472 return hc_setup_virtual_root_hub(hcd, USB_SPEED_HIGH);
473}
474
475/** Initialize memory structures used by the EHCI hcd.
476 *
477 * @param[in] instance EHCI hc driver structure.
478 * @return Error code.
479 */
480errno_t hc_init_memory(hc_t *instance)
481{
482 assert(instance);
483 usb_log_debug2("HC(%p): Initializing Async list(%p).", instance,
484 &instance->async_list);
485 errno_t ret = endpoint_list_init(&instance->async_list, "ASYNC");
486 if (ret != EOK) {
487 usb_log_error("HC(%p): Failed to setup ASYNC list: %s",
488 instance, str_error(ret));
489 return ret;
490 }
491 /* Specs say "Software must set queue head horizontal pointer T-bits to
492 * a zero for queue heads in the asynchronous schedule" (4.4.0).
493 * So we must maintain circular buffer (all horizontal pointers
494 * have to be valid */
495 endpoint_list_chain(&instance->async_list, &instance->async_list);
496
497 usb_log_debug2("HC(%p): Initializing Interrupt list (%p).", instance,
498 &instance->int_list);
499 ret = endpoint_list_init(&instance->int_list, "INT");
500 if (ret != EOK) {
501 usb_log_error("HC(%p): Failed to setup INT list: %s",
502 instance, str_error(ret));
503 endpoint_list_fini(&instance->async_list);
504 return ret;
505 }
506
507 /* Take 1024 periodic list heads, we ignore low mem options */
508 if (dma_buffer_alloc(&instance->dma_buffer, PAGE_SIZE)) {
509 usb_log_error("HC(%p): Failed to get ISO schedule page.",
510 instance);
511 endpoint_list_fini(&instance->async_list);
512 endpoint_list_fini(&instance->int_list);
513 return ENOMEM;
514 }
515 instance->periodic_list = instance->dma_buffer.virt;
516
517 usb_log_debug2("HC(%p): Initializing Periodic list.", instance);
518 for (unsigned i = 0; i < PAGE_SIZE/sizeof(link_pointer_t); ++i)
519 {
520 /* Disable everything for now */
521 instance->periodic_list[i] =
522 LINK_POINTER_QH(addr_to_phys(instance->int_list.list_head));
523 }
524 return EOK;
525}
526
527/**
528 * @}
529 */
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