source: mainline/uspace/drv/bus/usb/ehci/hc.c

Last change on this file was 9dfb034, checked in by Jiri Svoboda <jiri@…>, 4 months ago

Implement quiesce for EHCI and OHCI.
  • Property mode set to 100644
File size: 16.5 KB
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1/*
2 * Copyright (c) 2025 Jiri Svoboda
3 * Copyright (c) 2011 Jan Vesely
4 * Copyright (c) 2018 Ondrej Hlavaty
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * - Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * - Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * - The name of the author may not be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31/** @addtogroup drvusbehci
32 * @{
33 */
34/** @file
35 * @brief EHCI Host controller driver routines
36 */
37
38#include <assert.h>
39#include <async.h>
40#include <errno.h>
41#include <macros.h>
42#include <mem.h>
43#include <stdlib.h>
44#include <stdint.h>
45#include <str_error.h>
46
47#include <usb/debug.h>
48#include <usb/usb.h>
49#include <usb/host/utility.h>
50
51#include "ehci_batch.h"
52
53#include "hc.h"
54
55#define EHCI_USED_INTERRUPTS \
56 (USB_INTR_IRQ_FLAG | USB_INTR_ERR_IRQ_FLAG | USB_INTR_PORT_CHANGE_FLAG | \
57 USB_INTR_ASYNC_ADVANCE_FLAG | USB_INTR_HOST_ERR_FLAG)
58
59static const irq_pio_range_t ehci_pio_ranges[] = {
60 {
61 .base = 0,
62 .size = sizeof(ehci_regs_t)
63 }
64};
65
66static const irq_cmd_t ehci_irq_commands[] = {
67 {
68 .cmd = CMD_PIO_READ_32,
69 .dstarg = 1,
70 .addr = NULL
71 },
72 {
73 .cmd = CMD_AND,
74 .srcarg = 1,
75 .dstarg = 2,
76 .value = 0
77 },
78 {
79 .cmd = CMD_PREDICATE,
80 .srcarg = 2,
81 .value = 2
82 },
83 {
84 .cmd = CMD_PIO_WRITE_A_32,
85 .srcarg = 1,
86 .addr = NULL
87 },
88 {
89 .cmd = CMD_ACCEPT
90 }
91};
92
93static errno_t hc_init_memory(hc_t *instance);
94
95/** Generate IRQ code.
96 * @param[out] ranges PIO ranges buffer.
97 * @param[in] hw_res Device's resources.
98 *
99 * @param[out] irq
100 *
101 * @return Error code.
102 */
103errno_t hc_gen_irq_code(irq_code_t *code, hc_device_t *hcd, const hw_res_list_parsed_t *hw_res, int *irq)
104{
105 assert(code);
106 assert(hw_res);
107 hc_t *instance = hcd_to_hc(hcd);
108
109 if (hw_res->irqs.count != 1 || hw_res->mem_ranges.count != 1)
110 return EINVAL;
111
112 addr_range_t regs = hw_res->mem_ranges.ranges[0];
113
114 if (RNGSZ(regs) < sizeof(ehci_regs_t))
115 return EOVERFLOW;
116
117 code->ranges = malloc(sizeof(ehci_pio_ranges));
118 if (code->ranges == NULL)
119 return ENOMEM;
120
121 code->cmds = malloc(sizeof(ehci_irq_commands));
122 if (code->cmds == NULL) {
123 free(code->ranges);
124 return ENOMEM;
125 }
126
127 code->rangecount = ARRAY_SIZE(ehci_pio_ranges);
128 code->cmdcount = ARRAY_SIZE(ehci_irq_commands);
129
130 memcpy(code->ranges, ehci_pio_ranges, sizeof(ehci_pio_ranges));
131 code->ranges[0].base = RNGABS(regs);
132
133 memcpy(code->cmds, ehci_irq_commands, sizeof(ehci_irq_commands));
134
135 ehci_regs_t *registers =
136 (ehci_regs_t *)(RNGABSPTR(regs) + EHCI_RD8(instance->caps->caplength));
137 code->cmds[0].addr = (void *) &registers->usbsts;
138 code->cmds[3].addr = (void *) &registers->usbsts;
139 EHCI_WR(code->cmds[1].value, EHCI_USED_INTERRUPTS);
140
141 usb_log_debug("Memory mapped regs at %p (size %zu), IRQ %d.",
142 RNGABSPTR(regs), RNGSZ(regs), hw_res->irqs.irqs[0]);
143
144 *irq = hw_res->irqs.irqs[0];
145 return EOK;
146}
147
148/** Initialize EHCI hc driver structure
149 *
150 * @param[in] instance Memory place for the structure.
151 * @param[in] regs Device's I/O registers range.
152 * @param[in] interrupts True if w interrupts should be used
153 * @return Error code
154 */
155errno_t hc_add(hc_device_t *hcd, const hw_res_list_parsed_t *hw_res)
156{
157 hc_t *instance = hcd_to_hc(hcd);
158 assert(hw_res);
159 if (hw_res->mem_ranges.count != 1 ||
160 hw_res->mem_ranges.ranges[0].size <
161 (sizeof(ehci_caps_regs_t) + sizeof(ehci_regs_t)))
162 return EINVAL;
163
164 errno_t ret = pio_enable_range(&hw_res->mem_ranges.ranges[0],
165 (void **)&instance->caps);
166 if (ret != EOK) {
167 usb_log_error("HC(%p): Failed to gain access to device "
168 "registers: %s.", instance, str_error(ret));
169 return ret;
170 }
171
172 usb_log_info("HC(%p): Device registers at %" PRIx64 " (%zuB) accessible.",
173 instance, hw_res->mem_ranges.ranges[0].address.absolute,
174 hw_res->mem_ranges.ranges[0].size);
175 instance->registers =
176 (void *)instance->caps + EHCI_RD8(instance->caps->caplength);
177 usb_log_info("HC(%p): Device control registers at %" PRIx64, instance,
178 hw_res->mem_ranges.ranges[0].address.absolute +
179 EHCI_RD8(instance->caps->caplength));
180
181 list_initialize(&instance->pending_endpoints);
182 fibril_mutex_initialize(&instance->guard);
183 fibril_condvar_initialize(&instance->async_doorbell);
184
185 ret = hc_init_memory(instance);
186 if (ret != EOK) {
187 usb_log_error("HC(%p): Failed to create EHCI memory structures:"
188 " %s.", instance, str_error(ret));
189 return ret;
190 }
191
192 usb_log_info("HC(%p): Initializing RH(%p).", instance, &instance->rh);
193 ehci_rh_init(
194 &instance->rh, instance->caps, instance->registers, &instance->guard,
195 "ehci rh");
196
197 ehci_bus_init(&instance->bus, instance);
198 hc_device_setup(hcd, (bus_t *) &instance->bus);
199 return EOK;
200}
201
202/** Safely dispose host controller internal structures
203 *
204 * @param[in] instance Host controller structure to use.
205 */
206int hc_gone(hc_device_t *hcd)
207{
208 hc_t *hc = hcd_to_hc(hcd);
209 endpoint_list_fini(&hc->async_list);
210 endpoint_list_fini(&hc->int_list);
211 dma_buffer_free(&hc->dma_buffer);
212 return EOK;
213}
214
215/** Quiesce host controller
216 *
217 * @param hcd Host controller device
218 */
219int hc_quiesce(hc_device_t *hcd)
220{
221 hc_t *instance = hcd_to_hc(hcd);
222
223 /*
224 * Turn off the HC if it's running, Reseting a running device is
225 * undefined
226 */
227 if (!(EHCI_RD(instance->registers->usbsts) & USB_STS_HC_HALTED_FLAG)) {
228 /* disable all interrupts */
229 EHCI_WR(instance->registers->usbintr, 0);
230 /* ack all interrupts */
231 EHCI_WR(instance->registers->usbsts, 0x3f);
232 /* Stop HC hw */
233 EHCI_WR(instance->registers->usbcmd, 0);
234 /* Wait until hc is halted */
235 while ((EHCI_RD(instance->registers->usbsts) & USB_STS_HC_HALTED_FLAG) == 0) {
236 fibril_usleep(1);
237 }
238 usb_log_info("HC(%p): EHCI turned off.", instance);
239 } else {
240 usb_log_info("HC(%p): EHCI was not running.", instance);
241 }
242
243 /* Hw initialization sequence, see page 53 (pdf 63) */
244 EHCI_SET(instance->registers->usbcmd, USB_CMD_HC_RESET_FLAG);
245 usb_log_info("HC(%p): Waiting for HW reset.", instance);
246 while (EHCI_RD(instance->registers->usbcmd) & USB_CMD_HC_RESET_FLAG) {
247 fibril_usleep(1);
248 }
249 usb_log_debug("HC(%p): HW reset OK.", instance);
250
251 return EOK;
252}
253
254void hc_enqueue_endpoint(hc_t *instance, const endpoint_t *ep)
255{
256 assert(instance);
257 assert(ep);
258 ehci_endpoint_t *ehci_ep = ehci_endpoint_get(ep);
259 usb_log_debug("HC(%p) enqueue EP(%d:%d:%s:%s)", instance,
260 ep->device->address, ep->endpoint,
261 usb_str_transfer_type_short(ep->transfer_type),
262 usb_str_direction(ep->direction));
263 switch (ep->transfer_type) {
264 case USB_TRANSFER_CONTROL:
265 case USB_TRANSFER_BULK:
266 endpoint_list_append_ep(&instance->async_list, ehci_ep);
267 break;
268 case USB_TRANSFER_INTERRUPT:
269 endpoint_list_append_ep(&instance->int_list, ehci_ep);
270 break;
271 case USB_TRANSFER_ISOCHRONOUS:
272 /* NOT SUPPORTED */
273 break;
274 }
275}
276
277void hc_dequeue_endpoint(hc_t *instance, const endpoint_t *ep)
278{
279 assert(instance);
280 assert(ep);
281 ehci_endpoint_t *ehci_ep = ehci_endpoint_get(ep);
282 usb_log_debug("HC(%p) dequeue EP(%d:%d:%s:%s)", instance,
283 ep->device->address, ep->endpoint,
284 usb_str_transfer_type_short(ep->transfer_type),
285 usb_str_direction(ep->direction));
286 switch (ep->transfer_type) {
287 case USB_TRANSFER_INTERRUPT:
288 endpoint_list_remove_ep(&instance->int_list, ehci_ep);
289 /* Fall through */
290 case USB_TRANSFER_ISOCHRONOUS:
291 /* NOT SUPPORTED */
292 return;
293 case USB_TRANSFER_CONTROL:
294 case USB_TRANSFER_BULK:
295 endpoint_list_remove_ep(&instance->async_list, ehci_ep);
296 break;
297 }
298 fibril_mutex_lock(&instance->guard);
299 usb_log_debug("HC(%p): Waiting for doorbell", instance);
300 EHCI_SET(instance->registers->usbcmd, USB_CMD_IRQ_ASYNC_DOORBELL);
301 fibril_condvar_wait(&instance->async_doorbell, &instance->guard);
302 usb_log_debug2("HC(%p): Got doorbell", instance);
303 fibril_mutex_unlock(&instance->guard);
304}
305
306errno_t ehci_hc_status(bus_t *bus_base, uint32_t *status)
307{
308 assert(bus_base);
309 assert(status);
310
311 ehci_bus_t *bus = (ehci_bus_t *) bus_base;
312 hc_t *hc = bus->hc;
313 assert(hc);
314
315 *status = 0;
316 if (hc->registers) {
317 *status = EHCI_RD(hc->registers->usbsts);
318 EHCI_WR(hc->registers->usbsts, *status);
319 }
320 usb_log_debug2("HC(%p): Read status: %x", hc, *status);
321 return EOK;
322}
323
324/** Add USB transfer to the schedule.
325 *
326 * @param[in] hcd HCD driver structure.
327 * @param[in] batch Batch representing the transfer.
328 * @return Error code.
329 */
330errno_t ehci_hc_schedule(usb_transfer_batch_t *batch)
331{
332 assert(batch);
333
334 ehci_bus_t *bus = (ehci_bus_t *) endpoint_get_bus(batch->ep);
335 hc_t *hc = bus->hc;
336 assert(hc);
337
338 /* Check for root hub communication */
339 if (batch->target.address == ehci_rh_get_address(&hc->rh)) {
340 usb_log_debug("HC(%p): Scheduling BATCH(%p) for RH(%p)",
341 hc, batch, &hc->rh);
342 return ehci_rh_schedule(&hc->rh, batch);
343 }
344
345 endpoint_t *const ep = batch->ep;
346 ehci_endpoint_t *const ehci_ep = ehci_endpoint_get(ep);
347 ehci_transfer_batch_t *ehci_batch = ehci_transfer_batch_get(batch);
348
349 int err;
350
351 if ((err = ehci_transfer_batch_prepare(ehci_batch)))
352 return err;
353
354 fibril_mutex_lock(&hc->guard);
355
356 if ((err = endpoint_activate_locked(ep, batch))) {
357 fibril_mutex_unlock(&hc->guard);
358 return err;
359 }
360
361 usb_log_debug("HC(%p): Committing BATCH(%p)", hc, batch);
362 ehci_transfer_batch_commit(ehci_batch);
363
364 /* Enqueue endpoint to the checked list */
365 usb_log_debug2("HC(%p): Appending BATCH(%p)", hc, batch);
366 list_append(&ehci_ep->pending_link, &hc->pending_endpoints);
367
368 fibril_mutex_unlock(&hc->guard);
369 return EOK;
370}
371
372/** Interrupt handling routine
373 *
374 * @param[in] hcd HCD driver structure.
375 * @param[in] status Value of the status register at the time of interrupt.
376 */
377void ehci_hc_interrupt(bus_t *bus_base, uint32_t status)
378{
379 assert(bus_base);
380
381 ehci_bus_t *bus = (ehci_bus_t *) bus_base;
382 hc_t *hc = bus->hc;
383 assert(hc);
384
385 usb_log_debug2("HC(%p): Interrupt: %" PRIx32, hc, status);
386 if (status & USB_STS_PORT_CHANGE_FLAG) {
387 ehci_rh_interrupt(&hc->rh);
388 }
389
390 if (status & USB_STS_IRQ_ASYNC_ADVANCE_FLAG) {
391 fibril_mutex_lock(&hc->guard);
392 usb_log_debug2("HC(%p): Signaling doorbell", hc);
393 fibril_condvar_broadcast(&hc->async_doorbell);
394 fibril_mutex_unlock(&hc->guard);
395 }
396
397 if (status & (USB_STS_IRQ_FLAG | USB_STS_ERR_IRQ_FLAG)) {
398 fibril_mutex_lock(&hc->guard);
399
400 usb_log_debug2("HC(%p): Scanning %zu pending endpoints", hc,
401 list_count(&hc->pending_endpoints));
402 list_foreach_safe(hc->pending_endpoints, current, next) {
403 ehci_endpoint_t *ep =
404 list_get_instance(current, ehci_endpoint_t, pending_link);
405
406 ehci_transfer_batch_t *batch =
407 ehci_transfer_batch_get(ep->base.active_batch);
408 assert(batch);
409
410 if (ehci_transfer_batch_check_completed(batch)) {
411 endpoint_deactivate_locked(&ep->base);
412 list_remove(current);
413 hc_reset_toggles(&batch->base, &ehci_ep_toggle_reset);
414 usb_transfer_batch_finish(&batch->base);
415 }
416 }
417 fibril_mutex_unlock(&hc->guard);
418
419 }
420
421 if (status & USB_STS_HOST_ERROR_FLAG) {
422 usb_log_fatal("HCD(%p): HOST SYSTEM ERROR!", hc);
423 //TODO do something here
424 }
425}
426
427/** EHCI hw initialization routine.
428 *
429 * @param[in] instance EHCI hc driver structure.
430 */
431int hc_start(hc_device_t *hcd)
432{
433 hc_t *instance = hcd_to_hc(hcd);
434 usb_log_debug("HC(%p): Starting HW.", instance);
435
436 /*
437 * Turn off the HC if it's running, Reseting a running device is
438 * undefined
439 */
440 if (!(EHCI_RD(instance->registers->usbsts) & USB_STS_HC_HALTED_FLAG)) {
441 /* disable all interrupts */
442 EHCI_WR(instance->registers->usbintr, 0);
443 /* ack all interrupts */
444 EHCI_WR(instance->registers->usbsts, 0x3f);
445 /* Stop HC hw */
446 EHCI_WR(instance->registers->usbcmd, 0);
447 /* Wait until hc is halted */
448 while ((EHCI_RD(instance->registers->usbsts) & USB_STS_HC_HALTED_FLAG) == 0) {
449 fibril_usleep(1);
450 }
451 usb_log_info("HC(%p): EHCI turned off.", instance);
452 } else {
453 usb_log_info("HC(%p): EHCI was not running.", instance);
454 }
455
456 /* Hw initialization sequence, see page 53 (pdf 63) */
457 EHCI_SET(instance->registers->usbcmd, USB_CMD_HC_RESET_FLAG);
458 usb_log_info("HC(%p): Waiting for HW reset.", instance);
459 while (EHCI_RD(instance->registers->usbcmd) & USB_CMD_HC_RESET_FLAG) {
460 fibril_usleep(1);
461 }
462 usb_log_debug("HC(%p): HW reset OK.", instance);
463
464 /* Use the lowest 4G segment */
465 EHCI_WR(instance->registers->ctrldssegment, 0);
466
467 /* Enable periodic list */
468 assert(instance->periodic_list);
469 uintptr_t phys_base =
470 addr_to_phys((void *)instance->periodic_list);
471 assert((phys_base & USB_PERIODIC_LIST_BASE_MASK) == phys_base);
472 EHCI_WR(instance->registers->periodiclistbase, phys_base);
473 EHCI_SET(instance->registers->usbcmd, USB_CMD_PERIODIC_SCHEDULE_FLAG);
474 usb_log_debug("HC(%p): Enabled periodic list.", instance);
475
476 /* Enable Async schedule */
477 phys_base = addr_to_phys((void *)instance->async_list.list_head);
478 assert((phys_base & USB_ASYNCLIST_MASK) == phys_base);
479 EHCI_WR(instance->registers->asynclistaddr, phys_base);
480 EHCI_SET(instance->registers->usbcmd, USB_CMD_ASYNC_SCHEDULE_FLAG);
481 usb_log_debug("HC(%p): Enabled async list.", instance);
482
483 /* Start hc and get all ports */
484 EHCI_SET(instance->registers->usbcmd, USB_CMD_RUN_FLAG);
485 EHCI_SET(instance->registers->configflag, USB_CONFIG_FLAG_FLAG);
486 usb_log_debug("HC(%p): HW started.", instance);
487
488 usb_log_debug2("HC(%p): Registers: "
489 "\tUSBCMD(%p): %x(0x00080000 = at least 1ms between interrupts)"
490 "\tUSBSTS(%p): %x(0x00001000 = HC halted)"
491 "\tUSBINT(%p): %x(0x0 = no interrupts)."
492 "\tCONFIG(%p): %x(0x0 = ports controlled by companion hc).",
493 instance,
494 &instance->registers->usbcmd, EHCI_RD(instance->registers->usbcmd),
495 &instance->registers->usbsts, EHCI_RD(instance->registers->usbsts),
496 &instance->registers->usbintr, EHCI_RD(instance->registers->usbintr),
497 &instance->registers->configflag, EHCI_RD(instance->registers->configflag));
498 /* Clear and Enable interrupts */
499 EHCI_WR(instance->registers->usbsts, EHCI_RD(instance->registers->usbsts));
500 EHCI_WR(instance->registers->usbintr, EHCI_USED_INTERRUPTS);
501
502 return EOK;
503}
504
505/**
506 * Setup roothub as a virtual hub.
507 */
508int hc_setup_roothub(hc_device_t *hcd)
509{
510 return hc_setup_virtual_root_hub(hcd, USB_SPEED_HIGH);
511}
512
513/** Initialize memory structures used by the EHCI hcd.
514 *
515 * @param[in] instance EHCI hc driver structure.
516 * @return Error code.
517 */
518errno_t hc_init_memory(hc_t *instance)
519{
520 assert(instance);
521 usb_log_debug2("HC(%p): Initializing Async list(%p).", instance,
522 &instance->async_list);
523 errno_t ret = endpoint_list_init(&instance->async_list, "ASYNC");
524 if (ret != EOK) {
525 usb_log_error("HC(%p): Failed to setup ASYNC list: %s",
526 instance, str_error(ret));
527 return ret;
528 }
529 /*
530 * Specs say "Software must set queue head horizontal pointer T-bits to
531 * a zero for queue heads in the asynchronous schedule" (4.4.0).
532 * So we must maintain circular buffer (all horizontal pointers
533 * have to be valid
534 */
535 endpoint_list_chain(&instance->async_list, &instance->async_list);
536
537 usb_log_debug2("HC(%p): Initializing Interrupt list (%p).", instance,
538 &instance->int_list);
539 ret = endpoint_list_init(&instance->int_list, "INT");
540 if (ret != EOK) {
541 usb_log_error("HC(%p): Failed to setup INT list: %s",
542 instance, str_error(ret));
543 endpoint_list_fini(&instance->async_list);
544 return ret;
545 }
546
547 /* Take 1024 periodic list heads, we ignore low mem options */
548 if (dma_buffer_alloc(&instance->dma_buffer, PAGE_SIZE)) {
549 usb_log_error("HC(%p): Failed to get ISO schedule page.",
550 instance);
551 endpoint_list_fini(&instance->async_list);
552 endpoint_list_fini(&instance->int_list);
553 return ENOMEM;
554 }
555 instance->periodic_list = instance->dma_buffer.virt;
556
557 usb_log_debug2("HC(%p): Initializing Periodic list.", instance);
558 for (unsigned i = 0; i < PAGE_SIZE / sizeof(link_pointer_t); ++i) {
559 /* Disable everything for now */
560 instance->periodic_list[i] =
561 LINK_POINTER_QH(addr_to_phys(instance->int_list.list_head));
562 }
563 return EOK;
564}
565
566/**
567 * @}
568 */
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