source: mainline/kernel/arch/sparc64/src/mm/tlb.c@ aca95f6b

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since aca95f6b was 44d0758, checked in by Jakub Jermar <jakub@…>, 19 years ago

Add option to compile the sparc64 kernel without the TTE_CV bit support.
The bit is not used by default now.
Enabling it may theoretically lead to physical memory inconsistencies until code that
mitigates the problem is written.
  • Property mode set to 100644
File size: 11.6 KB
Line 
1/*
2 * Copyright (C) 2005 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup sparc64mm
30 * @{
31 */
32/** @file
33 */
34
35#include <arch/mm/tlb.h>
36#include <mm/tlb.h>
37#include <mm/as.h>
38#include <mm/asid.h>
39#include <arch/mm/frame.h>
40#include <arch/mm/page.h>
41#include <arch/mm/mmu.h>
42#include <arch/interrupt.h>
43#include <interrupt.h>
44#include <arch.h>
45#include <print.h>
46#include <arch/types.h>
47#include <typedefs.h>
48#include <config.h>
49#include <arch/trap/trap.h>
50#include <arch/trap/exception.h>
51#include <panic.h>
52#include <arch/asm.h>
53
54#ifdef CONFIG_TSB
55#include <arch/mm/tsb.h>
56#endif
57
58static void dtlb_pte_copy(pte_t *t, bool ro);
59static void itlb_pte_copy(pte_t *t);
60static void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const char *str);
61static void do_fast_data_access_mmu_miss_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str);
62static void do_fast_data_access_protection_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str);
63
64char *context_encoding[] = {
65 "Primary",
66 "Secondary",
67 "Nucleus",
68 "Reserved"
69};
70
71void tlb_arch_init(void)
72{
73 /*
74 * Invalidate all non-locked DTLB and ITLB entries.
75 */
76 tlb_invalidate_all();
77
78 /*
79 * Clear both SFSRs.
80 */
81 dtlb_sfsr_write(0);
82 itlb_sfsr_write(0);
83}
84
85/** Insert privileged mapping into DMMU TLB.
86 *
87 * @param page Virtual page address.
88 * @param frame Physical frame address.
89 * @param pagesize Page size.
90 * @param locked True for permanent mappings, false otherwise.
91 * @param cacheable True if the mapping is cacheable, false otherwise.
92 */
93void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable)
94{
95 tlb_tag_access_reg_t tag;
96 tlb_data_t data;
97 page_address_t pg;
98 frame_address_t fr;
99
100 pg.address = page;
101 fr.address = frame;
102
103 tag.value = ASID_KERNEL;
104 tag.vpn = pg.vpn;
105
106 dtlb_tag_access_write(tag.value);
107
108 data.value = 0;
109 data.v = true;
110 data.size = pagesize;
111 data.pfn = fr.pfn;
112 data.l = locked;
113 data.cp = cacheable;
114#ifdef CONFIG_VIRT_IDX_CACHE
115 data.cv = cacheable;
116#endif /* CONFIG_VIRT_IDX_CACHE */
117 data.p = true;
118 data.w = true;
119 data.g = false;
120
121 dtlb_data_in_write(data.value);
122}
123
124/** Copy PTE to TLB.
125 *
126 * @param t Page Table Entry to be copied.
127 * @param ro If true, the entry will be created read-only, regardless of its w field.
128 */
129void dtlb_pte_copy(pte_t *t, bool ro)
130{
131 tlb_tag_access_reg_t tag;
132 tlb_data_t data;
133 page_address_t pg;
134 frame_address_t fr;
135
136 pg.address = t->page;
137 fr.address = t->frame;
138
139 tag.value = 0;
140 tag.context = t->as->asid;
141 tag.vpn = pg.vpn;
142
143 dtlb_tag_access_write(tag.value);
144
145 data.value = 0;
146 data.v = true;
147 data.size = PAGESIZE_8K;
148 data.pfn = fr.pfn;
149 data.l = false;
150 data.cp = t->c;
151#ifdef CONFIG_VIRT_IDX_CACHE
152 data.cv = t->c;
153#endif /* CONFIG_VIRT_IDX_CACHE */
154 data.p = t->k; /* p like privileged */
155 data.w = ro ? false : t->w;
156 data.g = t->g;
157
158 dtlb_data_in_write(data.value);
159}
160
161/** Copy PTE to ITLB.
162 *
163 * @param t Page Table Entry to be copied.
164 */
165void itlb_pte_copy(pte_t *t)
166{
167 tlb_tag_access_reg_t tag;
168 tlb_data_t data;
169 page_address_t pg;
170 frame_address_t fr;
171
172 pg.address = t->page;
173 fr.address = t->frame;
174
175 tag.value = 0;
176 tag.context = t->as->asid;
177 tag.vpn = pg.vpn;
178
179 itlb_tag_access_write(tag.value);
180
181 data.value = 0;
182 data.v = true;
183 data.size = PAGESIZE_8K;
184 data.pfn = fr.pfn;
185 data.l = false;
186 data.cp = t->c;
187#ifdef CONFIG_VIRT_IDX_CACHE
188 data.cv = t->c;
189#endif /* CONFIG_VIRT_IDX_CACHE */
190 data.p = t->k; /* p like privileged */
191 data.w = false;
192 data.g = t->g;
193
194 itlb_data_in_write(data.value);
195}
196
197/** ITLB miss handler. */
198void fast_instruction_access_mmu_miss(int n, istate_t *istate)
199{
200 uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);
201 pte_t *t;
202
203 page_table_lock(AS, true);
204 t = page_mapping_find(AS, va);
205 if (t && PTE_EXECUTABLE(t)) {
206 /*
207 * The mapping was found in the software page hash table.
208 * Insert it into ITLB.
209 */
210 t->a = true;
211 itlb_pte_copy(t);
212#ifdef CONFIG_TSB
213 itsb_pte_copy(t);
214#endif
215 page_table_unlock(AS, true);
216 } else {
217 /*
218 * Forward the page fault to the address space page fault handler.
219 */
220 page_table_unlock(AS, true);
221 if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
222 do_fast_instruction_access_mmu_miss_fault(istate, __FUNCTION__);
223 }
224 }
225}
226
227/** DTLB miss handler.
228 *
229 * Note that some faults (e.g. kernel faults) were already resolved
230 * by the low-level, assembly language part of the fast_data_access_mmu_miss
231 * handler.
232 */
233void fast_data_access_mmu_miss(int n, istate_t *istate)
234{
235 tlb_tag_access_reg_t tag;
236 uintptr_t va;
237 pte_t *t;
238
239 tag.value = dtlb_tag_access_read();
240 va = tag.vpn << PAGE_WIDTH;
241
242 if (tag.context == ASID_KERNEL) {
243 if (!tag.vpn) {
244 /* NULL access in kernel */
245 do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__);
246 }
247 do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected kernel page fault.");
248 }
249
250 page_table_lock(AS, true);
251 t = page_mapping_find(AS, va);
252 if (t) {
253 /*
254 * The mapping was found in the software page hash table.
255 * Insert it into DTLB.
256 */
257 t->a = true;
258 dtlb_pte_copy(t, true);
259#ifdef CONFIG_TSB
260 dtsb_pte_copy(t, true);
261#endif
262 page_table_unlock(AS, true);
263 } else {
264 /*
265 * Forward the page fault to the address space page fault handler.
266 */
267 page_table_unlock(AS, true);
268 if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
269 do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__);
270 }
271 }
272}
273
274/** DTLB protection fault handler. */
275void fast_data_access_protection(int n, istate_t *istate)
276{
277 tlb_tag_access_reg_t tag;
278 uintptr_t va;
279 pte_t *t;
280
281 tag.value = dtlb_tag_access_read();
282 va = tag.vpn << PAGE_WIDTH;
283
284 page_table_lock(AS, true);
285 t = page_mapping_find(AS, va);
286 if (t && PTE_WRITABLE(t)) {
287 /*
288 * The mapping was found in the software page hash table and is writable.
289 * Demap the old mapping and insert an updated mapping into DTLB.
290 */
291 t->a = true;
292 t->d = true;
293 dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, va);
294 dtlb_pte_copy(t, false);
295#ifdef CONFIG_TSB
296 dtsb_pte_copy(t, false);
297#endif
298 page_table_unlock(AS, true);
299 } else {
300 /*
301 * Forward the page fault to the address space page fault handler.
302 */
303 page_table_unlock(AS, true);
304 if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
305 do_fast_data_access_protection_fault(istate, tag, __FUNCTION__);
306 }
307 }
308}
309
310/** Print contents of both TLBs. */
311void tlb_print(void)
312{
313 int i;
314 tlb_data_t d;
315 tlb_tag_read_reg_t t;
316
317 printf("I-TLB contents:\n");
318 for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
319 d.value = itlb_data_access_read(i);
320 t.value = itlb_tag_read_read(i);
321
322 printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
323 i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
324 }
325
326 printf("D-TLB contents:\n");
327 for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
328 d.value = dtlb_data_access_read(i);
329 t.value = dtlb_tag_read_read(i);
330
331 printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
332 i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
333 }
334
335}
336
337void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const char *str)
338{
339 fault_if_from_uspace(istate, "%s\n", str);
340 dump_istate(istate);
341 panic("%s\n", str);
342}
343
344void do_fast_data_access_mmu_miss_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str)
345{
346 uintptr_t va;
347
348 va = tag.vpn << PAGE_WIDTH;
349
350 fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, tag.context);
351 dump_istate(istate);
352 printf("Faulting page: %p, ASID=%d\n", va, tag.context);
353 panic("%s\n", str);
354}
355
356void do_fast_data_access_protection_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str)
357{
358 uintptr_t va;
359
360 va = tag.vpn << PAGE_WIDTH;
361
362 fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, tag.context);
363 printf("Faulting page: %p, ASID=%d\n", va, tag.context);
364 dump_istate(istate);
365 panic("%s\n", str);
366}
367
368void dump_sfsr_and_sfar(void)
369{
370 tlb_sfsr_reg_t sfsr;
371 uintptr_t sfar;
372
373 sfsr.value = dtlb_sfsr_read();
374 sfar = dtlb_sfar_read();
375
376 printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, fv=%d\n",
377 sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, sfsr.ow, sfsr.fv);
378 printf("DTLB SFAR: address=%p\n", sfar);
379
380 dtlb_sfsr_write(0);
381}
382
383/** Invalidate all unlocked ITLB and DTLB entries. */
384void tlb_invalidate_all(void)
385{
386 int i;
387 tlb_data_t d;
388 tlb_tag_read_reg_t t;
389
390 for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
391 d.value = itlb_data_access_read(i);
392 if (!d.l) {
393 t.value = itlb_tag_read_read(i);
394 d.v = false;
395 itlb_tag_access_write(t.value);
396 itlb_data_access_write(i, d.value);
397 }
398 }
399
400 for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
401 d.value = dtlb_data_access_read(i);
402 if (!d.l) {
403 t.value = dtlb_tag_read_read(i);
404 d.v = false;
405 dtlb_tag_access_write(t.value);
406 dtlb_data_access_write(i, d.value);
407 }
408 }
409
410}
411
412/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
413 *
414 * @param asid Address Space ID.
415 */
416void tlb_invalidate_asid(asid_t asid)
417{
418 tlb_context_reg_t pc_save, ctx;
419
420 /* switch to nucleus because we are mapped by the primary context */
421 nucleus_enter();
422
423 ctx.v = pc_save.v = mmu_primary_context_read();
424 ctx.context = asid;
425 mmu_primary_context_write(ctx.v);
426
427 itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
428 dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
429
430 mmu_primary_context_write(pc_save.v);
431
432 nucleus_leave();
433}
434
435/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.
436 *
437 * @param asid Address Space ID.
438 * @param page First page which to sweep out from ITLB and DTLB.
439 * @param cnt Number of ITLB and DTLB entries to invalidate.
440 */
441void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
442{
443 int i;
444 tlb_context_reg_t pc_save, ctx;
445
446 /* switch to nucleus because we are mapped by the primary context */
447 nucleus_enter();
448
449 ctx.v = pc_save.v = mmu_primary_context_read();
450 ctx.context = asid;
451 mmu_primary_context_write(ctx.v);
452
453 for (i = 0; i < cnt; i++) {
454 itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE);
455 dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE);
456 }
457
458 mmu_primary_context_write(pc_save.v);
459
460 nucleus_leave();
461}
462
463/** @}
464 */
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