source: mainline/boot/arch/sparc32/include/arch.h@ 32e8cd1

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 32e8cd1 was f6f22cdb, checked in by Martin Decky <martin@…>, 12 years ago

code revision
coding style changes

  • Property mode set to 100644
File size: 2.1 KB
Line 
1/*
2 * Copyright (c) 2013 Jakub Klama
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef BOOT_sparc32_ARCH_H
30#define BOOT_sparc32_ARCH_H
31
32#define PTL0_ENTRIES 256
33#define PTL0_SHIFT 24
34#define PTL0_SIZE (1 << 24)
35#define PTL0_ENTRY_SIZE 4
36
37/* ASI assignments: */
38#define ASI_CACHEMISS 0x01
39#define ASI_CACHECTRL 0x02
40#define ASI_MMUREGS 0x19
41#define ASI_MMUBYPASS 0x1c
42
43/*
44 * Address where the boot stage image starts
45 * (beginning of usable physical memory).
46 */
47
48#define BOOT_BASE 0x40000000
49#define BOOT_OFFSET (BOOT_BASE + 0xa00000)
50
51#define PA_OFFSET 0x40000000
52
53#ifndef __ASM__
54 #define PA2KA(addr) (((uintptr_t) (addr)) + PA_OFFSET)
55#else
56 #define PA2KA(addr) ((addr) + PA_OFFSET)
57#endif
58
59#endif
60
61/** @}
62 */
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