source: mainline/arch/amd64/src/fpu_context.c@ ffc277e

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since ffc277e was ffc277e, checked in by Ondrej Palkovsky <ondrap@…>, 20 years ago

Cleanup of makefiles to have common options in one main makefile.

Add simple build process for different simulators for MIPS.
Added FPU context & lazy FPU context switching to MIPS.
Cleanup of MIPS linker script.
Moved MIPS kernel above 1MB. Not tested on real machine yet, but it might help.

There is something broken with gcc inlined memcpy (either simulator or gcc), it is disabled on BigEndian mips now.

  • Property mode set to 100644
File size: 2.0 KB
RevLine 
[1141c1a]1/*
[3396f59]2 * Copyright (C) 2005 Jakub Vana
[1141c1a]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
[3396f59]27 *
[1141c1a]28 */
29
[3396f59]30#include <fpu_context.h>
31#include <arch.h>
32#include <cpu.h>
33
34void fpu_context_save(fpu_context_t *fctx)
35{
[b49f4ae]36 /* Align on 16-byte boundary */
[3396f59]37 if (((__u64)fctx) & 0xf)
38 fctx = (fpu_context_t *)((((__u64)fctx) | 0xf) + 1);
[1141c1a]39
[3396f59]40 __asm__ volatile (
41 "fxsave %0"
42 : "=m"(*fctx)
43 );
44}
[1141c1a]45
[b49f4ae]46void fpu_context_restore(fpu_context_t *fctx)
[3396f59]47{
[ffc277e]48 /* Align on 16-byte boundary */
[3396f59]49 if (((__u64)fctx) & 0xf)
50 fctx = (fpu_context_t *)((((__u64)fctx) | 0xf) + 1);
51 __asm__ volatile (
52 "fxrstor %0"
53 : "=m"(*fctx)
54 );
55}
[1141c1a]56
[3396f59]57void fpu_init(void)
58{
[ffc277e]59 /* TODO: Zero all SSE, MMX etc. registers */
[3396f59]60 __asm__ volatile (
61 "fninit;"
62 );
63}
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